2025-04-28 01:31:22 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.80.20:5700'
2025-04-28 01:31:22 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.80.20:5802)
2025-04-28 01:31:22 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.80.20:5801)
2025-04-28 01:31:22 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.80.22:6700'
2025-04-28 01:31:22 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.80.22:6802)
2025-04-28 01:31:22 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.80.22:6801)
2025-04-28 01:31:22 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.80.20:5700/1'
2025-04-28 01:31:22 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.80.20:5804)
2025-04-28 01:31:22 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.80.20:5803)
2025-04-28 01:31:22 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.80.20:5700/2'
2025-04-28 01:31:22 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.80.20:5806)
2025-04-28 01:31:22 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.80.20:5805)
2025-04-28 01:31:22 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.80.20:5700/3'
2025-04-28 01:31:22 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.80.20:5808)
2025-04-28 01:31:22 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.80.20:5807)
2025-04-28 01:31:22 [INFO] fake_trx.py:423 Init complete
2025-04-28 01:31:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 0 -> 1
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 0 -> 1
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 0 -> 1
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 0 -> 1
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:31:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:31:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:31:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:31:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:31:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:31:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:31:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:31:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:31:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:31:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 01:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
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2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:31:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:31:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:31:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:31:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:31:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:31:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:31:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:31:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:31:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:31:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:31:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:31:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:31:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:32:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:32:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:32:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:32:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:32:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:32:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:32:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:32:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:32:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:32:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:32:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:32:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:32:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:32:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:32:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:32:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:32:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:32:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:32:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 01:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 01:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 01:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 01:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 01:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 01:32:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 01:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 01:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 01:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 01:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 01:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 01:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 01:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 01:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 01:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 01:32:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 01:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 01:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 01:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 01:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 01:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 01:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 01:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:32:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 01:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 01:32:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 01:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 01:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 01:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 01:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 01:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 01:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 01:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 01:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 01:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 01:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 01:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 01:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 01:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 01:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 01:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 01:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 01:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 01:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 01:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 01:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 01:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 01:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 01:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 01:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 01:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 01:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 01:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 01:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 01:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 01:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 01:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 01:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 01:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 01:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 01:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 01:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 01:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 01:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 01:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 01:33:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 01:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 01:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 01:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 01:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 01:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 01:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 01:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 01:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 01:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 01:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 01:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 01:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 01:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 01:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 01:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 01:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:27 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=16554 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 01:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 01:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 01:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 01:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 01:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 01:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 01:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 01:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 01:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 01:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 01:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 01:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 01:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 01:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 01:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 01:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 01:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 01:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 01:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 01:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 01:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 01:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 01:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-28 01:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=19310 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:33:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:33:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=19311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:33:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:33:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:33:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:33:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:33:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:33:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:33:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:33:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:33:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:33:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:33:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:33:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:33:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:33:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:33:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:33:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:33:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:33:50 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:33:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:33:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:33:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:33:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:34:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:34:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:34:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:34:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:34:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:34:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:34:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:34:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:34:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:13 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1885 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:34:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:34:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:34:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:34:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:34:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:34:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:34:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:34:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:34:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:34:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:34:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:34:40 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:34:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:40 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:34:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:01 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=4680 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 01:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 01:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 01:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 01:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 01:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 01:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 01:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 01:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 01:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 01:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 01:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 01:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 01:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 01:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 01:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 01:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 01:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 01:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:23 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=9399 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 01:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 01:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 01:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 01:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 01:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 01:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 01:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 01:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 01:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 01:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 01:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 01:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 01:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 01:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 01:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 01:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 01:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 01:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 01:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 01:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 01:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 01:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 01:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 01:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 01:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 01:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 01:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 01:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 01:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 01:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 01:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 01:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 01:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 01:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 01:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 01:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 01:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 01:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 01:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 01:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 01:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 01:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 01:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 01:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 01:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 01:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 01:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 01:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 01:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 01:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 01:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 01:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 01:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 01:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 01:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 01:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 01:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 01:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 01:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 01:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 01:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 01:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 01:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:35:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:35:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 01:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 01:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 01:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 01:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 01:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 01:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 01:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 01:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 01:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 01:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 01:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 01:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 01:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 01:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:36:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:36:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:36:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:36:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:36:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:36:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:36:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:36:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:36:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:36:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:36:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:36:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:36:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:36:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:36:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:36:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:36:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:36:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:36:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:36:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:36:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:38 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=4807 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 01:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 01:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 01:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 01:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 01:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 01:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 01:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 01:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 01:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 01:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 01:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:36:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 01:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 01:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 01:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 01:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 01:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 01:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 01:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 01:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 01:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 01:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 01:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 01:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 01:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 01:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 01:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 01:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 01:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 01:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 01:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 01:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 01:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 01:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 01:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 01:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 01:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 01:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 01:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 01:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 01:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 01:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 01:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 01:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 01:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 01:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 01:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 01:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 01:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 01:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 01:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 01:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 01:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 01:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 01:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 01:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 01:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 01:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 01:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 01:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 01:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 01:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 01:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 01:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 01:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 01:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 01:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 01:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 01:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 01:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 01:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 01:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 01:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 01:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 01:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 01:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 01:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 01:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 01:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 01:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 01:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 01:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 01:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 01:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 01:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 01:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 01:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 01:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 01:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 01:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 01:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 01:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 01:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 01:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 01:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 01:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 01:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 01:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 01:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 01:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 01:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 01:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 01:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:37:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:37:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:37:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:37:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:37:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:37:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:37:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:37:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:37:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:37:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:37:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:37:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:37:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:37:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:37:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:37:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:37:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:37:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:37:56 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:37:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:37:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:38:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:38:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:38:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:38:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5913 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5913 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5913 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5913 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5913 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5914 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:38:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:38:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:38:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:38:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:38:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:38:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:38:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:38:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:32 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:32 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:38:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:40 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2549 tn=0 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:40 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2549 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:38:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:38:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:38:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:38:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:38:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:38:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:39:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:39:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:39:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:39:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:39:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:39:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:39:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:39:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:39:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:07 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:07 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:39:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:11 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1664 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:11 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1664 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:11 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1664 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:39:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:39:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:39:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:27 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=5148 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:35 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=6829 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:35 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=6829 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 01:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:38 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=7543 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 01:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 01:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 01:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 01:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 01:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 01:39:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 01:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 01:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 01:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 01:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 01:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 01:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 01:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 01:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 01:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 01:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 01:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 01:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 01:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:39:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:39:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:39:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10187 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:39:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:39:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:39:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:39:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:39:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:39:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:39:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:39:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:39:56 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:39:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:39:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:39:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:39:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:39:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2019 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2019 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2020 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:40:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:40:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:40:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:40:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:40:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2024 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:40:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:40:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:40:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:40:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:40:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:40:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:40:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:40:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:40:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:40:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:40:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:40:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:40:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:40:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2181 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2182 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:40:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:40:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:40:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:40:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:41:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:41:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:41:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=570 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:41:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:41:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:41:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:41:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:41:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:41:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1282 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:41:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:41:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1184 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1184 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1184 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1184 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1184 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:41:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:41:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:41:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:41:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:41:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:41:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:41:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:41:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:41:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3296 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:42:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:42:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:42:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:42:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1852 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:42:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:42:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:42:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:42:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:42:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:42:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:42:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:42:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:42:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:42:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:42:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:42:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:42:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:42:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:42:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:42:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:42:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:42:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3575 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:43:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:43:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:43:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:43:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:43:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:43:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:43:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:43:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:43:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3572 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:43:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:43:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:32 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:43:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:43:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:43:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:43:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:43:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:43:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:43:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:43:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:43:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:43:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:43:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:43:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:43:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:43:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:43:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:43:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3592 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:44:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:44:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:44:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:44:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:44:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:44:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:44:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:44:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:44:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:44:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:44:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:44:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:44:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:44:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:44:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:44:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:44:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:44:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:44:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:44:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:44:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:44:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:44:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:44:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:44:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:45:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 01:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 01:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 01:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 01:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 01:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 01:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 01:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 01:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 01:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 01:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 01:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 01:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 01:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 01:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 01:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 01:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 01:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 01:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 01:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 01:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 01:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 01:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 01:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 01:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 01:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 01:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 01:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 01:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 01:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:27 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=10492 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 01:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 01:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 01:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 01:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 01:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 01:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 01:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 01:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 01:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 01:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 01:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 01:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 01:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 01:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 01:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 01:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 01:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 01:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 01:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 01:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 01:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 01:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 01:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 01:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 01:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 01:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 01:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 01:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 01:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 01:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 01:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:45:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:45:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:45:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:45:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:45:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:45:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:45:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:45:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:45:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:45:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:45:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:45:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:45:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:45:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:45:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:46:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:46:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:46:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:46:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:46:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:46:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:46:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:46:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1847 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:46:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:46:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:46:24 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:46:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:24 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:46:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:46:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:46:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:46:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:46:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:46:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:46:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:46:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:46:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:46:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:46:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1503 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:46:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:46:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:46:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:46:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:46:50 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:46:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:46:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:46:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:46:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:46:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:46:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:47:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:47:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:47:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:47:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:47:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:47:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:47:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:47:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:47:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:47:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:47:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:47:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:47:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:47:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:47:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:47:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4365 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:47:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:47:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:47:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:47:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=126 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=127 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=128 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:30 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:31 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=302 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=302 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=302 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=302 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=302 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:47:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:47:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:47:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:47:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:47:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=305 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=305 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=305 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=305 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=305 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:47:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:47:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:47:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:47:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:47:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:47:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:47:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:47:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:47:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:47:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:47:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:47:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:48:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:48:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:48:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:48:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:48:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:48:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:48:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:48:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:48:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:48:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:48:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:48:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:48:22 [DEBUG] fake_trx.py:263 (MS@172.18.80.22:6700) Recv SETTA cmd
2025-04-28 01:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:48:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4326 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4326 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4326 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4326 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4326 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:48:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:48:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:48:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:48:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:48:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:48:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:48:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:48:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:48:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:48:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:48:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:49:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:49:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:49:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:49:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:49:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1667 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:49:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:49:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:49:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:49:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:49:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2263 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2264 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:49:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:49:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:49:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:49:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:49:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:49:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:49:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:49:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:49:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:49:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:49:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:49:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:49:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:49:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:49:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:49:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2870 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:50:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:50:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:50:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:50:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:50:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:50:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:50:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:50:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:50:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:50:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:50:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:50:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:50:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:50:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:50:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:50:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:50:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:50:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3739 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:50:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:50:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:50:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:50:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:50:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:50:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:50:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:50:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:50:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:50:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:51:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:51:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:51:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:51:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:51:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:51:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:51:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:51:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:51:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:51:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:51:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:51:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:51:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:51:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:51:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:51:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:51:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:51:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:51:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4731 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:51:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:51:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:51:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:51:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:51:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:51:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:51:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:51:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:51:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:51:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:51:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:51:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:51:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:52:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:52:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:52:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:52:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:52:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:52:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:52:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:52:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:52:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:52:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:52:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:52:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:52:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:52:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:52:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:52:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:52:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:52:57 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:52:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:52:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:52:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:52:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:53:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:53:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:53:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:53:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:53:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:53:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:53:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:53:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:53:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:53:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:53:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:53:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:53:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:53:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:53:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:53:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:53:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:53:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:53:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:53:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:53:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:53:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:53:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:53:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:53:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1850 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:53:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:53:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:53:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:53:35 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:53:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:53:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:53:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:53:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:53:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:53:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:53:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:53:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:53:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:53:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:53:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:53:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:53:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:53:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:54:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:54:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:54:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:54:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:54:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:54:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:54:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:54:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:54:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:54:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:54:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:54:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:54:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:54:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:54:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:54:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:54:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:54:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:54:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:54:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:54:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1831 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:54:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:54:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:54:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:54:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:54:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:54:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:54:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:54:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:54:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3553 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3554 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:19 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:24 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:24 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:35 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:55:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:55:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:55:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:55:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:55:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:55:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:55:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:55:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:55:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:55:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:55:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:55:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 01:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 01:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 01:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 01:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 01:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 01:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 01:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 01:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 01:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 01:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 01:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 01:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 01:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 01:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 01:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 01:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 01:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 01:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 01:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 01:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 01:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 01:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 01:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 01:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 01:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 01:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 01:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 01:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 01:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 01:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 01:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 01:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 01:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 01:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 01:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 01:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 01:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 01:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 01:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 01:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 01:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 01:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 01:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 01:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 01:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 01:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 01:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 01:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 01:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 01:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 01:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:56:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:56:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:56:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:56:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:56:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:56:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:56:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:56:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=756 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=756 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=756 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=756 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=756 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:56:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:56:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:56:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:56:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:56:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:56:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:56:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:56:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:56:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:56:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:56:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:56:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:56:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:56:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:56:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:56:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:56:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:56:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:56:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:56:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:56:57 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:56:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:57:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:57:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:57:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:57:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:57:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:57:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:57:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=965 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=966 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:32 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:57:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:57:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:57:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:57:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=776 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=776 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=776 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=776 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=776 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:57:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:57:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:57:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:57:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:57:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:57:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:57:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:57:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:58:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:58:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:58:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:58:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:58:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:58:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:58:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:58:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:58:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:58:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:58:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:58:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:58:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:58:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:58:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1843 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1844 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:58:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:58:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:58:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:58:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:58:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:58:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:58:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:58:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:58:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:58:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:58:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:58:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:58:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:58:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1202 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:58:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:58:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:58:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:58:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1340 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:59:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:59:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 01:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 01:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 01:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 01:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 01:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2021 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 01:59:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 01:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 01:59:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 01:59:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 01:59:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 01:59:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 01:59:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 01:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 01:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 01:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 01:59:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 01:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 01:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 01:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 01:59:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 01:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 01:59:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 01:59:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 01:59:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 01:59:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 01:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 01:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 01:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 01:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:00:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:00:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:00:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:00:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=872 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:17 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:00:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:00:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:00:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:50 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:00:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:00:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:00:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:00:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:00:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:00:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:00:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:00:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:00:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:00:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=548 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:17 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=722 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:01:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:01:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:01:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:01:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:01:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:01:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:01:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:01:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:01:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:01:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:02:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:02:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:02:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:02:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:18 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=763 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:02:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:02:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:02:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:02:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:02:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:02:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:02:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:02:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:03:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:03:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:03:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:39 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 02:03:39 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 200
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:40 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 02:03:40 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 0
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:46 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 02:03:46 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 200
2025-04-28 02:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 02:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 02:03:48 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 0
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=465 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:03:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:03:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:03:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:03:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:03:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:03:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:03:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:03:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:03:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:04:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:04:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:04:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:04:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:04:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:04:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:04:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:04:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:04:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:04:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9183 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9183 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9183 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9183 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9183 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:04:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:04:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:04:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:04:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:04:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:04:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:04:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:04:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:04:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:04:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:04:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:04:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:05:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:05:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:05:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:05:06 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:05:06 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:05:06 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:05:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:05:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:05:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:05:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:05:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:05:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:05:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:05:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:05:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:05:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:05:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:05:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:05:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:05:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:05:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1736 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:05:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:05:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:05:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:05:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:05:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:05:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:05:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:05:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:05:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:06:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:06:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:06:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:06:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:06:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:06:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:14 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:14 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:14 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:07:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:40 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:40 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:07:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:07:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:07:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:07:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:07:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:07:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:07:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:07:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:07:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:07:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:08:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:08:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:08:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:08:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:08:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:08:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:08:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:08:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:08:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:16 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1221 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:16 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1221 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:16 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1221 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:08:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3706 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3706 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3706 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3706 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3706 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:08:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:08:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:08:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:08:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:08:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:08:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:08:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:08:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:09:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:09:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:09:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5144 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:09:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:09:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:09:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:09:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:09:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:09:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:09:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:09:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:09:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:09:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:09:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:09:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:09:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:09:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:09:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:09:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:09:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:09:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:09:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:09:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:09:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:09:56 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:09:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:09:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:09:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:09:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:10:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:10:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:10:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:10:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:10:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:10:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:10:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:10:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:10:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:10:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:10:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:10:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:17 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:10:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:10:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:10:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:10:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:10:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:10:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:10:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:10:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:10:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:10:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:10:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:10:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:10:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:10:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:10:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:10:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:10:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:10:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:10:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:10:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:10:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:10:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:10:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:10:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:10:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:10:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:10:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:10:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:10:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:10:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:10:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:10:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:10:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:10:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:10:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:10:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:10:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:10:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:10:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:10:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:10:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:10:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:10:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:10:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:10:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:10:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:10:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:10:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:10:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:10:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:10:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:10:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:10:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:10:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:10:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:10:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:10:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:10:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:10:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:10:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:10:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:10:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:10:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:10:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:10:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:10:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:10:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:10:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:10:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:10:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:10:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:10:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:06 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:06 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:06 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1037 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1038 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:11:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1041 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1042 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=597 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:48 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:11:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:11:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:11:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:11:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:11:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:11:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:11:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:11:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:11:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=296 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:12:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:12:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=235 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=235 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=235 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=235 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=235 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=236 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:12:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=994 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=284 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:12:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:12:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:12:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:12:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:12:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:12:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:12:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:12:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:12:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:12:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:12:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:13:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:13:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:13:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:13:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:13:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:13:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:13:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:13:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:13:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:13:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:13:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:17 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:13:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:13:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:13:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:13:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:13:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:13:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:13:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:13:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:13:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:13:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3941 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3942 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:13:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:13:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:13:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:13:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:13:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:13:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:13:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:13:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:13:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:13:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:13:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2797 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:14:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:14:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:14:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:14:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:14:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:14:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:14:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:14:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:14:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:14:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:14:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:14:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:14:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:14:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:14:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:14:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:14:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:14:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:14:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:14:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:14:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:14:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:14:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:14:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:14:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:14:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:14:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:14:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:14:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:14:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:14:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:14:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:14:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:14:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:15:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:15:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:15:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:15:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:15:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:15:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:15:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:15:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:15:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:15:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:15:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:15:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:15:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:15:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:15:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:15:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:15:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:15:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:15:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:15:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:15:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:15:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:15:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:15:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:15:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:15:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:15:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:15:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:16:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:16:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:16:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:16:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:16:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:16:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:16:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:16:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:16:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:16:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:16:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:16:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:16:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:16:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:16:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:16:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:16:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:16:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:16:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:16:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:16:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:16:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:17:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:17:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:17:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:17:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:17:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:17:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:17:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:17:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:17:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:17:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:17:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:17:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:17:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:17:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:17:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2479 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:17:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:17:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:17:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:17:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:17:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:17:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:17:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:17:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:18:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:18:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:18:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:18:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:18:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:18:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:18:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:18:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:18:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:18:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:18:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2256 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2256 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2256 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2256 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2257 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:18:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:18:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:18:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:18:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:18:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:18:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:18:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:18:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:18:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:18:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2675 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2675 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2675 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2675 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2675 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:18:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2676 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:19:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:19:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:19:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:19:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:19:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:19:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:19:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:19:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:19:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:19:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:19:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:19:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:19:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:19:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:19:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:19:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:19:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:19:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:20:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:20:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:20:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:20:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:20:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:20:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:20:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:20:24 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:20:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:20:24 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:20:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:20:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:20:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:20:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:20:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:20:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:20:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:20:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:20:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:20:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:20:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:20:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:20:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:20:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:20:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:20:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:21:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:21:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:21:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:21:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:21:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:21:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:21:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:21:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:21:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:21:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:21:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:21:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:21:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:21:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:21:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:21:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:21:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:21:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:21:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2467 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:21:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:21:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:21:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:21:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:21:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:21:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:21:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:21:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:21:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:21:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:21:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:21:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:21:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2247 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:22:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:22:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:22:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:22:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:22:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:22:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:22:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:22:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:22:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:22:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:22:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:22:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:22:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:22:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:22:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:22:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:22:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:22:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:22:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:22:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:22:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:22:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:22:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:22:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:22:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:22:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3327 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3327 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3327 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3327 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3327 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:22:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3328 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:23:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:23:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:23:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:23:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:23:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:23:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:23:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:23:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:23:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:23:17 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:23:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:17 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:23:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4453 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4454 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:23:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:23:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:23:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:23:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:23:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:23:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:23:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:23:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:23:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:23:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:23:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:23:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:24:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:24:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4439 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:24:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:24:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:24:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:24:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:24:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:24:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:24:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:24:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:24:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:24:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:24:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:24:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:24:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:24:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:24:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:24:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:24:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:24:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:24:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:24:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:24:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:24:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:24:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:24:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:24:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:25:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:25:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:25:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:25:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:25:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:25:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:25:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:25:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:25:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=635 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:25:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:25:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:25:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:25:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:25:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:25:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:25:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:25:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:25:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:25:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:25:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:25:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:25:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:25:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 02:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 02:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 02:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 02:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 02:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 02:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 02:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 02:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 02:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 02:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 02:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 02:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 02:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 02:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 02:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 02:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 02:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 02:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 02:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 02:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 02:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 02:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 02:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 02:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 02:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 02:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 02:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 02:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 02:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 02:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 02:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 02:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 02:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 02:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 02:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 02:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 02:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:26:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:26:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:26:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:26:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:26:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:26:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:26:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:26:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:26:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:26:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:26:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:26:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:26:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:26:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:26:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:26:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:26:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:26:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:26:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:26:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:26:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:26:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3847 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3847 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3847 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3847 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3847 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:26:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3848 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:27:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:27:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:27:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:27:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2921 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:27:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:27:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:27:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:27:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:27:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:27:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:27:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:27:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:27:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:27:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2995 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2995 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2995 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2995 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2995 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:27:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:27:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:27:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:27:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:27:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:27:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:27:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:27:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:27:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1349 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:28:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:28:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:28:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:28:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:28:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:28:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:28:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:28:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:28:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:28:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:28:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:28:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:28:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:28:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:28:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:28:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:28:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:28:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:28:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:29:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 02:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 02:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 02:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 02:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 02:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 02:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 02:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 02:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 02:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:29:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:29:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 02:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 02:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 02:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 02:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 02:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 02:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 02:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 02:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 02:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 02:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 02:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 02:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 02:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 02:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 02:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 02:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 02:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 02:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 02:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 02:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 02:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 02:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 02:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 02:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 02:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 02:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 02:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 02:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 02:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 02:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 02:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 02:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 02:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 02:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 02:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 02:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 02:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 02:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 02:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 02:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 02:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 02:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 02:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 02:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 02:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 02:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-28 02:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-28 02:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-28 02:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2025-04-28 02:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2025-04-28 02:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2025-04-28 02:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2025-04-28 02:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2025-04-28 02:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2025-04-28 02:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2025-04-28 02:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2025-04-28 02:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2025-04-28 02:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2025-04-28 02:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2025-04-28 02:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2025-04-28 02:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2025-04-28 02:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2025-04-28 02:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2025-04-28 02:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2025-04-28 02:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2025-04-28 02:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2025-04-28 02:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2025-04-28 02:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2025-04-28 02:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2025-04-28 02:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2025-04-28 02:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2025-04-28 02:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2025-04-28 02:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:30:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2025-04-28 02:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2025-04-28 02:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2025-04-28 02:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2025-04-28 02:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2025-04-28 02:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2025-04-28 02:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2025-04-28 02:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2025-04-28 02:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2025-04-28 02:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2025-04-28 02:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2025-04-28 02:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2025-04-28 02:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2025-04-28 02:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2025-04-28 02:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2025-04-28 02:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2025-04-28 02:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2025-04-28 02:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2025-04-28 02:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2025-04-28 02:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2025-04-28 02:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2025-04-28 02:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2025-04-28 02:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2025-04-28 02:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2025-04-28 02:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2025-04-28 02:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2025-04-28 02:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2025-04-28 02:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2025-04-28 02:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2025-04-28 02:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2025-04-28 02:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2025-04-28 02:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2025-04-28 02:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2025-04-28 02:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2025-04-28 02:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2025-04-28 02:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2025-04-28 02:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 25704
2025-04-28 02:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 25806
2025-04-28 02:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 25908
2025-04-28 02:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 26010
2025-04-28 02:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 26112
2025-04-28 02:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 26214
2025-04-28 02:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 26316
2025-04-28 02:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 26418
2025-04-28 02:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 26520
2025-04-28 02:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 26622
2025-04-28 02:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 26724
2025-04-28 02:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 26826
2025-04-28 02:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 26928
2025-04-28 02:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 27030
2025-04-28 02:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 27132
2025-04-28 02:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 27234
2025-04-28 02:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 27336
2025-04-28 02:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 27438
2025-04-28 02:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 27540
2025-04-28 02:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 27642
2025-04-28 02:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 27744
2025-04-28 02:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 27846
2025-04-28 02:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 27948
2025-04-28 02:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 28050
2025-04-28 02:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 28152
2025-04-28 02:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 28254
2025-04-28 02:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 28356
2025-04-28 02:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 28458
2025-04-28 02:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 28560
2025-04-28 02:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 28662
2025-04-28 02:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 28764
2025-04-28 02:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 28866
2025-04-28 02:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 28968
2025-04-28 02:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 29070
2025-04-28 02:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 29172
2025-04-28 02:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 29274
2025-04-28 02:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 29376
2025-04-28 02:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 29478
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:30:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:30:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=29567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:30:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:30:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:30:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:30:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:30:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:30:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:30:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:30:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:30:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:30:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:30:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:30:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:30:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:30:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:30:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:30:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:30:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:30:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:30:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:30:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:57 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:30:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:30:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:30:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:31:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:31:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:31:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:31:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:31:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2420 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:31:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:31:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:31:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:31:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:31:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:31:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:31:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:31:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:31:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:31:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:31:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:31:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:31:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:31:37 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:31:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:31:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:32:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:32:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=12840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:32:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:32:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:32:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:32:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:32:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:32:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:32:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:32:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:32:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:32:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:32:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:32:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:32:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:32:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:32:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:32:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:32:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:32:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:32:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:32:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:32:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:32:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:32:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:32:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:33:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:33:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:33:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:33:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:33:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:33:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:33:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:33:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:33:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:33:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:33:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:33:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:33:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:33:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:33:35 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:33:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:33:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:33:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4612 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:33:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4612 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4612 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:33:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4613 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:34:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:34:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:34:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:34:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:34:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2981 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:29 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:29 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:34 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=393 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=393 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=393 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=393 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=393 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:34:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:34:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:34:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:34:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:34:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:34:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:34:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:34:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=138 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:35:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:35:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:35:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:35:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:35:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:35:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:35:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:35:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:35:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:35:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:35:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:35:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:35:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:36:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:36:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:36:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:36:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:36:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:36:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=3432 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=3432 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3439 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3439 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3439 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3439 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3439 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:36:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:36:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:36:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:36:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:25 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:36:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:36:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:36:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:36:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:36:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:36:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:36:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=574 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=574 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=574 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=574 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=575 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:36:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:36:44 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.80.20:5700'
2025-04-28 02:36:44 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.80.20:5802)
2025-04-28 02:36:44 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.80.20:5801)
2025-04-28 02:36:44 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.80.22:6700'
2025-04-28 02:36:44 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.80.22:6802)
2025-04-28 02:36:44 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.80.22:6801)
2025-04-28 02:36:44 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.80.20:5700/1'
2025-04-28 02:36:44 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.80.20:5804)
2025-04-28 02:36:44 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.80.20:5803)
2025-04-28 02:36:44 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.80.20:5700/2'
2025-04-28 02:36:44 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.80.20:5806)
2025-04-28 02:36:44 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.80.20:5805)
2025-04-28 02:36:44 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.80.20:5700/3'
2025-04-28 02:36:44 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.80.20:5808)
2025-04-28 02:36:44 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.80.20:5807)
2025-04-28 02:36:44 [INFO] fake_trx.py:423 Init complete
2025-04-28 02:36:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:36:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:36:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:36:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:36:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:37:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:37:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:37:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:37:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:37:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 0 -> 1
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:37:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 0 -> 1
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:37:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 0 -> 1
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:37:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 0 -> 1
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:37:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:37:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:37:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:37:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:25 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.80.20:5700'
2025-04-28 02:38:25 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.80.20:5802)
2025-04-28 02:38:25 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.80.20:5801)
2025-04-28 02:38:25 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.80.22:6700'
2025-04-28 02:38:25 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.80.22:6802)
2025-04-28 02:38:25 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.80.22:6801)
2025-04-28 02:38:25 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.80.20:5700/1'
2025-04-28 02:38:25 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.80.20:5804)
2025-04-28 02:38:25 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.80.20:5803)
2025-04-28 02:38:25 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.80.20:5700/2'
2025-04-28 02:38:25 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.80.20:5806)
2025-04-28 02:38:25 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.80.20:5805)
2025-04-28 02:38:25 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.80.20:5700/3'
2025-04-28 02:38:25 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.80.20:5808)
2025-04-28 02:38:25 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.80.20:5807)
2025-04-28 02:38:25 [INFO] fake_trx.py:423 Init complete
2025-04-28 02:38:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 0 -> 1
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 0 -> 1
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 0 -> 1
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 0 -> 1
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:38:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:38:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:38:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:34 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:35 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:35 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:39 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:41 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:41 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:42 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:42 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:42 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:42 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:43 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:38:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:38:43 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2957 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:38:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:38:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:38:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
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2025-04-28 02:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:38:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:38:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:38:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:38:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:38:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:56 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:38:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:38:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:38:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:38:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:38:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:39:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:39:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:39:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:39:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:39:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:39:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:39:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:39:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:39:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:39:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:39:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:39:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:39:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:39:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:39:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:39:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:39:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:39:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:39:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:39:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:39:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:39:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:39:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:39:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:39:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:40:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:04 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:04 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:08 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:08 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:40:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:12 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:12 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:40:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 02:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 02:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:17 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:17 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 02:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 02:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 02:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 02:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 02:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 02:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 02:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 02:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 02:40:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 02:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 02:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 02:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 02:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 02:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 02:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 02:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:25 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=15595 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:25 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 02:40:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 02:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 02:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 02:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 02:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 02:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 02:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 02:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 02:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 02:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 02:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 02:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 02:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 02:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 02:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 02:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 02:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:34 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:34 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 02:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 02:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 02:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 02:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 02:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 02:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 02:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 02:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:38 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 02:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 02:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 02:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 02:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 02:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 02:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 02:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-28 02:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:43 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=19314 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:40:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:40:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:40:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:40:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:40:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:40:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:40:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:40:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:40:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:40:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:40:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:40:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:40:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:40:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:40:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:40:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:40:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:40:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:55 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:56 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:56 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:56 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:58 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:59 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:59 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:40:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:40:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:00 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:00 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:00 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:00 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:02 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:02 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:02 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:02 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:03 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:41:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:41:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:41:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:41:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:41:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:41:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:41:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:41:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:41:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:41:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:16 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:41:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:17 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:17 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:41:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:18 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:41:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:23 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:25 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:26 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:26 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:41:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:29 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:41:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:31 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:32 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:33 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:35 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:41:36 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:41:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:41:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:41:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:41:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:41:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:41:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:41:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:41:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:41:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:41:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:41:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:41:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:41:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:41:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:41:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:05 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=4680 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:09 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:09 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:13 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=6578 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:27 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:31 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:36 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 02:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 02:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 02:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 02:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 02:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:48 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:48 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 02:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 02:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 02:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 02:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 02:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 02:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 02:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 02:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:53 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 02:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 02:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 02:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 02:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 02:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 02:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 02:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:57 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:42:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:42:57 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 02:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 02:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 02:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 02:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 02:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 02:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 02:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 02:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:43:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 02:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 02:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 02:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 02:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 02:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 02:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 02:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:43:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 02:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 02:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 02:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 02:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 02:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 02:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 02:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:10 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:43:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:43:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:43:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=18563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:43:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:43:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:43:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:43:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:43:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:43:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:43:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:43:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:43:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:43:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:43:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:43:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:43:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:43:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:43:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:43:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:43:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:43:42 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:43:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:43:46 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=5751 tn=2 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:43:47 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:51 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:43:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:43:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:10 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:10 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:14 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:19 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:19 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:23 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 02:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 02:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 02:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 02:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 02:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 02:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 02:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 02:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:27 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:27 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 02:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 02:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 02:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 02:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 02:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 02:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 02:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 02:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:32 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 02:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 02:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 02:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 02:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 02:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 02:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 02:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 02:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 02:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:36 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 02:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 02:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 02:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 02:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 02:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 02:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 02:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 02:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 02:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 02:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 02:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 02:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 02:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 02:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 02:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 02:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:45 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:44:45 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 02:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 02:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 02:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 02:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 02:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 02:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 02:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 02:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:49 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:44:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:44:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:44:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:44:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:44:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:44:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:44:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:44:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:44:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:44:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:44:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:44:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:44:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:44:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:44:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:44:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:44:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:44:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:44:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:02 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=662 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:45:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:06 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1560 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:08 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:08 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1885 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:08 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1885 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:08 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:09 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:11 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2535 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:15 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:15 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:16 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:16 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:18 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:18 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:19 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:19 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:22 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:22 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:23 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:25 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:26 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:26 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:45:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:45:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:45:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:45:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:45:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:45:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:45:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:45:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:45:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:45:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:45:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:45:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:45:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:37 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:37 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:45:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:45:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:45:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:41 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=1768 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:45:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:48 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:45:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:55 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:45:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:45:59 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:45:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:45:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:02 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:46:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:46:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:46:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:46:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:46:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:46:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:46:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:46:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:46:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:46:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:46:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:46:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:46:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:19 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2600 tn=3 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:19 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2600 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:20 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=2808 tn=4 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:20 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:24 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:24 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=3588 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:24 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:46:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:46:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:32 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:46:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:39 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=6931 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:39 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=6931 tn=7 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:46:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:47 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:47 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:51 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:51 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:54 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:46:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:46:54 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:46:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:46:55 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:46:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:46:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:46:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:46:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:47:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:47:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:47:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:47:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:47:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2026 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:47:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:47:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:47:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:47:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:47:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:47:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2025 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:47:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:47:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:47:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:47:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:47:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:47:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2879 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:47:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:47:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:47:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:47:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:47:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:47:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:47:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:47:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:47:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:47:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:47:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:47:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:47:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:47:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:47:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:47:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:47:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:48:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:48:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:04 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:04 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=537 tn=1 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:48:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=812 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=813 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:48:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:48:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:48:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=571 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=571 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=571 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:48:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:48:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:48:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:48:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:48:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:48:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:48:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:48:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:48:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:48:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:48:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:48:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1178 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1178 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1178 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1178 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1178 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1179 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:48:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:48:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:48:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:48:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:48:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:48:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:48:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:48:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:48:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:48:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:48:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:49:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:49:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:49:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:32 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:49:32 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:49:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:49:45 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:49:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:49:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:49:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:49:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:49:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:49:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:49:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:49:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:00 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:50:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:50:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:50:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:50:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7026 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7027 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:50:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:50:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:50:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:50:43 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:50:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:50:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:50:51 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:52 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (TRX2@172.18.80.20:5700/2) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:50:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:50:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:50:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:50:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:50:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:50:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:51:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:51:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:51:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:51:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:51:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:51:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:51:11 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:51:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:51:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:20 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:51:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:51:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:51:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:51:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:51:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:51:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:51:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:51:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:51:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:51:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:51:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:51:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:51:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:51:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:51:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:51:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:51:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:51:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:51:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:51:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:51:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:51:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:51:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:51:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:51:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:51:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:52:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:52:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:52:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:52:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:52:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:52:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:52:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:52:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:52:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4316 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4316 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4316 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4316 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4316 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4317 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:52:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:52:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:52:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:52:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:52:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:52:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:52:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:52:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:52:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:52:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:52:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:52:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:52:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:52:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:52:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:52:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:52:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:52:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:52:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:52:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:52:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:52:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:52:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:52:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:52:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:52:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:52:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:52:47 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:03 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:53:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:53:03 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 02:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 02:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 02:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 02:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 02:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 02:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 02:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 02:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 02:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 02:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 02:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 02:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 02:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 02:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 02:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 02:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 02:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 02:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 02:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 02:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 02:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 02:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 02:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 02:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 02:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 02:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 02:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:18 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:53:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 02:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 02:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 02:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 02:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 02:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 02:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 02:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 02:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 02:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 02:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 02:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 02:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 02:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 02:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 02:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 02:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 02:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 02:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 02:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 02:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 02:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 02:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 02:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 02:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 02:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 02:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 02:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 02:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 02:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 02:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 02:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:53:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:53:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13457 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=13458 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:53:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:53:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:53:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:53:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:53:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:53:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:53:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:53:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:53:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:53:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:53:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:53:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:53:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:53:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:53:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:53:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:53:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:53:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:53:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:53:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:53:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2355 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2356 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:53:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2357 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:54:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:54:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:54:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:54:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:54:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:54:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:54:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:54:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:54:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:54:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2364 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2365 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:54:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:54:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:54:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:54:18 [DEBUG] fake_trx.py:263 (MS@172.18.80.22:6700) Recv SETTA cmd
2025-04-28 02:54:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:54:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:54:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4419 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4419 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4419 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4420 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:54:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:54:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:54:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:54:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:54:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:54:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:54:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:54:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:54:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:54:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:54:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:54:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:54:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:54:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:55:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:55:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:55:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:55:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:55:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:55:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:55:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:55:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2277 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:55:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:55:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:55:27 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:55:27 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:55:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:55:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:55:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:55:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:55:40 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:40 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:55:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:55:43 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:55:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2875 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:55:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:55:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:55:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:55:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:55:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:55:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:55:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:56:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:56:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:56:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:56:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:56:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:56:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:56:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:56:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:56:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:56:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:56:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:56:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:56:18 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:56:18 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:56:18 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:56:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 02:56:18 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:56:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:56:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:56:20 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:56:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:56:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:56:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:56:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:56:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:56:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:56:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:56:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:56:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:56:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:56:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:56:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:56:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:56:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:56:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:56:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:57:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:57:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:57:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4711 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:57:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:57:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:57:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:57:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:57:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:57:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:57:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:57:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:57:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:57:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:57:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:57:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:57:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:57:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:57:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:57:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4727 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4728 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:57:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:57:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:57:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:57:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:57:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:57:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:57:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:57:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:57:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:57:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:57:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:57:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:57:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:57:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:57:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:57:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 02:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 02:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 02:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 02:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 02:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 02:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 02:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 02:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 02:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 02:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 02:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 02:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:58:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:58:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:58:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:58:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7285 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:58:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:58:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:58:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:58:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:58:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:58:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:58:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:58:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:58:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:58:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:58:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 02:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 02:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 02:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 02:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 02:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 02:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 02:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 02:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 02:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 02:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 02:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 02:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 02:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 02:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 02:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 02:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 02:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 02:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 02:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 02:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 02:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 02:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 02:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 02:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 02:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 02:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 02:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 02:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 02:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 02:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 02:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 02:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 02:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 02:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 02:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 02:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 02:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 02:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 02:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 02:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:58:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:58:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:58:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:58:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:58:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:58:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:58:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:58:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:58:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:58:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:58:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:58:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:58:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:58:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:58:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:58:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:58:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:06 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:06 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:06 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:59:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:59:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:59:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:59:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:59:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:59:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:59:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1817 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1817 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1817 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1817 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1817 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1818 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:59:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:59:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 02:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 02:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 02:59:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 02:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 02:59:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 02:59:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 02:59:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 02:59:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 02:59:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 02:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 02:59:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 02:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 02:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 02:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 02:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 02:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 02:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 02:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 02:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 02:59:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 02:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 02:59:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 02:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 02:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 02:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 02:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 02:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:00:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:00:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:00:06 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:00:06 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:00:06 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:00:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:00:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:00:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:00:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:00:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:00:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:00:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:00:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3542 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3542 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3542 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3542 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:00:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:00:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:00:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:00:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:00:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:00:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:00:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:00:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:00:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:00:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:00:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:00:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:00:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:00:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:00:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:00:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:00:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:11 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:11 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:16 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:16 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:16 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:16 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:28 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:01:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:01:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:01:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:01:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:01:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:01:50 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:01:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:01:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:01:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:02:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7304 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7304 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7304 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7304 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7305 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:02:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:02:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:02:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:02:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:02:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:02:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:02:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:02:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:02:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:02:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:02:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:02:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:02:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:02:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:02:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:02:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:02:49 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:02:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:02:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:02:49 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:02:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:02:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:02:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:02:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:02:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:02:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:02:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:03:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:03:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1826 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:03:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:03:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=970 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=970 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=970 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=970 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=970 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=971 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:03:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:03:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:03:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:03:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:03:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:03:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:03:55 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:03:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:03:55 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:03:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:03:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:03:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=779 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=779 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=779 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=779 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=779 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:03:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=780 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:04:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:04:01 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:04:01 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:04:01 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:04:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:04:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:04:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:04:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:04:04 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:04:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:04:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:04:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:04:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:04:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:04:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:04:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:04:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:04:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:18 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:04:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:04:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:04:24 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:04:24 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:04:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:04:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:04:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:04:27 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1820 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1820 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1820 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1820 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1820 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:04:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:04:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:04:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:04:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:04:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:04:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:04:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:04:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:04:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:04:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:04:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:04:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:04:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:04:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:04:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:04:51 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:04:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:04:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:04:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:04:56 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:04:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:04:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:04:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1199 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:05:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:05:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1206 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:05:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:05:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=781 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=782 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:16 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=783 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:05:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:05:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:05:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2018 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2018 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2018 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2018 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2018 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:05:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:05:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:05:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:05:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:05:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:05:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:05:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:05:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:05:56 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:05:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:05:56 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:05:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:05:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:05:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:05:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:05:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:05:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:06:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:06:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:06:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:06:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:06:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:06:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:06:14 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2025-04-28 03:06:14 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:06:15 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=996 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:06:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:06:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:06:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:06:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:06:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:06:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:06:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:06:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:06:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:34 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:06:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:06:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:06:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:06:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:06:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:06:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:06:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:06:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:06:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:06:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:06:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:06:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:06:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:06:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:06:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:06:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:06:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:06:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=760 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:06:56 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=761 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:24 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:07:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:07:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:07:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:07:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:07:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:07:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:07:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:07:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:07:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:07:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:07:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:07:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:02 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:02 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:02 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:08:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:08:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:08:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:08:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=542 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:19 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:22 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=767 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:27 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:41 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:47 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:08:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:08:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:08:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:08:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:08:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:08:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:08:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:08:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=111 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:09:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:09:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:09:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:09:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:09:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:43 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 03:09:43 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 200
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:44 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 03:09:44 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 0
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:50 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:50 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:50 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 03:09:50 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 200
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] fake_trx.py:376 (BTS@172.18.80.20:5700) Recv FAKE_TRXC_DELAY cmd
2025-04-28 03:09:51 [INFO] fake_trx.py:379 (BTS@172.18.80.20:5700) Artificial TRXC delay set to 0
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD FAKE_TRXC_DELAY
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=463 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:09:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:09:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:09:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:09:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:09:57 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:09:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:09:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:09:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:09:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:10:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:10:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:10:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:10:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:10:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:10:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:10:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:10:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:10:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:10:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:19 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:19 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:19 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:22 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:22 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:22 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:22 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:25 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:10:37 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:41 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:47 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:47 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 03:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:50 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:51 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:51 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 03:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 03:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 03:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 03:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:10:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:10:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=9794 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:10:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:10:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:10:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:10:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:10:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:10:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:59 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:00 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:00 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:11:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:11:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:11:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:11:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:07 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:11:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:11:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:11:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:11:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:14 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:15 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:11:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:15 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:11:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:11:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:11:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:22 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:11:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:11:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:11:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:11:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:11:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:11:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:11:34 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5618 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:11:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:11:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:11:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:11:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:11:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:11:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:12:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:12:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:03 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:12:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:12:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:12:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:12:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:12:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:12:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:12:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:12:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:12:30 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:12:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:12:30 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:35 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:36 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:38 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:38 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:45 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:12:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:12:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:12:46 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=7833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:12 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:12 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=430 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:19 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:20 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:22 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:23 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:38 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:39 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:42 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:45 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:51 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:51 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:51 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:52 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=445 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:13:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:13:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:13:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:58 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:58 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:13:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:13:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:13:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:00 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:12 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:19 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:19 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:19 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:20 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:20 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:21 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:31 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:14:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:41 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:49 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:49 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:14:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:14:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:52 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:52 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:52 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:14:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:14:57 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:14:58 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:14:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:14:58 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:14:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:14:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:14:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:14:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:14:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:15:04 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:15:04 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:15:04 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:15:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:15:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:15:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:15:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:15:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:24 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:25 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:25 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:26 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:28 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:29 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:31 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:32 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:33 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:34 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:34 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:35 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:15:36 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:37 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:15:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:15:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:15:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:15:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:15:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:16:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:16:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:16:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:16:12 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:12 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:16:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:16:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:16:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:16:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:16:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:16:17 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:16:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:16:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:16:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:16:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:16:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:16:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:16:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:17:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:17:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:17:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:17:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:17:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:17:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:17:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:17:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:17:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:17:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:17:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:17:09 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:17 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:17:17 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:17:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:17:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3557 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:17:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:17:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:17:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:17:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:17:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:17:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:17:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:17:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:17:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:17:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:17:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:17:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:17:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:17:30 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:17:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:17:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:17:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:17:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:17:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:17:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:17:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:17:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:17:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:17:35 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:17:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:17:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:17:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:17:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:17:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:17:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:17:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:17:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:17:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:17:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:17:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:17:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:17:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:17:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:17:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:17:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:17:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:17:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:17:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:17:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:17:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:17:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:17:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:17:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:17:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:17:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:17:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:17:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:17:49 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:17:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:17:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:17:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:17:50 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:17:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:17:51 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:17:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:17:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:17:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:17:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:17:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:17:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:17:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:17:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:17:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:17:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:17:56 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:17:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:17:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:17:58 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:17:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:17:58 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:17:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:17:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6820 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6820 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6820 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6820 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6820 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:17:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:18:16 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:18 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:18:18 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:18:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:20 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1032 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1032 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1032 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1032 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1032 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1034 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:18:37 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:39 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:18:40 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:42 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:18:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:18:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:18:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:18:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:18:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:18:55 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:18:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:18:57 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:18:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:18:57 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=599 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:18:57 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:02 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:03 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:03 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:03 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=987 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=988 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:19:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:19:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:22 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:22 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:22 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=320 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:19:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:19:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:19:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=995 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:44 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:19:45 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:19:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:19:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:49 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:19:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:19:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:19:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:19:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:19:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:19:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:19:55 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:19:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:19:55 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:00 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:00 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:00 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:00 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:08 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:20:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:20:26 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:27 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:27 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:32 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:35 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:35 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:40 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:20:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:50 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2068 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:20:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:20:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:20:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:20:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:20:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:20:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:20:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:20:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:21:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:21:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:21:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:21:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2075 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2075 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2075 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2075 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:05 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2075 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:21:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:21:10 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:21:10 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:21:10 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:21:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:21:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:21:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2067 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2067 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2067 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2067 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:19 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2067 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:21:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:21:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:21:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:21:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:21:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:21:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:21:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:34 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:21:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:21:39 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:21:40 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:21:40 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:21:40 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:21:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:21:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD NOHANDOVER
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:21:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2069 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2069 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2069 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2069 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:49 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2069 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:21:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:21:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:21:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:21:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:21:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:21:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:04 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:04 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:09 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:22:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:22:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:22:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:22:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:22:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:22:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:22:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1846 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:22:34 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:22:34 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:22:34 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:22:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:22:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:22:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:22:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:47 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:22:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:22:52 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:22:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:22:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:22:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:22:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:22:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:22:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:22:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:05 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:10 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:23:11 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:23:11 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:23:11 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:19 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:24 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:24 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:29 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:23:29 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:23:29 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:23:29 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:23:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:23:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:23:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:23:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3112 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3112 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3112 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3112 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3112 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:23:54 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:23:54 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:23:54 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:23:54 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:23:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:23:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:23:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:23:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:02 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:02 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:07 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:24:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:24:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:24:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:24:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:24:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:23 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:23 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:28 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:28 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:33 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:24:33 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:24:33 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:24:33 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:24:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:24:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:45 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:45 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2474 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:50 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:24:55 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:24:55 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:24:55 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:24:55 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:24:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:24:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:24:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:25:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:25:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:15 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:25:20 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:25:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:25:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:25:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:25:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:25:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:25:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:25:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:25:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:25:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:25:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:25:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:25:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:25:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:25:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:25:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:25:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:25:58 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:25:58 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2666 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:03 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:26:09 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:26:09 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:26:09 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:26:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:26:09 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:26:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:17 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:26:28 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:26:28 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:26:28 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:26:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:26:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:26:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:26:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1829 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:41 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:46 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:26:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:26:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:26:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:26:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:26:46 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:26:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:26:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:26:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:26:54 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:26:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:26:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:26:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:26:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:27:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:27:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:27:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:27:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:27:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:27:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:27:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:27:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:27:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:13 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:13 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:27:18 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:18 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:27:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:27:23 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:27:24 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:27:24 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:27:24 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:27:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:27:24 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:27:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:27:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:38 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3095 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:27:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:27:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:27:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:27:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:27:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:27:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:27:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:27:48 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:27:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:27:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:27:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:27:56 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:27:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:27:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:27:56 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:28:01 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:28:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:28:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:28:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:28:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:28:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:28:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:28:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:28:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:28:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:28:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2276 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:28:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:22 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:28:27 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:28:27 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:28:27 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:28:27 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:28:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:28:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:28:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:28:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:28:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:28:39 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:39 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2472 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2472 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2472 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2472 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2472 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:39 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:28:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:28:50 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:28:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:28:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:28:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:28:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2876 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:29:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:08 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:29:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:29:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:29:13 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:29:14 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:29:14 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:29:14 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:29:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:29:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:29:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:29:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:29:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2692 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2692 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2692 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2692 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:29:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:29:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:29:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:29:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:29:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:29:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:29:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:29:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:29:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:29:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:29:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:29:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2488 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:29:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:29:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:29:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:29:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:29:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:29:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:29:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:29:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:29:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:29:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3331 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:30:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:30:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:30:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:30:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:30:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:30:14 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:30:14 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:30:14 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:30:15 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:16 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:16 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:30:21 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:30:21 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:30:21 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:30:21 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:30:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:30:26 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:30:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:30:37 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:42 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:42 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4474 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:30:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:30:47 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:30:47 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:47 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:30:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:30:52 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:57 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:30:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:31:02 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:31:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:31:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:31:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:31:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:31:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:31:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:31:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:31:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:31:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:31:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:31:18 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:23 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:31:28 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:31:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:31:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4490 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4490 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4491 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:31:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:31:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:31:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:31:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:31:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:31:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:31:39 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:31:39 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:31:39 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:31:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:31:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:49 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:31:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:31:54 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:31:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:31:59 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:31:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:31:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:31:59 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:31:59 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:32:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:32:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:32:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:32:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:32:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:32:04 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:32:05 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:32:05 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:32:05 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:32:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:32:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:07 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:32:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:32:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=583 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=583 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=583 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=583 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:32:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:32:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:32:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:32:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:32:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:32:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:32:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:32:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:32:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:32:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:32:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:32:33 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:53 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:32:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:32:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 03:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 03:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 03:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 03:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 03:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 03:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 03:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 03:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 03:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 03:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 03:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 03:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 03:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 03:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 03:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 03:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 03:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 03:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 03:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 03:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 03:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 03:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 03:33:04 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 03:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 03:33:05 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 03:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 03:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 03:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 03:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 03:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 03:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 03:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 03:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 03:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 03:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 03:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 03:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 03:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 03:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 03:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 03:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 03:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 03:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 03:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 03:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 03:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 03:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 03:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 03:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 03:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 03:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 03:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 03:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 03:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 03:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 03:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 03:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 03:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 03:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 03:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 03:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 03:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 03:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 03:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 03:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 03:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 03:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 03:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 03:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 03:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 03:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 03:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 03:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 03:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 03:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 03:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 03:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 03:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 03:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 03:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 03:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:33:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:33:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17409 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=17410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:33:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:33:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:33:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:33:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:33:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:33:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:33:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:33:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:33:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:33:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:33:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:33:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:33:43 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:33:43 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:43 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:45 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:45 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:45 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:33:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:53 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:56 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:56 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:58 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:33:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:33:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:33:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:33:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:33:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:01 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4000 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4000 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4000 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4000 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:01 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:34:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:34:06 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:34:07 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:34:07 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:34:07 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:10 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:13 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:17 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:20 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=2927 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:34:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:34:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:34:26 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:34:26 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:34:26 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:26 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:34:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:29 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:32 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:32 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:32 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:34:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:34:37 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:34:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:34:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:34:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:41 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:34:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:34:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:34:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:34:46 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:06 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:35:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:35:06 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:06 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6253 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:35:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:35:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:35:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:35:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:35:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:35:11 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:35:12 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:35:12 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:12 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:35:13 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:14 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:35:16 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:35:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:35:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5225 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5225 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5225 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=5226 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:35:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:35:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:35:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:35:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:35:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:35:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:35:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:35:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:35:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:35:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:35:44 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:35:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:46 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:35:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:35:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:35:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:10 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:36:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:36:10 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:10 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:36:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:36:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:36:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:36:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:36:15 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:36:15 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:36:15 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:15 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:36:16 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:36:17 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:17 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:36:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:36:17 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:17 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:36:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:36:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:36:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:36:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:36:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:36:22 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:36:23 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:36:23 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:36:23 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:36:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:36:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:36:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:36:56 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 03:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 03:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 03:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 03:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 03:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 03:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 03:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 03:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 03:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 03:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 03:37:09 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 03:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 03:37:10 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 03:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2025-04-28 03:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2025-04-28 03:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2025-04-28 03:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2025-04-28 03:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2025-04-28 03:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2025-04-28 03:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2025-04-28 03:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2025-04-28 03:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2025-04-28 03:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2025-04-28 03:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2025-04-28 03:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2025-04-28 03:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2025-04-28 03:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2025-04-28 03:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2025-04-28 03:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2025-04-28 03:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2025-04-28 03:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2025-04-28 03:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2025-04-28 03:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2025-04-28 03:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2025-04-28 03:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2025-04-28 03:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2025-04-28 03:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2025-04-28 03:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2025-04-28 03:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2025-04-28 03:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2025-04-28 03:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2025-04-28 03:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2025-04-28 03:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2025-04-28 03:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2025-04-28 03:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2025-04-28 03:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2025-04-28 03:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2025-04-28 03:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2025-04-28 03:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2025-04-28 03:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2025-04-28 03:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2025-04-28 03:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2025-04-28 03:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2025-04-28 03:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:37:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:37:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:37:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:37:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:37:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:37:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2025-04-28 03:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2025-04-28 03:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2025-04-28 03:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2025-04-28 03:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2025-04-28 03:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2025-04-28 03:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2025-04-28 03:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2025-04-28 03:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2025-04-28 03:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2025-04-28 03:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2025-04-28 03:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2025-04-28 03:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2025-04-28 03:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2025-04-28 03:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2025-04-28 03:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2025-04-28 03:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2025-04-28 03:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2025-04-28 03:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2025-04-28 03:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2025-04-28 03:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2025-04-28 03:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2025-04-28 03:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2025-04-28 03:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2025-04-28 03:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2025-04-28 03:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2025-04-28 03:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2025-04-28 03:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2025-04-28 03:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2025-04-28 03:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2025-04-28 03:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2025-04-28 03:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2025-04-28 03:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2025-04-28 03:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2025-04-28 03:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2025-04-28 03:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2025-04-28 03:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2025-04-28 03:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2025-04-28 03:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2025-04-28 03:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2025-04-28 03:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2025-04-28 03:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2025-04-28 03:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2025-04-28 03:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2025-04-28 03:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2025-04-28 03:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2025-04-28 03:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2025-04-28 03:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2025-04-28 03:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2025-04-28 03:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2025-04-28 03:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2025-04-28 03:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2025-04-28 03:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2025-04-28 03:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2025-04-28 03:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2025-04-28 03:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2025-04-28 03:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2025-04-28 03:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2025-04-28 03:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2025-04-28 03:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2025-04-28 03:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2025-04-28 03:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2025-04-28 03:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2025-04-28 03:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2025-04-28 03:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2025-04-28 03:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2025-04-28 03:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2025-04-28 03:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2025-04-28 03:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2025-04-28 03:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2025-04-28 03:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2025-04-28 03:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2025-04-28 03:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2025-04-28 03:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2025-04-28 03:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:38:05 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2025-04-28 03:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2025-04-28 03:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2025-04-28 03:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2025-04-28 03:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2025-04-28 03:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2025-04-28 03:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2025-04-28 03:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2025-04-28 03:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2025-04-28 03:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2025-04-28 03:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2025-04-28 03:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2025-04-28 03:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2025-04-28 03:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2025-04-28 03:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2025-04-28 03:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2025-04-28 03:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2025-04-28 03:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2025-04-28 03:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2025-04-28 03:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2025-04-28 03:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2025-04-28 03:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2025-04-28 03:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2025-04-28 03:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2025-04-28 03:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2025-04-28 03:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2025-04-28 03:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2025-04-28 03:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2025-04-28 03:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2025-04-28 03:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2025-04-28 03:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2025-04-28 03:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2025-04-28 03:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2025-04-28 03:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:21 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:21 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:38:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:21 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=25673 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:38:26 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:38:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:38:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:38:32 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:38:32 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:32 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:38:33 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:38:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:36 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:38:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:40 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:38:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1959 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:38:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:38:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:38:46 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:38:46 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:38:46 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:38:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:38:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:38:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:38:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:38:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:38:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:39:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:39:01 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:16 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:39:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 03:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 03:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 03:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 03:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 03:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 03:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:39:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:39:30 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 03:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 03:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 03:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 03:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 03:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:33 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:39:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:39:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:39:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:39:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:39:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:39:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:39:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:39:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:39:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:39:38 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:39:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:39:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:39:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:39:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:39:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:39:43 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:39:44 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:39:44 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:44 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:39:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:39:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:39:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:39:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:39:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:39:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:39:54 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:04 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:40:11 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2025-04-28 03:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2025-04-28 03:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2025-04-28 03:40:14 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2025-04-28 03:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2025-04-28 03:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2025-04-28 03:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2025-04-28 03:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2025-04-28 03:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2025-04-28 03:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2025-04-28 03:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2025-04-28 03:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2025-04-28 03:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2025-04-28 03:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2025-04-28 03:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2025-04-28 03:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2025-04-28 03:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2025-04-28 03:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2025-04-28 03:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2025-04-28 03:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2025-04-28 03:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2025-04-28 03:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2025-04-28 03:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2025-04-28 03:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2025-04-28 03:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2025-04-28 03:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2025-04-28 03:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2025-04-28 03:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2025-04-28 03:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2025-04-28 03:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2025-04-28 03:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2025-04-28 03:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2025-04-28 03:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2025-04-28 03:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2025-04-28 03:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2025-04-28 03:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2025-04-28 03:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2025-04-28 03:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2025-04-28 03:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:31 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:40:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:40:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10337 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10337 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10337 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10337 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=10337 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:40:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:40:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:40:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:40:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:40:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:40:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:40:37 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:38 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:40:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:43 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:40:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:40:43 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1377 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:43 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=1378 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:40:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:40:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:40:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:40:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:40:48 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:40:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:40:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:40:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:40:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:40:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:40:52 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:40:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:40:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:55 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:40:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:40:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:40:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:40:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:40:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:40:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:03 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:03 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:41:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:41:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:41:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:41:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:41:09 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:09 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:41:10 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:30 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (TRX1@172.18.80.20:5700/1) RX TRXD message (ver=1 fn=4854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=4854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:41:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:41:36 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:41:36 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:36 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:41:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:41:39 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:41:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:44 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:41:50 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:51 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:51 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:51 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3388 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:41:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:41:56 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:41:57 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:41:57 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:57 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:41:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:41:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:41:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:41:59 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:42:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:01 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:42:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:42:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.80.22:6700) Recv SETFH cmd
2025-04-28 03:42:06 [INFO] transceiver.py:201 (MS@172.18.80.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2025-04-28 03:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2025-04-28 03:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2025-04-28 03:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2025-04-28 03:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2025-04-28 03:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2025-04-28 03:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2025-04-28 03:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2025-04-28 03:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2025-04-28 03:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2025-04-28 03:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2025-04-28 03:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2025-04-28 03:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2025-04-28 03:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2025-04-28 03:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2025-04-28 03:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2025-04-28 03:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2025-04-28 03:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2025-04-28 03:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2025-04-28 03:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2025-04-28 03:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2025-04-28 03:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2025-04-28 03:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2025-04-28 03:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2025-04-28 03:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2025-04-28 03:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2025-04-28 03:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2025-04-28 03:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2025-04-28 03:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:42:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:42:26 [INFO] transceiver.py:205 (MS@172.18.80.22:6700) Frequency hopping disabled
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:26 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:26 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=6330 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:42:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:42:31 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:42:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:42:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:33 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:33 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:42:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:42:38 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:42:38 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:42:38 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:38 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:40 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:40 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:42:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:42:45 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:42:45 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:42:45 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:42:45 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:46 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=397 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:46 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:42:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:42:51 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:42:52 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:42:52 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:42:52 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:53 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:53 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:42:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:42:58 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:42:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:42:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:00 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:00 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:05 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:06 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:06 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:07 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=409 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=409 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:07 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=411 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:12 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:13 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:13 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:13 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:14 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:14 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:19 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:20 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:20 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:20 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:20 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:25 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:25 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:25 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:25 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:30 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:31 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:31 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:31 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:31 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:36 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:37 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:37 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:37 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:37 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:42 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:42 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:42 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:42 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:47 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:48 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:48 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:48 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:48 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:53 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:53 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:53 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:53 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:54 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:54 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:43:59 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:43:59 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:43:59 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:43:59 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:43:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:43:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:44:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:44:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:03 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:44:08 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:44:08 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:44:08 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:44:08 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:09 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:09 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=259 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:44:14 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:44:14 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:44:14 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:44:14 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2025-04-28 03:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2025-04-28 03:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2025-04-28 03:44:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2025-04-28 03:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2025-04-28 03:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2025-04-28 03:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2025-04-28 03:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2025-04-28 03:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2025-04-28 03:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2025-04-28 03:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2025-04-28 03:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2025-04-28 03:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2025-04-28 03:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2025-04-28 03:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2025-04-28 03:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2025-04-28 03:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2025-04-28 03:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2025-04-28 03:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2025-04-28 03:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2025-04-28 03:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2025-04-28 03:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2025-04-28 03:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2025-04-28 03:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2025-04-28 03:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2025-04-28 03:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2025-04-28 03:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2025-04-28 03:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (MS@172.18.80.22:6700) RX TRXD message (fn=3432 tn=6 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:30 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:30 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:44:35 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:44:35 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:44:35 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:35 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:36 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:36 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:44:41 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2025-04-28 03:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2025-04-28 03:44:41 [DEBUG] fake_trx.py:272 (BTS@172.18.80.20:5700) Recv FAKE_TOA cmd
2025-04-28 03:44:41 [DEBUG] fake_trx.py:291 (BTS@172.18.80.20:5700) Recv FAKE_RSSI cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:41 [DEBUG] fake_trx.py:316 (BTS@172.18.80.20:5700) Recv FAKE_CI cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD HANDOVER
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2025-04-28 03:44:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2025-04-28 03:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD ECHO
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.80.22:6700) Ignore CMD SETSLOT
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.80.22:6700) Recv RXTUNE cmd
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.80.22:6700) Recv TXTUNE cmd
2025-04-28 03:44:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.80.22:6700) Recv POWERON CMD
2025-04-28 03:44:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.80.22:6700) Starting transceiver...
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD NOHANDOVER
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.80.22:6700) Recv POWEROFF cmd
2025-04-28 03:44:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.80.22:6700) Stopping transceiver...
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.80.20:5700) Recv SETPOWER cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.80.20:5700/1) Recv SETPOWER cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.80.20:5700/2) Recv SETPOWER cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.80.20:5700/3) Recv SETPOWER cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:44 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:44 [WARNING] transceiver.py:250 (BTS@172.18.80.20:5700) RX TRXD message (ver=1 fn=585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.80.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.80.20:5700) Recv SETFORMAT cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.80.20:5700) TRXD header version 1 -> 1
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.80.20:5700/1) Recv RXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.80.20:5700/1) Recv TXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.80.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.80.20:5700/1) Recv NOMTXPOWER cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.80.20:5700/1) Recv SETFORMAT cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.80.20:5700/1) TRXD header version 1 -> 1
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.80.20:5700/2) Recv RXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.80.20:5700/2) Recv TXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.80.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.80.20:5700/2) Recv NOMTXPOWER cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.80.20:5700/2) Recv SETFORMAT cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.80.20:5700/2) TRXD header version 1 -> 1
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.80.20:5700/3) Recv RXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.80.20:5700/3) Recv TXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.80.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.80.20:5700/3) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.80.20:5700/3) Recv NOMTXPOWER cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.80.20:5700/3) Recv SETFORMAT cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.80.20:5700/3) TRXD header version 1 -> 1
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.80.20:5700) Recv RXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETTSC
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETTSC
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.80.20:5700) Recv TXTUNE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETTSC
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETRXGAIN
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETRXGAIN
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETTSC
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETRXGAIN
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.80.20:5700) Recv NOMTXPOWER cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.80.20:5700) Recv POWERON CMD
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.80.20:5700) Starting transceiver...
2025-04-28 03:44:49 [INFO] transceiver.py:236 Starting clock generator
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETRXGAIN
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.80.20:5700/1) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.80.20:5700/1) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.80.20:5700) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.80.20:5700) Recv RFMUTE cmd
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.80.20:5700/2) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.80.20:5700) Recv POWEROFF cmd
2025-04-28 03:44:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.80.20:5700) Stopping transceiver...
2025-04-28 03:44:49 [INFO] transceiver.py:239 Stopping clock generator
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.80.20:5700/3) Ignore CMD SETSLOT
2025-04-28 03:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.80.20:5700/2) Recv RFMUTE cmd