Timing Advance mismatch: expected 2, but received 0 PCU_Tests.ttcn:7640 PCU_Tests control part PCU_Tests.ttcn:572 TC_ta_ul_ack_nack_first_block testcase Timing Advance value doesn't match PCU_Tests.ttcn:7641 PCU_Tests control part PCU_Tests.ttcn:607 TC_ta_idle_dl_tbf_ass testcase Failed to match Timing Advance Index for #0 PCU_Tests.ttcn:7642 PCU_Tests control part PCU_Tests.ttcn:807 TC_ta_ptcch_ul_multi_tbf testcase Failed to match DL DATA: { ctrl := { mac_hdr := { payload_type := MAC_PT_RLCMAC_NO_OPT (1), rrbp := RRBP_Nplus13_mod_2715648 (0), rrbp_valid := false, usf := 7 }, opt := omit, payload := { msg_type := PACKET_DL_DUMMY_CTRL (37), u := { dl_dummy := { page_mode := PAGE_MODE_NORMAL (0), persistence_levels_present := '0'B, persistence_levels := omit } } } } } vs ({ data := { cs := ?, mac_hdr := { mac_hdr := { payload_type := MAC_PT_RLC_DATA (0), rrbp := ?, rrbp_valid := ?, usf := ? }, hdr_ext := ? }, blocks := ? } }, { data_egprs := { mcs := ?, mac_hdr := ?, fbi := ?, e := ?, blocks := ? } }) PCU_Tests.ttcn:7692 PCU_Tests control part PCU_Tests.ttcn:4381 TC_dl_gprs_data_no_llc_ui_dummy testcase Expected 8 PDCH slots allocated but got 4 PCU_Tests.ttcn:7717 PCU_Tests control part PCU_Tests.ttcn:3442 TC_dl_multislot_tbf_ms_class_from_sgsn testcase Expected 1 PDCH slots allocated but got 4 PCU_Tests.ttcn:7718 PCU_Tests control part PCU_Tests.ttcn:3512 TC_dl_multislot_tbf_ms_class_unknown testcase