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"timestamp" : 1770632990000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/pespin", "fullName" : "Pau Espin Pedrol" }, "authorEmail" : "pespin@sysmocom.de", "comment" : "hnbgw: expected-results.xml: Add missing TC_sccp_cr_limit\u000a\u000aChange-Id: I4138cff311f82358f040290f3af483df8facc4cf\u000a", "date" : "2026-02-09 10:29:50 +0000", "id" : "13d6d38bb7ed843d27c6bcca9ec78d716103e869", "msg" : "hnbgw: expected-results.xml: Add missing TC_sccp_cr_limit", "paths" : [ { "editType" : "edit", "file" : "hnbgw/expected-results.xml" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "8ce558dd9294636c2ea397edbdcd38061f489d1d", "timestamp" : 1770640567000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: as_rsl_meas_res(): tolerate bad RxQual in early reports\u000a\u000aBit errors are expected during early stage of channel establishment.\u000aIgnore bad RxQual in the very first reports (4 * 0.480s = 1.92s).\u000a\u000aThis reduces probability of sporadic failures.\u000a\u000aChange-Id: Ie8acb15b66cd92092ec49bc8caeaf0ad4d471f1d\u000aRelated: OS#6933\u000a", "date" : "2026-02-09 12:36:07 +0000", "id" : "8ce558dd9294636c2ea397edbdcd38061f489d1d", "msg" : "bts: as_rsl_meas_res(): tolerate bad RxQual in early reports", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "b15aa10ce5eb103c573b1b7e63bde24a59de2c53", "timestamp" : 1770640567000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: as_rsl_meas_res(): do not expect dummy UL SACCH\u000a\u000aWe're now populating the UL SACCH cache before establishing a\u000adecicated channel in f_est_dchan(), so this special case is\u000ano longer needed and can be safely removed.\u000a\u000aChange-Id: I6eeee2876a76d41ab453af4c7724173fea773b83\u000aRelated: I4781fe7539e64e77d594e84f905646c127f46b64\u000aRelated: OS#6933\u000a", "date" : "2026-02-09 12:36:07 +0000", "id" : "b15aa10ce5eb103c573b1b7e63bde24a59de2c53", "msg" : "bts: as_rsl_meas_res(): do not expect dummy UL SACCH", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "8287922724dea28f845c34304d5a8fddfe851edb", "timestamp" : 1770640878000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: f_verify_ramp_up(): fix RxLev / dBm mixup\u000a\u000aComparing RxLev and dBm values is comparing apples to oranges. It's\u000ajust a lucky coincidence that fake_trx is using RF path loss value of\u000a110 dB, which is also the offset between RxLev and dBm.\u000a\u000a* Add `mp_rf_path_loss` matching the default value (110 dB) in fake_trx.\u000a* Add `f_bts_max_rx_level_dbm()` calculating the expected Rx power level.\u000a* Apply `rxlev2dbm()` on `l1_dl.dl_info.rx_level` whenever needed.\u000a* Clarify the units in verdict / logging messages.\u000a\u000aChange-Id: I818d18d6e0711247b73ee1f336133e2ed3f6e2cb\u000aRelated: OS#6939\u000a", "date" : "2026-02-09 12:41:18 +0000", "id" : "8287922724dea28f845c34304d5a8fddfe851edb", "msg" : "bts: f_verify_ramp_up(): fix RxLev / dBm mixup", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "836c96ae708d095b8603d2b3b3fba2e8d14a508e", "timestamp" : 1770640878000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: fix TC_rsl_ms_pwr_dyn_ass_updown: simulate a good C/I value\u000a\u000aNow that we populate the UL SACCH cache in advance, trxcon is sending\u000ams-pwr-lvl 7 in the first UL SACCH block (as expected). This suddenly\u000amakes the testcase fail, because now the MS power loop is perfectly\u000ahappy about the received input values and does not order any changes\u000ato the current MS power level anymore, contrary to our expectations.\u000a\u000aWhy? Short answer: because of C/I (curr 6, avg 6) being outside of\u000athe good range (thresh 13..17). The MS power loop intentionally\u000aavoids reducing Tx power because that would potentially degrade the\u000alink quality (C/I) even further. Solution: let's order fake_trx.py\u000ato simulate a C/I value that is within the thresholds.\u000a\u000aThis alone does not fix the testcase yet, another fix follows.\u000a\u000aChange-Id: I8926fc925e930bc2703210931b613988161a72da\u000aRelated: c246f207 (\"bts: f_est_dchan(): populate UL SACCH cache\")\u000aRelated: OS#6945\u000a", "date" : "2026-02-09 12:41:18 +0000", "id" : "836c96ae708d095b8603d2b3b3fba2e8d14a508e", "msg" : "bts: fix TC_rsl_ms_pwr_dyn_ass_updown: simulate a good C/I value", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "787f3c571017ccadec975b51f977a699a45ab951", "timestamp" : 1770640878000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: fix TC_rsl_ms_pwr_dyn_ass_updown: adjust the timers\u000a\u000aThis testcase predates major changes to the MS power control logic\u000ain osmo-bts and was passing thanks to a coincidence (broken UL SACCH\u000acache in trxcon). Specifically, the MS power loop is now using\u000aP_Con_INTERVAL=4 by default. This means that the power control\u000adecision is intentionally delayed and a change may occur only once\u000ain a period of 4 SACCH blocks (N=4 is ~1.92s).\u000a\u000aAdjust the timer values to take this into account. Take a chance\u000ato move comments in-place and expand them with more details.\u000a\u000aThis patch makes TC_rsl_ms_pwr_dyn_ass_updown pass again.\u000a\u000aChange-Id: I36d87c12f49ec13003b708d768285aa6840e81eb\u000aRelated: OS#6945\u000a", "date" : "2026-02-09 12:41:18 +0000", "id" : "787f3c571017ccadec975b51f977a699a45ab951", "msg" : "bts: fix TC_rsl_ms_pwr_dyn_ass_updown: adjust the timers", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "b508408549f43f4bb02bc93ab97389d809e6ea33", "timestamp" : 1770640878000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, "authorEmail" : "laforge@osmocom.org", "comment" : "bts: TC_rsl_ms_pwr_dyn_ass_updown: misc improvements\u000a\u000aChange-Id: Iae3fa5f09d68bd472f7236bf882f5b168d87384a\u000aRelated: OS#6945\u000a", "date" : "2026-02-09 12:41:18 +0000", "id" : "b508408549f43f4bb02bc93ab97389d809e6ea33", "msg" : "bts: TC_rsl_ms_pwr_dyn_ass_updown: misc improvements", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] } ], "kind" : "git" }, "culprits" : [ { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/laforge", "fullName" : "laforge" }, { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/pespin", "fullName" : "Pau Espin Pedrol" } ] }