// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

#include <dt-bindings/clock/nvidia,tegra264.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/nvidia,tegra264.h>
#include <dt-bindings/power/nvidia,tegra264-bpmp.h>
#include <dt-bindings/reset/nvidia,tegra264.h>

/ {
	compatible = "nvidia,tegra264";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		shmem_bpmp: shmem@86070000 {
			compatible = "nvidia,tegra264-bpmp-shmem";
			reg = <0x0 0x86070000 0x0 0x2000>;
			no-map;
		};
	};

	/* SYSTEM MMIO */
	bus@0 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;

		misc@100000 {
			compatible = "nvidia,tegra234-misc";
			reg = <0x0 0x00100000 0x0 0x0f000>,
			      <0x0 0x0c140000 0x0 0x10000>;
		};

		timer@8000000 {
			compatible = "nvidia,tegra234-timer";
			reg = <0x0 0x08000000 0x0 0x140000>;
			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		aconnect@9000000 {
			compatible = "nvidia,tegra264-aconnect",
					"nvidia,tegra210-aconnect";
			clocks = <&bpmp TEGRA264_CLK_APE>,
				<&bpmp TEGRA264_CLK_ADSP>;
			clock-names = "ape", "apb2ape";
			power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
			status = "disabled";

			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>;

			adma: dma-controller@9440000 {
				compatible = "nvidia,tegra264-adma";
				reg = <0x0 0x9440000 0x0 0xb0000>;
				interrupt-parent = <&agic_page0>;
				interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>,
					   <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>;
				#dma-cells = <1>;
				clocks = <&bpmp TEGRA264_CLK_AHUB>;
				clock-names = "d_audio";
				status = "disabled";
			};

			tegra_ahub: ahub@9630000 {
				compatible = "nvidia,tegra264-ahub";
				reg = <0x0 0x9630000 0x0 0x10000>;
				clocks = <&bpmp TEGRA264_CLK_AHUB>;
				clock-names = "ahub";
				assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>;
				assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>;
				status = "disabled";

				#address-cells = <2>;
				#size-cells = <2>;
				/* ADMA is under AHUB range, its excluded in the defined range */
				ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>,
					<0x0 0x9510000 0x0 0x9510000 0x0 0x370000>;

				tegra_i2s1: i2s@9280000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x9280000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S1>,
					       <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S1";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s1_cif: endpoint {
								remote-endpoint = <&xbar_i2s1>;
							};
						};

						i2s1_port: port@1 {
							reg = <1>;

							i2s1_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s2: i2s@9290000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x9290000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S2>,
						 <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S2";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s2_cif: endpoint {
								remote-endpoint = <&xbar_i2s2>;
							};
						};

						i2s2_port: port@1 {
							reg = <1>;

							i2s2_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s3: i2s@92a0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92a0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S3>,
					       <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S3";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s3_cif: endpoint {
								remote-endpoint = <&xbar_i2s3>;
							};
						};

						i2s3_port: port@1 {
							reg = <1>;

							i2s3_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s4: i2s@92b0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92b0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S4>,
					       <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S4";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s4_cif: endpoint {
								remote-endpoint = <&xbar_i2s4>;
							};
						};

						i2s4_port: port@1 {
							reg = <1>;

							i2s4_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s5: i2s@92c0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92c0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S5>,
					       <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S5";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s5_cif: endpoint {
								remote-endpoint = <&xbar_i2s5>;
							};
						};

						i2s5_port: port@1 {
							reg = <1>;

							i2s5_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s6: i2s@92d0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92d0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S6>,
					       <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S6";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s6_cif: endpoint {
								remote-endpoint = <&xbar_i2s6>;
							};
						};

						i2s6_port: port@1 {
							reg = <1>;

							i2s6_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s7: i2s@92e0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92e0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S7>,
					       <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S7";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s7_cif: endpoint {
								remote-endpoint = <&xbar_i2s7>;
							};
						};

						i2s7_port: port@1 {
							reg = <1>;

							i2s7_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_i2s8: i2s@92f0000 {
					compatible = "nvidia,tegra264-i2s";
					reg = <0x0 0x92f0000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_I2S8>,
					       <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>;
					clock-names = "i2s", "sync_input";
					assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <1536000>;
					sound-name-prefix = "I2S8";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s8_cif: endpoint {
								remote-endpoint = <&xbar_i2s8>;
							};
						};

						i2s8_port: port@1 {
							reg = <1>;

							i2s8_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_dmic1: dmic@9300000 {
					compatible = "nvidia,tegra264-dmic",
							"nvidia,tegra210-dmic";
					reg = <0x0 0x9300000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_DMIC1>;
					clock-names = "dmic";
					assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <3072000>;
					sound-name-prefix = "DMIC1";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							dmic1_cif: endpoint {
								remote-endpoint = <&xbar_dmic1>;
							};
						};

						dmic1_port: port@1 {
							reg = <1>;

							dmic1_dap: endpoint {
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_dmic2: dmic@9310000 {
					compatible = "nvidia,tegra264-dmic",
						   "nvidia,tegra210-dmic";
					reg = <0x0 0x9310000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_DMIC1>;
					clock-names = "dmic";
					assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <3072000>;
					sound-name-prefix = "DMIC2";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							dmic2_cif: endpoint {
								remote-endpoint = <&xbar_dmic2>;
							};
						};

						dmic2_port: port@1 {
							reg = <1>;

							dmic2_dap: endpoint {
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_dspk1: dspk@9380000 {
					compatible = "nvidia,tegra264-dspk",
							"nvidia,tegra186-dspk";
					reg = <0x0 0x9380000 0x0 0x10000>;
					clocks = <&bpmp TEGRA264_CLK_DSPK1>;
					clock-names = "dspk";
					assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>;
					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
					assigned-clock-rates = <12288000>;
					sound-name-prefix = "DSPK1";
					status = "disabled";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							dspk1_cif: endpoint {
								remote-endpoint = <&xbar_dspk1>;
							};
						};

						dspk1_port: port@1 {
							reg = <1>;

							dspk1_dap: endpoint {
								/* placeholder for external codec */
							};
						};
					};
				};

				tegra_amx1: amx@9510000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9510000 0x0 0x10000>;
					sound-name-prefix = "AMX1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx1_in1: endpoint {
								remote-endpoint = <&xbar_amx1_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx1_in2: endpoint {
								remote-endpoint = <&xbar_amx1_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx1_in3: endpoint {
								remote-endpoint = <&xbar_amx1_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx1_in4: endpoint {
								remote-endpoint = <&xbar_amx1_in4>;
							};
						};

						amx1_out_port: port@4 {
							reg = <4>;

							amx1_out: endpoint {
								remote-endpoint = <&xbar_amx1_out>;
							};
						};
					};
				};

				tegra_amx2: amx@9520000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9520000 0x0 0x10000>;
					sound-name-prefix = "AMX2";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx2_in1: endpoint {
								remote-endpoint = <&xbar_amx2_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx2_in2: endpoint {
								remote-endpoint = <&xbar_amx2_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx2_in3: endpoint {
								remote-endpoint = <&xbar_amx2_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx2_in4: endpoint {
								remote-endpoint = <&xbar_amx2_in4>;
							};
						};

						amx2_out_port: port@4 {
							reg = <4>;

							amx2_out: endpoint {
								remote-endpoint = <&xbar_amx2_out>;
							};
						};
					};
				};

				tegra_amx3: amx@9530000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9530000 0x0 0x10000>;
					sound-name-prefix = "AMX3";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx3_in1: endpoint {
								remote-endpoint = <&xbar_amx3_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx3_in2: endpoint {
								remote-endpoint = <&xbar_amx3_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx3_in3: endpoint {
								remote-endpoint = <&xbar_amx3_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx3_in4: endpoint {
								remote-endpoint = <&xbar_amx3_in4>;
							};
						};

						amx3_out_port: port@4 {
							reg = <4>;

							amx3_out: endpoint {
								remote-endpoint = <&xbar_amx3_out>;
							};
						};
					};
				};

				tegra_amx4: amx@9540000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9540000 0x0 0x10000>;
					sound-name-prefix = "AMX4";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx4_in1: endpoint {
								remote-endpoint = <&xbar_amx4_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx4_in2: endpoint {
								remote-endpoint = <&xbar_amx4_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx4_in3: endpoint {
								remote-endpoint = <&xbar_amx4_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx4_in4: endpoint {
								remote-endpoint = <&xbar_amx4_in4>;
							};
						};

						amx4_out_port: port@4 {
							reg = <4>;

							amx4_out: endpoint {
								remote-endpoint = <&xbar_amx4_out>;
							};
						};
					};
				};

				tegra_amx5: amx@9550000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9550000 0x0 0x10000>;
					sound-name-prefix = "AMX5";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx5_in1: endpoint {
								remote-endpoint = <&xbar_amx5_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx5_in2: endpoint {
								remote-endpoint = <&xbar_amx5_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx5_in3: endpoint {
								remote-endpoint = <&xbar_amx5_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx5_in4: endpoint {
								remote-endpoint = <&xbar_amx5_in4>;
							};
						};

						amx5_out_port: port@4 {
							reg = <4>;

							amx5_out: endpoint {
								remote-endpoint = <&xbar_amx5_out>;
							};
						};
					};
				};

				tegra_amx6: amx@9560000 {
					compatible = "nvidia,tegra264-amx";
					reg = <0x0 0x9560000 0x0 0x10000>;
					sound-name-prefix = "AMX6";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx6_in1: endpoint {
								remote-endpoint = <&xbar_amx6_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx6_in2: endpoint {
								remote-endpoint = <&xbar_amx6_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx6_in3: endpoint {
								remote-endpoint = <&xbar_amx6_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx6_in4: endpoint {
								remote-endpoint = <&xbar_amx6_in4>;
							};
						};

						amx6_out_port: port@4 {
							reg = <4>;

							amx6_out: endpoint {
								remote-endpoint = <&xbar_amx6_out>;
							};
						};
					};
				};

				tegra_adx1: adx@9590000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x9590000 0x0 0x10000>;
					sound-name-prefix = "ADX1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx1_in: endpoint {
								remote-endpoint = <&xbar_adx1_in>;
							};
						};

						adx1_out1_port: port@1 {
							reg = <1>;

							adx1_out1: endpoint {
								remote-endpoint = <&xbar_adx1_out1>;
							};
						};

						adx1_out2_port: port@2 {
							reg = <2>;

							adx1_out2: endpoint {
								remote-endpoint = <&xbar_adx1_out2>;
							};
						};

						adx1_out3_port: port@3 {
							reg = <3>;

							adx1_out3: endpoint {
								remote-endpoint = <&xbar_adx1_out3>;
							};
						};

						adx1_out4_port: port@4 {
							reg = <4>;

							adx1_out4: endpoint {
								remote-endpoint = <&xbar_adx1_out4>;
							};
						};
					};
				};

				tegra_adx2: adx@95a0000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x95a0000 0x0 0x10000>;
					sound-name-prefix = "ADX2";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx2_in: endpoint {
								remote-endpoint = <&xbar_adx2_in>;
							};
						};

						adx2_out1_port: port@1 {
							reg = <1>;

							adx2_out1: endpoint {
								remote-endpoint = <&xbar_adx2_out1>;
							};
						};

						adx2_out2_port: port@2 {
							reg = <2>;

							adx2_out2: endpoint {
								remote-endpoint = <&xbar_adx2_out2>;
							};
						};

						adx2_out3_port: port@3 {
							reg = <3>;

							adx2_out3: endpoint {
								remote-endpoint = <&xbar_adx2_out3>;
							};
						};

						adx2_out4_port: port@4 {
							reg = <4>;

							adx2_out4: endpoint {
								remote-endpoint = <&xbar_adx2_out4>;
							};
						};
					};
				};

				tegra_adx3: adx@95b0000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x95b0000 0x0 0x10000>;
					sound-name-prefix = "ADX3";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx3_in: endpoint {
								remote-endpoint = <&xbar_adx3_in>;
							};
						};

						adx3_out1_port: port@1 {
							reg = <1>;

							adx3_out1: endpoint {
								remote-endpoint = <&xbar_adx3_out1>;
							};
						};

						adx3_out2_port: port@2 {
							reg = <2>;

							adx3_out2: endpoint {
								remote-endpoint = <&xbar_adx3_out2>;
							};
						};

						adx3_out3_port: port@3 {
							reg = <3>;

							adx3_out3: endpoint {
								remote-endpoint = <&xbar_adx3_out3>;
							};
						};

						adx3_out4_port: port@4 {
							reg = <4>;

							adx3_out4: endpoint {
								remote-endpoint = <&xbar_adx3_out4>;
							};
						};
					};
				};

				tegra_adx4: adx@95c0000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x95c0000 0x0 0x10000>;
					sound-name-prefix = "ADX4";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx4_in: endpoint {
								remote-endpoint = <&xbar_adx4_in>;
							};
						};

						adx4_out1_port: port@1 {
							reg = <1>;

							adx4_out1: endpoint {
								remote-endpoint = <&xbar_adx4_out1>;
							};
						};

						adx4_out2_port: port@2 {
							reg = <2>;

							adx4_out2: endpoint {
								remote-endpoint = <&xbar_adx4_out2>;
							};
						};

						adx4_out3_port: port@3 {
							reg = <3>;

							adx4_out3: endpoint {
								remote-endpoint = <&xbar_adx4_out3>;
							};
						};

						adx4_out4_port: port@4 {
							reg = <4>;

							adx4_out4: endpoint {
								remote-endpoint = <&xbar_adx4_out4>;
							};
						};
					};
				};

				tegra_adx5: adx@95d0000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x95d0000 0x0 0x10000>;
					sound-name-prefix = "ADX5";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx5_in: endpoint {
								remote-endpoint = <&xbar_adx5_in>;
							};
						};

						adx5_out1_port: port@1 {
							reg = <1>;

							adx5_out1: endpoint {
								remote-endpoint = <&xbar_adx5_out1>;
							};
						};

						adx5_out2_port: port@2 {
							reg = <2>;

							adx5_out2: endpoint {
								remote-endpoint = <&xbar_adx5_out2>;
							};
						};

						adx5_out3_port: port@3 {
							reg = <3>;

							adx5_out3: endpoint {
								remote-endpoint = <&xbar_adx5_out3>;
							};
						};

						adx5_out4_port: port@4 {
							reg = <4>;

							adx5_out4: endpoint {
								remote-endpoint = <&xbar_adx5_out4>;
							};
						};
					};
				};

				tegra_adx6: adx@95e0000 {
					compatible = "nvidia,tegra264-adx";
					reg = <0x0 0x95e0000 0x0 0x10000>;
					sound-name-prefix = "ADX6";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx6_in: endpoint {
								remote-endpoint = <&xbar_adx6_in>;
							};
						};

						adx6_out1_port: port@1 {
							reg = <1>;

							adx6_out1: endpoint {
								remote-endpoint = <&xbar_adx6_out1>;
							};
						};

						adx6_out2_port: port@2 {
							reg = <2>;

							adx6_out2: endpoint {
								remote-endpoint = <&xbar_adx6_out2>;
							};
						};

						adx6_out3_port: port@3 {
							reg = <3>;

							adx6_out3: endpoint {
								remote-endpoint = <&xbar_adx6_out3>;
							};
						};

						adx6_out4_port: port@4 {
							reg = <4>;

							adx6_out4: endpoint {
								remote-endpoint = <&xbar_adx6_out4>;
							};
						};
					};
				};

				tegra_admaif: admaif@9610000 {
					compatible = "nvidia,tegra264-admaif";
					reg = <0x0 0x9610000 0x0 0x10000>;
					dmas = <&adma 1>, <&adma 1>,
					     <&adma 2>, <&adma 2>,
					     <&adma 3>, <&adma 3>,
					     <&adma 4>, <&adma 4>,
					     <&adma 5>, <&adma 5>,
					     <&adma 6>, <&adma 6>,
					     <&adma 7>, <&adma 7>,
					     <&adma 8>, <&adma 8>,
					     <&adma 9>, <&adma 9>,
					     <&adma 10>, <&adma 10>,
					     <&adma 11>, <&adma 11>,
					     <&adma 12>, <&adma 12>,
					     <&adma 13>, <&adma 13>,
					     <&adma 14>, <&adma 14>,
					     <&adma 15>, <&adma 15>,
					     <&adma 16>, <&adma 16>,
					     <&adma 17>, <&adma 17>,
					     <&adma 18>, <&adma 18>,
					     <&adma 19>, <&adma 19>,
					     <&adma 20>, <&adma 20>,
					     <&adma 21>, <&adma 21>,
					     <&adma 22>, <&adma 22>,
					     <&adma 23>, <&adma 23>,
					     <&adma 24>, <&adma 24>,
					     <&adma 25>, <&adma 25>,
					     <&adma 26>, <&adma 26>,
					     <&adma 27>, <&adma 27>,
					     <&adma 28>, <&adma 28>,
					     <&adma 29>, <&adma 29>,
					     <&adma 30>, <&adma 30>,
					     <&adma 31>, <&adma 31>,
					     <&adma 32>, <&adma 32>;
					dma-names = "rx1", "tx1",
						"rx2", "tx2",
						"rx3", "tx3",
						"rx4", "tx4",
						"rx5", "tx5",
						"rx6", "tx6",
						"rx7", "tx7",
						"rx8", "tx8",
						"rx9", "tx9",
						"rx10", "tx10",
						"rx11", "tx11",
						"rx12", "tx12",
						"rx13", "tx13",
						"rx14", "tx14",
						"rx15", "tx15",
						"rx16", "tx16",
						"rx17", "tx17",
						"rx18", "tx18",
						"rx19", "tx19",
						"rx20", "tx20",
						"rx21", "tx21",
						"rx22", "tx22",
						"rx23", "tx23",
						"rx24", "tx24",
						"rx25", "tx25",
						"rx26", "tx26",
						"rx27", "tx27",
						"rx28", "tx28",
						"rx29", "tx29",
						"rx30", "tx30",
						"rx31", "tx31",
						"rx32", "tx32";

					 interconnects =
						<&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>,
						<&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>;
						interconnect-names = "dma-mem", "write";

					iommus = <&smmu1 TEGRA264_SID_APE>;

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						admaif0_port: port@0 {
							reg = <0x0>;

							admaif0: endpoint {
								remote-endpoint = <&xbar_admaif0>;
							};
						};

						admaif1_port: port@1 {
							reg = <0x1>;

							admaif1: endpoint {
								remote-endpoint = <&xbar_admaif1>;
							};
						};

						admaif2_port: port@2 {
							reg = <0x2>;

							admaif2: endpoint {
								remote-endpoint = <&xbar_admaif2>;
							};
						};

						admaif3_port: port@3 {
							reg = <0x3>;

							admaif3: endpoint {
								remote-endpoint = <&xbar_admaif3>;
							};
						};

						admaif4_port: port@4 {
							reg = <0x4>;

							admaif4: endpoint {
								remote-endpoint = <&xbar_admaif4>;
							};
						};

						admaif5_port: port@5 {
							reg = <0x5>;

							admaif5: endpoint {
								remote-endpoint = <&xbar_admaif5>;
							};
						};

						admaif6_port: port@6 {
							reg = <0x6>;

							admaif6: endpoint {
								remote-endpoint = <&xbar_admaif6>;
							};
						};

						admaif7_port: port@7 {
							reg = <0x7>;

							admaif7: endpoint {
								remote-endpoint = <&xbar_admaif7>;
							};
						};

						admaif8_port: port@8 {
							reg = <0x8>;

							admaif8: endpoint {
								remote-endpoint = <&xbar_admaif8>;
							};
						};

						admaif9_port: port@9 {
							reg = <0x9>;

							admaif9: endpoint {
								remote-endpoint = <&xbar_admaif9>;
							};
						};

						admaif10_port: port@a {
							reg = <0xa>;

							admaif10: endpoint {
								remote-endpoint = <&xbar_admaif10>;
							};
						};

						admaif11_port: port@b {
							reg = <0xb>;

							admaif11: endpoint {
								remote-endpoint = <&xbar_admaif11>;
							};
						};

						admaif12_port: port@c {
							reg = <0xc>;

							admaif12: endpoint {
								remote-endpoint = <&xbar_admaif12>;
							};
						};

						admaif13_port: port@d {
							reg = <0xd>;

							admaif13: endpoint {
								remote-endpoint = <&xbar_admaif13>;
							};
						};

						admaif14_port: port@e {
							reg = <0xe>;

							admaif14: endpoint {
								remote-endpoint = <&xbar_admaif14>;
							};
						};

						admaif15_port: port@f {
							reg = <0xf>;

							admaif15: endpoint {
								remote-endpoint = <&xbar_admaif15>;
							};
						};

						admaif16_port: port@10 {
							reg = <0x10>;

							admaif16: endpoint {
								remote-endpoint = <&xbar_admaif16>;
							};
						};

						admaif17_port: port@11 {
							reg = <0x11>;

							admaif17: endpoint {
								remote-endpoint = <&xbar_admaif17>;
							};
						};

						admaif18_port: port@12 {
							reg = <0x12>;

							admaif18: endpoint {
								remote-endpoint = <&xbar_admaif18>;
							};
						};

						admaif19_port: port@13 {
							reg = <0x13>;

							admaif19: endpoint {
								remote-endpoint = <&xbar_admaif19>;
							};
						};

						admaif20_port: port@14 {
							reg = <0x14>;

							admaif20: endpoint {
								remote-endpoint = <&xbar_admaif20>;
							};
						};

						admaif21_port: port@15 {
							reg = <0x15>;

							admaif21: endpoint {
								remote-endpoint = <&xbar_admaif21>;
							};
						};

						admaif22_port: port@16 {
							reg = <0x16>;

							admaif22: endpoint {
								remote-endpoint = <&xbar_admaif22>;
							};
						};

						admaif23_port: port@17 {
							reg = <0x17>;

							admaif23: endpoint {
								remote-endpoint = <&xbar_admaif23>;
							};
						};

						admaif24_port: port@18 {
							reg = <0x18>;

							admaif24: endpoint {
								remote-endpoint = <&xbar_admaif24>;
							};
						};

						admaif25_port: port@19 {
							reg = <0x19>;

							admaif25: endpoint {
								remote-endpoint = <&xbar_admaif25>;
							};
						};

						admaif26_port: port@1a {
							reg = <0x1a>;

							admaif26: endpoint {
								remote-endpoint = <&xbar_admaif26>;
							};
						};

						admaif27_port: port@1b {
							reg = <0x1b>;

							admaif27: endpoint {
								remote-endpoint = <&xbar_admaif27>;
							};
						};

						admaif28_port: port@1c {
							reg = <0x1c>;

							admaif28: endpoint {
								remote-endpoint = <&xbar_admaif28>;
							};
						};

						admaif29_port: port@1d {
							reg = <0x1d>;

							admaif29: endpoint {
								remote-endpoint = <&xbar_admaif29>;
							};
						};

						admaif30_port: port@1e {
							reg = <0x1e>;

							admaif30: endpoint {
								remote-endpoint = <&xbar_admaif30>;
							};
						};

						admaif31_port: port@1f {
							reg = <0x1f>;

							admaif31: endpoint {
								remote-endpoint = <&xbar_admaif31>;
							};
						};
					};
				};

				tegra_sfc1: sfc@9700000 {
					compatible = "nvidia,tegra264-sfc",
							"nvidia,tegra210-sfc";
					reg = <0x0 0x9700000 0x0 0x10000>;
					sound-name-prefix = "SFC1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc1_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc1_in>;
							};
						};

						sfc1_out_port: port@1 {
							reg = <1>;

							sfc1_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc1_out>;
							};
						};
					};
				};

				tegra_sfc2: sfc@9710000 {
					compatible = "nvidia,tegra264-sfc",
							"nvidia,tegra210-sfc";
					reg = <0x0 0x9710000 0x0 0x10000>;
					sound-name-prefix = "SFC2";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc2_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc2_in>;
							};
						};

						sfc2_out_port: port@1 {
							reg = <1>;

							sfc2_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc2_out>;
							};
						};
					};
				};

				tegra_sfc3: sfc@9720000 {
					compatible = "nvidia,tegra264-sfc",
							"nvidia,tegra210-sfc";
					reg = <0x0 0x9720000 0x0 0x10000>;
					sound-name-prefix = "SFC3";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc3_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc3_in>;
							};
						};

						sfc3_out_port: port@1 {
							reg = <1>;

							sfc3_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc3_out>;
							};
						};
					};
				};

				tegra_sfc4: sfc@9730000 {
					compatible = "nvidia,tegra264-sfc",
							"nvidia,tegra210-sfc";
					reg = <0x0 0x9730000 0x0 0x10000>;
					sound-name-prefix = "SFC4";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc4_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc4_in>;
							};
						};

						sfc4_out_port: port@1 {
							reg = <1>;

							sfc4_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc4_out>;
							};
						};
					};
				};

				tegra_ope1: processing-engine@9780000 {
					compatible = "nvidia,tegra264-ope",
							"nvidia,tegra210-ope";
					reg = <0x0 0x9780000 0x0 0x10000>;
					#address-cells = <2>;
					#size-cells = <2>;
					ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>;
					sound-name-prefix = "OPE1";

					equalizer@9790000 {
						compatible = "nvidia,tegra264-peq",
								"nvidia,tegra210-peq";
						reg = <0x0 0x9790000 0x0 0x10000>;
					};

					dynamic-range-compressor@97a0000 {
						compatible = "nvidia,tegra264-mbdrc",
								"nvidia,tegra210-mbdrc";
						reg = <0x0 0x97a0000 0x0 0x10000>;
					};

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							ope1_cif_in_ep: endpoint {
								remote-endpoint =
									<&xbar_ope1_in_ep>;
							};
						};

						ope1_out_port: port@1 {
							reg = <0x1>;

							ope1_cif_out_ep: endpoint {
								remote-endpoint =
									<&xbar_ope1_out_ep>;
							};
						};
					};
				};

				tegra_mvc1: mvc@9800000 {
					compatible = "nvidia,tegra264-mvc",
							"nvidia,tegra210-mvc";
					reg = <0x0 0x9800000 0x0 0x10000>;
					sound-name-prefix = "MVC1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							mvc1_cif_in: endpoint {
								remote-endpoint = <&xbar_mvc1_in>;
							};
						};

						mvc1_out_port: port@1 {
							reg = <1>;

							mvc1_cif_out: endpoint {
								remote-endpoint = <&xbar_mvc1_out>;
							};
						};
					};
				};

				tegra_mvc2: mvc@9810000 {
					compatible = "nvidia,tegra264-mvc",
							"nvidia,tegra210-mvc";
					reg = <0x0 0x9810000 0x0 0x10000>;
					sound-name-prefix = "MVC2";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							mvc2_cif_in: endpoint {
								remote-endpoint = <&xbar_mvc2_in>;
							};
						};

						mvc2_out_port: port@1 {
							reg = <1>;

							mvc2_cif_out: endpoint {
								remote-endpoint = <&xbar_mvc2_out>;
							};
						};
					};
				};

				tegra_amixer: amixer@9820000 {
					compatible = "nvidia,tegra264-amixer",
							"nvidia,tegra210-amixer";
					reg = <0x0 0x9820000 0x0 0x10000>;
					sound-name-prefix = "MIXER1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							mix_in1: endpoint {
								remote-endpoint = <&xbar_mix_in1>;
							};
						};

						port@1 {
							reg = <0x1>;

							mix_in2: endpoint {
								remote-endpoint = <&xbar_mix_in2>;
							};
						};

						port@2 {
							reg = <0x2>;

							mix_in3: endpoint {
								remote-endpoint = <&xbar_mix_in3>;
							};
						};

						port@3 {
							reg = <0x3>;

							mix_in4: endpoint {
								remote-endpoint = <&xbar_mix_in4>;
							};
						};

						port@4 {
							reg = <0x4>;

							mix_in5: endpoint {
								remote-endpoint = <&xbar_mix_in5>;
							};
						};

						port@5 {
							reg = <0x5>;

							mix_in6: endpoint {
								remote-endpoint = <&xbar_mix_in6>;
							};
						};

						port@6 {
							reg = <0x6>;

							mix_in7: endpoint {
								remote-endpoint = <&xbar_mix_in7>;
							};
						};

						port@7 {
							reg = <0x7>;

							mix_in8: endpoint {
								remote-endpoint = <&xbar_mix_in8>;
							};
						};

						port@8 {
							reg = <0x8>;

							mix_in9: endpoint {
								remote-endpoint = <&xbar_mix_in9>;
							};
						};

						port@9 {
							reg = <0x9>;

							mix_in10: endpoint {
								remote-endpoint = <&xbar_mix_in10>;
							};
						};

						mix_out1_port: port@a {
							reg = <0xa>;

							mix_out1: endpoint {
								remote-endpoint = <&xbar_mix_out1>;
							};
						};

						mix_out2_port: port@b {
							reg = <0xb>;

							mix_out2: endpoint {
								remote-endpoint = <&xbar_mix_out2>;
							};
						};

						mix_out3_port: port@c {
							reg = <0xc>;

							mix_out3: endpoint {
								remote-endpoint = <&xbar_mix_out3>;
							};
						};

						mix_out4_port: port@d {
							reg = <0xd>;

							mix_out4: endpoint {
								remote-endpoint = <&xbar_mix_out4>;
							};
						};

						mix_out5_port: port@e {
							reg = <0xe>;

							mix_out5: endpoint {
								remote-endpoint = <&xbar_mix_out5>;
							};
						};
					};
				};

				tegra_asrc: asrc@9850000 {
					compatible = "nvidia,tegra264-asrc";
					reg = <0x0 0x9850000 0x0 0x10000>;
					sound-name-prefix = "ASRC1";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							asrc_in1_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in1_ep>;
							};
						};

						port@1 {
							reg = <0x1>;

							asrc_in2_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in2_ep>;
							};
						};

						port@2 {
							reg = <0x2>;

							asrc_in3_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in3_ep>;
							};
						};

						port@3 {
							reg = <0x3>;

							asrc_in4_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in4_ep>;
							};
						};

						port@4 {
							reg = <0x4>;

							asrc_in5_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in5_ep>;
							};
						};

						port@5 {
							reg = <0x5>;

							asrc_in6_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in6_ep>;
							};
						};

						port@6 {
							reg = <0x6>;

							asrc_in7_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_in7_ep>;
							};
						};

						asrc_out1_port: port@7 {
							reg = <0x7>;

							asrc_out1_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out1_ep>;
							};
						};

						asrc_out2_port: port@8 {
							reg = <0x8>;

							asrc_out2_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out2_ep>;
							};
						};

						asrc_out3_port: port@9 {
							reg = <0x9>;

							asrc_out3_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out3_ep>;
							};
						};

						asrc_out4_port: port@a {
							reg = <0xa>;

							asrc_out4_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out4_ep>;
							};
						};

						asrc_out5_port: port@b {
							reg = <0xb>;

							asrc_out5_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out5_ep>;
							};
						};

						asrc_out6_port:	port@c {
							reg = <0xc>;

							asrc_out6_ep: endpoint {
								remote-endpoint =
									<&xbar_asrc_out6_ep>;
							};
						};
					};
				};

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0x0>;

						xbar_admaif0: endpoint {
							remote-endpoint = <&admaif0>;
						};
					};

					port@1 {
						reg = <0x1>;

						xbar_admaif1: endpoint {
							remote-endpoint = <&admaif1>;
						};
					};

					port@2 {
						reg = <0x2>;

						xbar_admaif2: endpoint {
							remote-endpoint = <&admaif2>;
						};
					};

					port@3 {
						reg = <0x3>;

						xbar_admaif3: endpoint {
							remote-endpoint = <&admaif3>;
						};
					};

					port@4 {
						reg = <0x4>;

						xbar_admaif4: endpoint {
							remote-endpoint = <&admaif4>;
						};
					};

					port@5 {
						reg = <0x5>;

						xbar_admaif5: endpoint {
							remote-endpoint = <&admaif5>;
						};
					};

					port@6 {
						reg = <0x6>;

						xbar_admaif6: endpoint {
							remote-endpoint = <&admaif6>;
						};
					};

					port@7 {
						reg = <0x7>;

						xbar_admaif7: endpoint {
							remote-endpoint = <&admaif7>;
						};
					};

					port@8 {
						reg = <0x8>;

						xbar_admaif8: endpoint {
							remote-endpoint = <&admaif8>;
						};
					};

					port@9 {
						reg = <0x9>;

						xbar_admaif9: endpoint {
							remote-endpoint = <&admaif9>;
						};
					};

					port@a {
						reg = <0xa>;

						xbar_admaif10: endpoint {
							remote-endpoint = <&admaif10>;
						};
					};

					port@b {
						reg = <0xb>;

						xbar_admaif11: endpoint {
							remote-endpoint = <&admaif11>;
						};
					};

					port@c {
						reg = <0xc>;

						xbar_admaif12: endpoint {
							remote-endpoint = <&admaif12>;
						};
					};

					port@d {
						reg = <0xd>;

						xbar_admaif13: endpoint {
							remote-endpoint = <&admaif13>;
						};
					};

					port@e {
						reg = <0xe>;

						xbar_admaif14: endpoint {
							remote-endpoint = <&admaif14>;
						};
					};

					port@f {
						reg = <0xf>;

						xbar_admaif15: endpoint {
							remote-endpoint = <&admaif15>;
						};
					};

					port@10 {
						reg = <0x10>;

						xbar_admaif16: endpoint {
							remote-endpoint = <&admaif16>;
						};
					};

					port@11 {
						reg = <0x11>;

						xbar_admaif17: endpoint {
							remote-endpoint = <&admaif17>;
						};
					};

					port@12 {
						reg = <0x12>;

						xbar_admaif18: endpoint {
							remote-endpoint = <&admaif18>;
						};
					};

					port@13 {
						reg = <0x13>;

						xbar_admaif19: endpoint {
							remote-endpoint = <&admaif19>;
						};
					};

					port@14 {
						reg = <0x14>;

						xbar_admaif20: endpoint {
							remote-endpoint = <&admaif20>;
						};
					};

					port@15 {
						reg = <0x15>;

						xbar_admaif21: endpoint {
							remote-endpoint = <&admaif21>;
						};
					};

					port@16 {
						reg = <0x16>;

						xbar_admaif22: endpoint {
							remote-endpoint = <&admaif22>;
						};
					};

					port@17 {
						reg = <0x17>;

						xbar_admaif23: endpoint {
							remote-endpoint = <&admaif23>;
						};
					};

					port@18 {
						reg = <0x18>;

						xbar_admaif24: endpoint {
							remote-endpoint = <&admaif24>;
						};
					};

					port@19 {
						reg = <0x19>;

						xbar_admaif25: endpoint {
							remote-endpoint = <&admaif25>;
						};
					};

					port@1a {
						reg = <0x1a>;

						xbar_admaif26: endpoint {
							remote-endpoint = <&admaif26>;
						};
					};

					port@1b {
						reg = <0x1b>;

						xbar_admaif27: endpoint {
							remote-endpoint = <&admaif27>;
						};
					};

					port@1c {
						reg = <0x1c>;

						xbar_admaif28: endpoint {
							remote-endpoint = <&admaif28>;
						};
					};

					port@1d {
						reg = <0x1d>;

						xbar_admaif29: endpoint {
							remote-endpoint = <&admaif29>;
						};
					};

					port@1e {
						reg = <0x1e>;

						xbar_admaif30: endpoint {
							remote-endpoint = <&admaif30>;
						};
					};

					port@1f {
						reg = <0x1f>;

						xbar_admaif31: endpoint {
							remote-endpoint = <&admaif31>;
						};
					};

					xbar_i2s1_port: port@20 {
						reg = <0x20>;

						xbar_i2s1: endpoint {
							remote-endpoint = <&i2s1_cif>;
						};
					};

					xbar_i2s2_port: port@21 {
						reg = <0x21>;

						xbar_i2s2: endpoint {
							remote-endpoint = <&i2s2_cif>;
						};
					};

					xbar_i2s3_port: port@22 {
						reg = <0x22>;

						xbar_i2s3: endpoint {
							remote-endpoint = <&i2s3_cif>;
						};
					};

					xbar_i2s4_port: port@23 {
						reg = <0x23>;

						xbar_i2s4: endpoint {
							remote-endpoint = <&i2s4_cif>;
						};
					};

					xbar_i2s5_port: port@24 {
						reg = <0x24>;

						xbar_i2s5: endpoint {
							remote-endpoint = <&i2s5_cif>;
						};
					};

					xbar_i2s6_port: port@25 {
						reg = <0x25>;

						xbar_i2s6: endpoint {
							remote-endpoint = <&i2s6_cif>;
						};
					};

					xbar_i2s7_port: port@26 {
						reg = <0x26>;

						xbar_i2s7: endpoint {
							remote-endpoint = <&i2s7_cif>;
						};
					};

					xbar_i2s8_port: port@27 {
						reg = <0x27>;

						xbar_i2s8: endpoint {
							remote-endpoint = <&i2s8_cif>;
						};
					};

					xbar_dmic1_port: port@28 {
						reg = <0x28>;

						xbar_dmic1: endpoint {
							remote-endpoint = <&dmic1_cif>;
						};
					};

					xbar_dmic2_port: port@29 {
						reg = <0x29>;

						xbar_dmic2: endpoint {
							remote-endpoint = <&dmic2_cif>;
						};
					};

					xbar_dspk1_port: port@2a {
						reg = <0x2a>;

						xbar_dspk1: endpoint {
							remote-endpoint = <&dspk1_cif>;
						};
					};

					xbar_sfc1_in_port: port@2b {
						reg = <0x2b>;

						xbar_sfc1_in: endpoint {
							remote-endpoint = <&sfc1_cif_in>;
						};
					};

					port@2c {
						reg = <0x2c>;

						xbar_sfc1_out: endpoint {
							remote-endpoint = <&sfc1_cif_out>;
						};
					};

					xbar_sfc2_in_port: port@2d {
						reg = <0x2d>;

						xbar_sfc2_in: endpoint {
							remote-endpoint = <&sfc2_cif_in>;
						};
					};

					port@2e {
						reg = <0x2e>;

						xbar_sfc2_out: endpoint {
							remote-endpoint = <&sfc2_cif_out>;
						};
					};

					xbar_sfc3_in_port: port@2f {
						reg = <0x2f>;

						xbar_sfc3_in: endpoint {
							remote-endpoint = <&sfc3_cif_in>;
						};
					};

					port@30 {
						reg = <0x30>;

						xbar_sfc3_out: endpoint {
							remote-endpoint = <&sfc3_cif_out>;
						};
					};

					xbar_sfc4_in_port: port@31 {
						reg = <0x31>;

						xbar_sfc4_in: endpoint {
							remote-endpoint = <&sfc4_cif_in>;
						};
					};

					port@32 {
						reg = <0x32>;

						xbar_sfc4_out: endpoint {
							remote-endpoint = <&sfc4_cif_out>;
						};
					};

					xbar_mvc1_in_port: port@33 {
						reg = <0x33>;

						xbar_mvc1_in: endpoint {
							remote-endpoint = <&mvc1_cif_in>;
						};
					};

					port@34 {
						reg = <0x34>;

						xbar_mvc1_out: endpoint {
							remote-endpoint = <&mvc1_cif_out>;
						};
					};

					xbar_mvc2_in_port: port@35 {
						reg = <0x35>;

						xbar_mvc2_in: endpoint {
							remote-endpoint = <&mvc2_cif_in>;
						};
					};

					port@36 {
						reg = <0x36>;

						xbar_mvc2_out: endpoint {
							remote-endpoint = <&mvc2_cif_out>;
						};
					};

					xbar_amx1_in1_port: port@37 {
						reg = <0x37>;

						xbar_amx1_in1: endpoint {
							remote-endpoint = <&amx1_in1>;
						};
					};

					xbar_amx1_in2_port: port@38 {
						reg = <0x38>;

						xbar_amx1_in2: endpoint {
							remote-endpoint = <&amx1_in2>;
						};
					};

					xbar_amx1_in3_port: port@39 {
						reg = <0x39>;

						xbar_amx1_in3: endpoint {
							remote-endpoint = <&amx1_in3>;
						};
					};

					xbar_amx1_in4_port: port@3a {
						reg = <0x3a>;

						xbar_amx1_in4: endpoint {
							remote-endpoint = <&amx1_in4>;
						};
					};

					port@3b {
						reg = <0x3b>;

						xbar_amx1_out: endpoint {
							remote-endpoint = <&amx1_out>;
						};
					};

					xbar_amx2_in1_port: port@3c {
						reg = <0x3c>;

						xbar_amx2_in1: endpoint {
							remote-endpoint = <&amx2_in1>;
						};
					};

					xbar_amx2_in2_port: port@3d {
						reg = <0x3d>;

						xbar_amx2_in2: endpoint {
							remote-endpoint = <&amx2_in2>;
						};
					};

					xbar_amx2_in3_port: port@3e {
						reg = <0x3e>;

						xbar_amx2_in3: endpoint {
							remote-endpoint = <&amx2_in3>;
						};
					};

					xbar_amx2_in4_port: port@3f {
						reg = <0x3f>;

						xbar_amx2_in4: endpoint {
							remote-endpoint = <&amx2_in4>;
						};
					};

					port@40 {
						reg = <0x40>;

						xbar_amx2_out: endpoint {
							remote-endpoint = <&amx2_out>;
						};
					};

					xbar_amx3_in1_port: port@41 {
						reg = <0x41>;

						xbar_amx3_in1: endpoint {
							remote-endpoint = <&amx3_in1>;
						};
					};

					xbar_amx3_in2_port: port@42 {
						reg = <0x42>;

						xbar_amx3_in2: endpoint {
							remote-endpoint = <&amx3_in2>;
						};
					};

					xbar_amx3_in3_port: port@43 {
						reg = <0x43>;

						xbar_amx3_in3: endpoint {
							remote-endpoint = <&amx3_in3>;
						};
					};

					xbar_amx3_in4_port: port@44 {
						reg = <0x44>;

						xbar_amx3_in4: endpoint {
							remote-endpoint = <&amx3_in4>;
						};
					};

					port@45 {
						reg = <0x45>;

						xbar_amx3_out: endpoint {
							remote-endpoint = <&amx3_out>;
						};
					};

					xbar_amx4_in1_port: port@46 {
						reg = <0x46>;

						xbar_amx4_in1: endpoint {
							remote-endpoint = <&amx4_in1>;
						};
					};

					xbar_amx4_in2_port: port@47 {
						reg = <0x47>;

						xbar_amx4_in2: endpoint {
							remote-endpoint = <&amx4_in2>;
						};
					};

					xbar_amx4_in3_port: port@48 {
						reg = <0x48>;

						xbar_amx4_in3: endpoint {
							remote-endpoint = <&amx4_in3>;
						};
					};

					xbar_amx4_in4_port: port@49 {
						reg = <0x49>;

						xbar_amx4_in4: endpoint {
							remote-endpoint = <&amx4_in4>;
						};
					};

					port@4a {
						reg = <0x4a>;

						xbar_amx4_out: endpoint {
							remote-endpoint = <&amx4_out>;
						};
					};

					xbar_amx5_in1_port: port@4b {
						reg = <0x4b>;

						xbar_amx5_in1: endpoint {
							remote-endpoint = <&amx5_in1>;
						};
					};

					xbar_amx5_in2_port: port@4c {
						reg = <0x4c>;

						xbar_amx5_in2: endpoint {
							remote-endpoint = <&amx5_in2>;
						};
					};

					xbar_amx5_in3_port: port@4d {
						reg = <0x4d>;

						xbar_amx5_in3: endpoint {
							remote-endpoint = <&amx5_in3>;
						};
					};

					xbar_amx5_in4_port: port@4e {
						reg = <0x4e>;

						xbar_amx5_in4: endpoint {
							remote-endpoint = <&amx5_in4>;
						};
					};

					port@4f {
						reg = <0x4f>;

						xbar_amx5_out: endpoint {
							remote-endpoint = <&amx5_out>;
						};
					};

					xbar_amx6_in1_port: port@50 {
						reg = <0x50>;

						xbar_amx6_in1: endpoint {
							remote-endpoint = <&amx6_in1>;
						};
					};

					xbar_amx6_in2_port: port@51 {
						reg = <0x51>;

						xbar_amx6_in2: endpoint {
							remote-endpoint = <&amx6_in2>;
						};
					};

					xbar_amx6_in3_port: port@52 {
						reg = <0x52>;

						xbar_amx6_in3: endpoint {
							remote-endpoint = <&amx6_in3>;
						};
					};

					xbar_amx6_in4_port: port@53 {
						reg = <0x53>;

						xbar_amx6_in4: endpoint {
							remote-endpoint = <&amx6_in4>;
						};
					};

					port@54 {
						reg = <0x54>;

						xbar_amx6_out: endpoint {
							remote-endpoint = <&amx6_out>;
						};
					};

					xbar_adx1_in_port: port@55 {
						reg = <0x55>;

						xbar_adx1_in: endpoint {
							remote-endpoint = <&adx1_in>;
						};
					};

					port@56 {
						reg = <0x56>;

						xbar_adx1_out1: endpoint {
							remote-endpoint = <&adx1_out1>;
						};
					};

					port@57 {
						reg = <0x57>;

						xbar_adx1_out2: endpoint {
							remote-endpoint = <&adx1_out2>;
						};
					};

					port@58 {
						reg = <0x58>;

						xbar_adx1_out3: endpoint {
							remote-endpoint = <&adx1_out3>;
						};
					};

					port@59 {
						reg = <0x59>;

						xbar_adx1_out4: endpoint {
							remote-endpoint = <&adx1_out4>;
						};
					};

					xbar_adx2_in_port: port@5a {
						reg = <0x5a>;

						xbar_adx2_in: endpoint {
							remote-endpoint = <&adx2_in>;
						};
					};

					port@5b {
						reg = <0x5b>;

						xbar_adx2_out1: endpoint {
							remote-endpoint = <&adx2_out1>;
						};
					};

					port@5c {
						reg = <0x5c>;

						xbar_adx2_out2: endpoint {
							remote-endpoint = <&adx2_out2>;
						};
					};

					port@5d {
						reg = <0x5d>;

						xbar_adx2_out3: endpoint {
							remote-endpoint = <&adx2_out3>;
						};
					};

					port@5e {
						reg = <0x5e>;

						xbar_adx2_out4: endpoint {
							remote-endpoint = <&adx2_out4>;
						};
					};

					xbar_adx3_in_port: port@5f {
						reg = <0x5f>;

						xbar_adx3_in: endpoint {
							remote-endpoint = <&adx3_in>;
						};
					};

					port@60 {
						reg = <0x60>;

						xbar_adx3_out1: endpoint {
							remote-endpoint = <&adx3_out1>;
						};
					};

					port@61 {
						reg = <0x61>;

						xbar_adx3_out2: endpoint {
							remote-endpoint = <&adx3_out2>;
						};
					};

					port@62 {
						reg = <0x62>;

						xbar_adx3_out3: endpoint {
							remote-endpoint = <&adx3_out3>;
						};
					};

					port@63 {
						reg = <0x63>;

						xbar_adx3_out4: endpoint {
							remote-endpoint = <&adx3_out4>;
						};
					};

					xbar_adx4_in_port: port@64 {
						reg = <0x64>;

						xbar_adx4_in: endpoint {
							remote-endpoint = <&adx4_in>;
						};
					};

					port@65 {
						reg = <0x65>;

						xbar_adx4_out1: endpoint {
							remote-endpoint = <&adx4_out1>;
						};
					};

					port@66 {
						reg = <0x66>;

						xbar_adx4_out2: endpoint {
							remote-endpoint = <&adx4_out2>;
						};
					};

					port@67 {
						reg = <0x67>;

						xbar_adx4_out3: endpoint {
							remote-endpoint = <&adx4_out3>;
						};
					};

					port@68 {
						reg = <0x68>;

						xbar_adx4_out4: endpoint {
							remote-endpoint = <&adx4_out4>;
						};
					};

					xbar_adx5_in_port: port@69 {
						reg = <0x69>;

						xbar_adx5_in: endpoint {
							remote-endpoint = <&adx5_in>;
						};
					};

					port@6a {
						reg = <0x6a>;

						xbar_adx5_out1: endpoint {
							remote-endpoint = <&adx5_out1>;
						};
					};

					port@6b {
						reg = <0x6b>;

						xbar_adx5_out2: endpoint {
							remote-endpoint = <&adx5_out2>;
						};
					};

					port@6c {
						reg = <0x6c>;

						xbar_adx5_out3: endpoint {
							remote-endpoint = <&adx5_out3>;
						};
					};

					port@6d {
						reg = <0x6d>;

						xbar_adx5_out4: endpoint {
							remote-endpoint = <&adx5_out4>;
						};
					};

					xbar_adx6_in_port: port@6e {
						reg = <0x6e>;

						xbar_adx6_in: endpoint {
							remote-endpoint = <&adx6_in>;
						};
					};

					port@6f {
						reg = <0x6f>;

						xbar_adx6_out1: endpoint {
							remote-endpoint = <&adx6_out1>;
						};
					};

					port@70 {
						reg = <0x70>;

						xbar_adx6_out2: endpoint {
							remote-endpoint = <&adx6_out2>;
						};
					};

					port@71 {
						reg = <0x71>;

						xbar_adx6_out3: endpoint {
							remote-endpoint = <&adx6_out3>;
						};
					};

					port@72 {
						reg = <0x72>;

						xbar_adx6_out4: endpoint {
							remote-endpoint = <&adx6_out4>;
						};
					};

					xbar_mix_in1_port: port@73 {
						reg = <0x73>;

						xbar_mix_in1: endpoint {
							remote-endpoint = <&mix_in1>;
						};
					};

					xbar_mix_in2_port: port@74 {
						reg = <0x74>;

						xbar_mix_in2: endpoint {
							remote-endpoint = <&mix_in2>;
						};
					};

					xbar_mix_in3_port: port@75 {
						reg = <0x75>;

						xbar_mix_in3: endpoint {
							remote-endpoint = <&mix_in3>;
						};
					};

					xbar_mix_in4_port: port@76 {
						reg = <0x76>;

						xbar_mix_in4: endpoint {
							remote-endpoint = <&mix_in4>;
						};
					};

					xbar_mix_in5_port: port@77 {
						reg = <0x77>;

						xbar_mix_in5: endpoint {
							remote-endpoint = <&mix_in5>;
						};
					};

					xbar_mix_in6_port: port@78 {
						reg = <0x78>;

						xbar_mix_in6: endpoint {
							remote-endpoint = <&mix_in6>;
						};
					};

					xbar_mix_in7_port: port@79 {
						reg = <0x79>;

						xbar_mix_in7: endpoint {
							remote-endpoint = <&mix_in7>;
						};
					};

					xbar_mix_in8_port: port@7a {
						reg = <0x7a>;

						xbar_mix_in8: endpoint {
							remote-endpoint = <&mix_in8>;
						};
					};

					xbar_mix_in9_port: port@7b {
						reg = <0x7b>;

						xbar_mix_in9: endpoint {
							remote-endpoint = <&mix_in9>;
						};
					};

					xbar_mix_in10_port: port@7c {
						reg = <0x7c>;

						xbar_mix_in10: endpoint {
							remote-endpoint = <&mix_in10>;
						};
					};

					port@7d {
						reg = <0x7d>;

						xbar_mix_out1: endpoint {
							remote-endpoint = <&mix_out1>;
						};
					};

					port@7e {
						reg = <0x7e>;

						xbar_mix_out2: endpoint {
							remote-endpoint = <&mix_out2>;
						};
					};

					port@7f {
						reg = <0x7f>;

						xbar_mix_out3: endpoint {
							remote-endpoint = <&mix_out3>;
						};
					};

					port@80 {
						reg = <0x80>;

						xbar_mix_out4: endpoint {
							remote-endpoint = <&mix_out4>;
						};
					};

					port@81 {
						reg = <0x81>;

						xbar_mix_out5: endpoint {
							remote-endpoint = <&mix_out5>;
						};
					};

					xbar_asrc_in1_port: port@82 {
						reg = <0x82>;

						xbar_asrc_in1_ep: endpoint {
							remote-endpoint = <&asrc_in1_ep>;
						};
					};

					port@83 {
						reg = <0x83>;

						xbar_asrc_out1_ep: endpoint {
							remote-endpoint = <&asrc_out1_ep>;
						};
					};

					xbar_asrc_in2_port: port@84 {
						reg = <0x84>;

						xbar_asrc_in2_ep: endpoint {
							remote-endpoint = <&asrc_in2_ep>;
						};
					};

					port@85 {
						reg = <0x85>;

						xbar_asrc_out2_ep: endpoint {
							remote-endpoint = <&asrc_out2_ep>;
						};
					};

					xbar_asrc_in3_port: port@86 {
						reg = <0x86>;

						xbar_asrc_in3_ep: endpoint {
							remote-endpoint = <&asrc_in3_ep>;
						};
					};

					port@87 {
						reg = <0x87>;

						xbar_asrc_out3_ep: endpoint {
							remote-endpoint = <&asrc_out3_ep>;
						};
					};

					xbar_asrc_in4_port: port@88 {
						reg = <0x88>;

						xbar_asrc_in4_ep: endpoint {
							remote-endpoint = <&asrc_in4_ep>;
						};
					};

					port@89 {
						reg = <0x89>;

						xbar_asrc_out4_ep: endpoint {
							remote-endpoint = <&asrc_out4_ep>;
						};
					};

					xbar_asrc_in5_port: port@8a {
						reg = <0x8a>;

						xbar_asrc_in5_ep: endpoint {
							remote-endpoint = <&asrc_in5_ep>;
						};
					};

					port@8b {
						reg = <0x8b>;

						xbar_asrc_out5_ep: endpoint {
							remote-endpoint = <&asrc_out5_ep>;
						};
					};

					xbar_asrc_in6_port: port@8c {
						reg = <0x8c>;

						xbar_asrc_in6_ep: endpoint {
							remote-endpoint = <&asrc_in6_ep>;
						};
					};

					port@8d {
						reg = <0x8d>;

						xbar_asrc_out6_ep: endpoint {
							remote-endpoint = <&asrc_out6_ep>;
						};
					};

					xbar_asrc_in7_port: port@8e {
						reg = <0x8e>;

						xbar_asrc_in7_ep: endpoint {
							remote-endpoint = <&asrc_in7_ep>;
						};
					};

					xbar_ope1_in_port: port@8f {
						reg = <0x8f>;

						xbar_ope1_in_ep: endpoint {
							remote-endpoint = <&ope1_cif_in_ep>;
						};
					};

					port@90 {
						reg = <0x90>;

						xbar_ope1_out_ep: endpoint {
							remote-endpoint = <&ope1_cif_out_ep>;
						};
					};
				};
			};

			agic_page0: interrupt-controller@9960000 {
				compatible = "nvidia,tegra264-agic",
						"nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x9961000 0x0 0x1000>,
					<0x0 0x9962000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x230
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};

			agic_page1: interrupt-controller@9970000 {
				compatible = "nvidia,tegra264-agic",
					   "nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x9971000 0x0 0x1000>,
					<0x0 0x9972000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x231
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};

			agic_page2: interrupt-controller@9980000 {
				compatible = "nvidia,tegra264-agic",
						"nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x9981000 0x0 0x1000>,
					<0x0 0x9982000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x232
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};

			agic_page3: interrupt-controller@9990000 {
				compatible = "nvidia,tegra264-agic",
						"nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x9991000 0x0 0x1000>,
					<0x0 0x9992000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x233
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};

			agic_page4: interrupt-controller@99a0000 {
				compatible = "nvidia,tegra264-agic",
						"nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x99a1000 0x0 0x1000>,
					<0x0 0x99a2000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x234
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};

			agic_page5: interrupt-controller@99b0000 {
				compatible = "nvidia,tegra264-agic",
						"nvidia,tegra210-agic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x0 0x99b1000 0x0 0x1000>,
					<0x0 0x99b2000 0x0 0x1000>;
				interrupts = <GIC_SPI 0x235
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				clocks = <&bpmp TEGRA264_CLK_ADSP>;
				clock-names = "clk";
				status = "disabled";
			};
		};

		gpcdma: dma-controller@8400000 {
			compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
			reg = <0x0 0x08400000 0x0 0x210000>;
			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			iommus = <&smmu1 0x00000800>;
			dma-coherent;
			dma-channel-mask = <0xfffffffe>;
			status = "disabled";
		};

		hsp_top: hsp@8800000 {
			compatible = "nvidia,tegra264-hsp";
			reg = <0x0 0x08800000 0x0 0xd0000>;
			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
					  "shared3", "shared4", "shared5", "shared6",
					  "shared7";
			#mbox-cells = <2>;
		};

		rtc: rtc@c2c0000 {
			compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
			reg = <0x0 0x0c2c0000 0x0 0x10000>;
			interrupt-parent = <&pmc>;
			interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA264_CLK_CLK_S>;
			clock-names = "rtc";
			status = "disabled";
		};

		serial@c4e0000 {
			compatible = "nvidia,tegra264-utc";
			reg = <0x0 0x0c4e0000 0x0 0x8000>,
			      <0x0 0x0c4e8000 0x0 0x8000>;
			reg-names = "tx", "rx";
			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
			rx-threshold = <4>;
			tx-threshold = <4>;
			status = "disabled";
		};

		serial@c5a0000 {
			compatible = "nvidia,tegra264-utc";
			reg = <0x0 0x0c5a0000 0x0 0x8000>,
			      <0x0 0x0c5a8000 0x0 0x8000>;
			reg-names = "tx", "rx";
			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
			rx-threshold = <4>;
			tx-threshold = <4>;
			status = "disabled";
		};

		uart0: serial@c5f0000 {
			compatible = "arm,sbsa-uart";
			reg = <0x0 0x0c5f0000 0x0 0x10000>;
			interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		i2c2: i2c@c600000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x0 0x0c600000 0x0 0x10000>;
			interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
				 <&bpmp TEGRA264_CLK_PLLAON>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
			resets = <&bpmp TEGRA264_RESET_I2C2>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c3: i2c@c610000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x0 0x0c610000 0x0 0x10000>;
			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
				 <&bpmp TEGRA264_CLK_PLLAON>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
			resets = <&bpmp TEGRA264_RESET_I2C3>;
			reset-names = "i2c";
			status = "disabled";
		};

		pmc: pmc@c800000 {
			compatible = "nvidia,tegra264-pmc";
			reg = <0x0 0x0c800000 0x0 0x100000>,
			      <0x0 0x0c990000 0x0 0x10000>,
			      <0x0 0x0ca00000 0x0 0x10000>,
			      <0x0 0x0c980000 0x0 0x10000>,
			      <0x0 0x0c9c0000 0x0 0x40000>;
			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
			#interrupt-cells = <2>;
			interrupt-controller;
		};
	};

	/* TOP_MMIO */
	bus@8100000000 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */
			 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
			 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */

		smmu1: iommu@5000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x5000000 0x0 0x200000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		smmu2: iommu@6000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x6000000 0x0 0x200000>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		mc: memory-controller@8020000 {
			compatible = "nvidia,tegra264-mc";
			reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */
			      <0x00 0x8040000 0x0 0x20000>, /* MC  0 */
			      <0x00 0x8060000 0x0 0x20000>, /* MC  1 */
			      <0x00 0x8080000 0x0 0x20000>, /* MC  2 */
			      <0x00 0x80a0000 0x0 0x20000>, /* MC  3 */
			      <0x00 0x80c0000 0x0 0x20000>, /* MC  4 */
			      <0x00 0x80e0000 0x0 0x20000>, /* MC  5 */
			      <0x00 0x8100000 0x0 0x20000>, /* MC  6 */
			      <0x00 0x8120000 0x0 0x20000>, /* MC  7 */
			      <0x00 0x8140000 0x0 0x20000>, /* MC  8 */
			      <0x00 0x8160000 0x0 0x20000>, /* MC  9 */
			      <0x00 0x8180000 0x0 0x20000>, /* MC 10 */
			      <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */
			      <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */
			      <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */
			      <0x00 0x8200000 0x0 0x20000>, /* MC 14 */
			      <0x00 0x8220000 0x0 0x20000>; /* MC 15 */
			reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",
				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9",
				    "ch10", "ch11", "ch12", "ch13", "ch14",
				    "ch15";
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			#interconnect-cells = <1>;

			#address-cells = <2>;
			#size-cells = <2>;

			/* limit the DMA range for memory clients to [39:0] */
			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;

			emc: external-memory-controller@8800000 {
				compatible = "nvidia,tegra264-emc";
				reg = <0x00 0x8800000 0x0 0x20000>,
				      <0x00 0x8890000 0x0 0x20000>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA264_CLK_EMC>;
				clock-names = "emc";

				#interconnect-cells = <0>;
				nvidia,bpmp = <&bpmp>;
			};
		};

		smmu0: iommu@a000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0xa000000 0x0 0x200000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		smmu4: iommu@b000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0xb000000 0x0 0x200000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		i2c14: i2c@c410000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c410000 0x0 0x10000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C14>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c15: i2c@c420000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c420000 0x0 0x10000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C15>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c16: i2c@c430000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c430000 0x0 0x10000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C16>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c0: i2c@c630000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c630000 0x0 0x10000>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C0>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c1: i2c@c640000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c640000 0x0 0x10000>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C1>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c4: i2c@c650000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c650000 0x0 0x10000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C4>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c6: i2c@c670000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c670000 0x0 0x10000>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C6>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c7: i2c@c680000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c680000 0x0 0x10000>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C7>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c8: i2c@c690000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c690000 0x0 0x10000>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C8>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c9: i2c@c6a0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C9>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c10: i2c@c6b0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6b0000 0x0 0x10000>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C10>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c11: i2c@c6c0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6c0000 0x0 0x10000>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C11>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c12: i2c@c6d0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6d0000 0x0 0x10000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C12>;
			reset-names = "i2c";
			status = "disabled";
		};

		gic: interrupt-controller@46000000 {
			compatible = "arm,gic-v3";
			reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */
			      <0x00 0x46080000 0x0 0x400000>; /* GICR */
			interrupt-parent = <&gic>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

			redistributor-stride = <0x0 0x40000>;
			#redistributor-regions = <1>;
			#interrupt-cells = <3>;
			interrupt-controller;

			#address-cells = <2>;
			#size-cells = <2>;

			ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>;

			its: msi-controller@40000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x40000 0x0 0x40000>;
				#msi-cells = <1>;
				msi-controller;
			};
		};
	};

	/* DISP_USB MMIO */
	bus@8800000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;

		smmu3: iommu@6000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x6000000 0x0 0x200000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		hda@90b0000 {
			compatible = "nvidia,tegra264-hda";
			reg = <0x0 0x90b0000 0x0 0x10000>;
			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>;
			clock-names = "hda";
			resets = <&bpmp TEGRA264_RESET_HDA>,
				 <&bpmp TEGRA264_RESET_HDACODEC>;
			reset-names = "hda", "hda2codec_2x";
			interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>,
					<&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>;
			interconnect-names = "dma-mem", "write";
			iommus = <&smmu3 TEGRA264_SID_HDA>;
			status = "disabled";
		};
	};

	/* UPHY MMIO */
	bus@a800000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
			 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,armv8";
			device_type = "cpu";
			reg = <0x00000>;
			status = "okay";

			enable-method = "psci";

			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
		};

		cpu1: cpu@1 {
			compatible = "arm,armv8";
			device_type = "cpu";
			reg = <0x10000>;
			status = "okay";

			enable-method = "psci";

			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
		};
	};

	bpmp: bpmp {
		compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
		mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
				   TEGRA_HSP_DB_MASTER_BPMP>;
		memory-region = <&shmem_bpmp>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;

		i2c {
			compatible = "nvidia,tegra186-bpmp-i2c";
			nvidia,bpmp-bus-id = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		thermal {
			compatible = "nvidia,tegra186-bpmp-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};

	psci {
		compatible = "arm,psci-1.0";
		status = "okay";
		method = "smc";
	};

	sound {
		compatible = "nvidia,tegra264-audio-graph-card";

		clocks = <&bpmp TEGRA264_CLK_PLLA1>,
				<&bpmp TEGRA264_CLK_PLLA1_OUT1>;
		clock-names = "pll_a", "plla_out0";
		assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>,
			<&bpmp TEGRA264_CLK_PLLA1_OUT1>,
			<&bpmp TEGRA264_CLK_AUD_MCLK>;
		assigned-clock-parents = <0>,
			<&bpmp TEGRA264_CLK_PLLA1>,
			<&bpmp TEGRA264_CLK_PLLA1_OUT1>;

		status = "disabled";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};
};