// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ5424 device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&intc>;

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		xo_board: xo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;

				l3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x100>;
			next-level-cache = <&l2_100>;

			l2_100: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x200>;
			next-level-cache = <&l2_200>;

			l2_200: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x300>;
			next-level-cache = <&l2_300>;

			l2_300: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq5424", "qcom,scm";
			qcom,dload-mode = <&tcsr 0x25100>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu-dsu {
		compatible = "arm,dsu-pmu";
		interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		tz@8a600000 {
			reg = <0x0 0x8a600000 0x0 0x200000>;
			no-map;
		};

		smem@8a800000 {
			compatible = "qcom,smem";
			reg = <0x0 0x8a800000 0x0 0x32000>;
			no-map;

			hwlocks = <&tcsr_mutex 3>;
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;

		rng: rng@4c3000 {
			compatible = "qcom,ipq5424-trng", "qcom,trng";
			reg = <0 0x004c3000 0 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		system-cache-controller@800000 {
			compatible = "qcom,ipq5424-llcc";
			reg = <0 0x00800000 0 0x200000>;
			reg-names = "llcc0_base";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq5424-tlmm";
			reg = <0 0x01000000 0 0x300000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 50>;
			interrupt-controller;
			#interrupt-cells = <2>;

			uart1_pins: uart1-state {
				pins = "gpio43", "gpio44";
				function = "uart1";
				drive-strength = <8>;
				bias-pull-up;
			};
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,ipq5424-gcc";
			reg = <0 0x01800000 0 0x40000>;
			clocks = <&xo_board>,
				 <&sleep_clk>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#interconnect-cells = <1>;
		};

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0 0x01905000 0 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-ipq5424", "syscon";
			reg = <0 0x01937000 0 0x2a000>;
		};

		qupv3: geniqup@1ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x01ac0000 0 0x2000>;
			ranges;
			clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
				 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
			clock-names = "m-ahb", "s-ahb";
			#address-cells = <2>;
			#size-cells = <2>;

			uart1: serial@1a84000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x01a84000 0 0x4000>;
				clocks = <&gcc GCC_QUPV3_UART1_CLK>;
				clock-names = "se";
				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
			};

			spi0: spi@1a90000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x01a90000 0 0x4000>;
				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
				clock-names = "se";
				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi1: spi@1a94000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x01a94000 0 0x4000>;
				clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
				clock-names = "se";
				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		sdhc: mmc@7804000 {
			compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
			reg-names = "hc", "cqhci";

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";

			status = "disabled";
		};

		intc: interrupt-controller@f200000 {
			compatible = "arm,gic-v3";
			reg = <0 0xf200000 0 0x10000>, /* GICD */
			      <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
			#interrupt-cells = <0x3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			mbi-ranges = <672 128>;
			msi-controller;
		};

		watchdog@f410000 {
			compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
			reg = <0 0x0f410000 0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sleep_clk>;
		};

		qusb_phy_1: phy@71000 {
			compatible = "qcom,ipq5424-qusb2-phy";
			reg = <0 0x00071000 0 0x180>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
				<&xo_board>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
			status = "disabled";
		};

		usb2: usb2@1e00000 {
			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
			reg = <0 0x01ef8800 0 0x400>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_USB1_MASTER_CLK>,
				 <&gcc GCC_USB1_SLEEP_CLK>,
				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
				 <&gcc GCC_CNOC_USB_CLK>;

			clock-names = "core",
				      "sleep",
				      "mock_utmi",
				      "iface",
				      "cfg_noc";

			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
			assigned-clock-rates = <200000000>,
					       <24000000>;

			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pwr_event",
					  "qusb2_phy",
					  "dm_hs_phy_irq",
					  "dp_hs_phy_irq";

			resets = <&gcc GCC_USB1_BCR>;
			qcom,select-utmi-as-pipe-clk;
			status = "disabled";

			dwc_1: usb@1e00000 {
				compatible = "snps,dwc3";
				reg = <0 0x01e00000 0 0xe000>;
				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
				clock-names = "ref";
				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&qusb_phy_1>;
				phy-names = "usb2-phy";
				tx-fifo-resize;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
			};
		};

		qusb_phy_0: phy@7b000 {
			compatible = "qcom,ipq5424-qusb2-phy";
			reg = <0 0x0007b000 0 0x180>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				<&xo_board>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
			status = "disabled";
		};

		ssphy_0: phy@7d000 {
			compatible = "qcom,ipq5424-qmp-usb3-phy";
			reg = <0 0x0007d000 0 0xa00>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB0_AUX_CLK>,
				 <&xo_board>,
				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				 <&gcc GCC_USB0_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "cfg_ahb",
				      "pipe";

			resets = <&gcc GCC_USB0_PHY_BCR>,
				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
			reset-names = "phy",
				      "phy_phy";

			#clock-cells = <0>;
			clock-output-names = "usb0_pipe_clk";

			status = "disabled";
		};

		usb3: usb3@8a00000 {
			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
			reg = <0 0x08af8800 0 0x400>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_USB0_MASTER_CLK>,
				 <&gcc GCC_USB0_SLEEP_CLK>,
				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				 <&gcc GCC_CNOC_USB_CLK>;

			clock-names = "core",
				      "sleep",
				      "mock_utmi",
				      "iface",
				      "cfg_noc";

			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
			assigned-clock-rates = <200000000>,
					       <24000000>;

			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pwr_event",
					  "qusb2_phy",
					  "dm_hs_phy_irq",
					  "dp_hs_phy_irq";

			resets = <&gcc GCC_USB_BCR>;
			status = "disabled";

			dwc_0: usb@8a00000 {
				compatible = "snps,dwc3";
				reg = <0 0x08a00000 0 0xcd00>;
				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
				clock-names = "ref";
				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&qusb_phy_0>, <&ssphy_0>;
				phy-names = "usb2-phy", "usb3-phy";
				tx-fifo-resize;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				snps,dis-u1-entry-quirk;
				snps,dis-u2-entry-quirk;
			};
		};

		timer@f420000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0 0xf420000 0 0x1000>;
			ranges = <0 0 0 0x10000000>;
			#address-cells = <1>;
			#size-cells = <1>;

			frame@f421000 {
				reg = <0xf421000 0x1000>,
				      <0xf422000 0x1000>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <0>;
			};

			frame@f423000 {
				reg = <0xf423000 0x1000>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <1>;
				status = "disabled";
			};

			frame@f425000 {
				reg = <0xf425000 0x1000>,
				      <0xf426000 0x1000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <2>;
				status = "disabled";
			};

			frame@f427000 {
				reg = <0xf427000 0x1000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <3>;
				status = "disabled";
			};

			frame@f429000 {
				reg = <0xf429000 0x1000>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <4>;
				status = "disabled";
			};

			frame@f42b000 {
				reg = <0xf42b000 0x1000>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <5>;
				status = "disabled";
			};

			frame@f42d000 {
				reg = <0xf42d000 0x1000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <6>;
				status = "disabled";
			};
		};

	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
	};
};