// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		xo_board_clk: xo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a78c";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd0>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <472>;

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78c";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			power-domains = <&cpu_pd1>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <472>;

			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a78c";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			power-domains = <&cpu_pd2>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <507>;

			l2_2: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a78c";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&l2_3>;
			power-domains = <&cpu_pd3>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <507>;

			l2_3: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_0>;
			};
		};

		cpu4: cpu@10000 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			next-level-cache = <&l2_4>;
			power-domains = <&cpu_pd4>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;

			l2_4: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_1>;
			};
		};

		cpu5: cpu@10100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			next-level-cache = <&l2_5>;
			power-domains = <&cpu_pd5>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;

			l2_5: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_1>;
			};
		};

		cpu6: cpu@10200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x10200>;
			enable-method = "psci";
			next-level-cache = <&l2_6>;
			power-domains = <&cpu_pd6>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;

			l2_6: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_1>;
			};
		};

		cpu7: cpu@10300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x10300>;
			enable-method = "psci";
			next-level-cache = <&l2_7>;
			power-domains = <&cpu_pd7>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;

			l2_7: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		l3_0: l3-cache-0 {
			compatible = "cache";
			cache-level = <3>;
			cache-unified;
		};

		l3_1: l3-cache-1 {
			compatible = "cache";
			cache-level = <3>;
			cache-unified;
		};

		idle-states {
			entry-method = "psci";

			little_cpu_sleep_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "silver-power-collapse";
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <449>;
				exit-latency-us = <801>;
				min-residency-us = <1574>;
				local-timer-stop;
			};

			little_cpu_sleep_1: cpu-sleep-0-1 {
				compatible = "arm,idle-state";
				idle-state-name = "silver-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <602>;
				exit-latency-us = <961>;
				min-residency-us = <4288>;
				local-timer-stop;
			};

			big_cpu_sleep_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "gold-power-collapse";
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <549>;
				exit-latency-us = <901>;
				min-residency-us = <1774>;
				local-timer-stop;
			};

			big_cpu_sleep_1: cpu-sleep-1-1 {
				compatible = "arm,idle-state";
				idle-state-name = "gold-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <702>;
				exit-latency-us = <1061>;
				min-residency-us = <4488>;
				local-timer-stop;
			};
		};

		domain-idle-states {
			silver_cluster_sleep: cluster-sleep-0 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x41000044>;
				entry-latency-us = <2552>;
				exit-latency-us = <2848>;
				min-residency-us = <5908>;
			};

			gold_cluster_sleep: cluster-sleep-1 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x41000044>;
				entry-latency-us = <2752>;
				exit-latency-us = <3048>;
				min-residency-us = <6118>;
			};

			system_sleep: domain-sleep {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x42000144>;
				entry-latency-us = <3263>;
				exit-latency-us = <6562>;
				min-residency-us = <9987>;
			};
		};
	};

	dummy_eud: dummy-sink {
		compatible = "arm,coresight-dummy-sink";

		in-ports {
			port {
				eud_in: endpoint {
					remote-endpoint = <&swao_rep_out1>;
				};
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-qcs8300", "qcom,scm";
			qcom,dload-mode = <&tcsr 0x13000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	clk_virt: interconnect-0 {
		compatible = "qcom,qcs8300-clk-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect-1 {
		compatible = "qcom,qcs8300-mc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu-a78 {
		compatible = "arm,cortex-a78-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		cpu_pd0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cpu_pd1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cpu_pd2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cpu_pd3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cpu_pd4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cluster_pd0: power-domain-cluster0 {
			#power-domain-cells = <0>;
			power-domains = <&system_pd>;
			domain-idle-states = <&gold_cluster_sleep>;
		};

		cluster_pd1: power-domain-cluster1 {
			#power-domain-cells = <0>;
			power-domains = <&system_pd>;
			domain-idle-states = <&silver_cluster_sleep>;
		};

		system_pd: power-domain-system {
			#power-domain-cells = <0>;
			domain-idle-states = <&system_sleep>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		aop_image_mem: aop-image-region@90800000 {
			reg = <0x0 0x90800000 0x0 0x60000>;
			no-map;
		};

		aop_cmd_db_mem: aop-cmd-db-region@90860000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x90860000 0x0 0x20000>;
			no-map;
		};

		smem_mem: smem@90900000 {
			compatible = "qcom,smem";
			reg = <0x0 0x90900000 0x0 0x200000>;
			no-map;
			hwlocks = <&tcsr_mutex 3>;
		};

		lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
			reg = <0x0 0x93b00000 0x0 0xf00000>;
			no-map;
		};

		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
			reg = <0x0 0x94a00000 0x0 0x800000>;
			no-map;
		};

		camera_mem: camera-region@95200000 {
			reg = <0x0 0x95200000 0x0 0x500000>;
			no-map;
		};

		adsp_mem: adsp-region@95c00000 {
			no-map;
			reg = <0x0 0x95c00000 0x0 0x1e00000>;
		};

		q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
			reg = <0x0 0x97a00000 0x0 0x80000>;
			no-map;
		};

		q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
			reg = <0x0 0x97a80000 0x0 0x80000>;
			no-map;
		};

		gpdsp_mem: gpdsp-region@97b00000 {
			reg = <0x0 0x97b00000 0x0 0x1e00000>;
			no-map;
		};

		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
			reg = <0x0 0x99900000 0x0 0x80000>;
			no-map;
		};

		cdsp_mem: cdsp-region@99980000 {
			reg = <0x0 0x99980000 0x0 0x1e00000>;
			no-map;
		};

		gpu_microcode_mem: gpu-microcode-region@9b780000 {
			reg = <0x0 0x9b780000 0x0 0x2000>;
			no-map;
		};

		cvp_mem: cvp-region@9b782000 {
			reg = <0x0 0x9b782000 0x0 0x700000>;
			no-map;
		};

		video_mem: video-region@9be82000 {
			reg = <0x0 0x9be82000 0x0 0x700000>;
			no-map;
		};
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_LPASS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,smem = <443>, <429>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		smp2p_adsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_adsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_CDSP
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,smem = <94>, <432>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		smp2p_cdsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_cdsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};
	};

	smp2p-gpdsp {
		compatible = "qcom,smp2p";
		interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_GPDSP0
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,smem = <617>, <616>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <17>;

		smp2p_gpdsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_gpdsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		ranges = <0 0 0 0 0x10 0>;
		#address-cells = <2>;
		#size-cells = <2>;

		gcc: clock-controller@100000 {
			compatible = "qcom,qcs8300-gcc";
			reg = <0x0 0x00100000 0x0 0xc7018>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&sleep_clk>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>;
		};

		ipcc: mailbox@408000 {
			compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
			reg = <0x0 0x408000 0x0 0x1000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#mbox-cells = <2>;
		};

		qfprom: efuse@784000 {
			compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
			reg = <0x0 0x00784000 0x0 0x1200>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		qupv3_id_0: geniqup@9c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x9c0000 0x0 0x2000>;
			ranges;
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			uart7: serial@99c000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0x0 0x0099c000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart7_default>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				status = "disabled";
			};
		};

		rng: rng@10d2000 {
			compatible = "qcom,qcs8300-trng", "qcom,trng";
			reg = <0x0 0x010d2000 0x0 0x1000>;
		};

		config_noc: interconnect@14c0000 {
			compatible = "qcom,qcs8300-config-noc";
			reg = <0x0 0x014c0000 0x0 0x13080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@1680000 {
			compatible = "qcom,qcs8300-system-noc";
			reg = <0x0 0x01680000 0x0 0x15080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre1_noc: interconnect@16c0000 {
			compatible = "qcom,qcs8300-aggre1-noc";
			reg = <0x0 0x016c0000 0x0 0x17080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre2_noc: interconnect@1700000 {
			compatible = "qcom,qcs8300-aggre2-noc";
			reg = <0x0 0x01700000 0x0 0x1a080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		pcie_anoc: interconnect@1760000 {
			compatible = "qcom,qcs8300-pcie-anoc";
			reg = <0x0 0x01760000 0x0 0xc080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		gpdsp_anoc: interconnect@1780000 {
			compatible = "qcom,qcs8300-gpdsp-anoc";
			reg = <0x0 0x01780000 0x0 0xd080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		mmss_noc: interconnect@17a0000 {
			compatible = "qcom,qcs8300-mmss-noc";
			reg = <0x0 0x017a0000 0x0 0x40000>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		ufs_mem_hc: ufs@1d84000 {
			compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
			reg = <0x0 0x01d84000 0x0 0x3000>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufs_mem_phy>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			#reset-cells = <1>;
			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			iommus = <&apps_smmu 0x100 0x0>;
			dma-coherent;

			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "ufs-ddr",
					     "cpu-ufs";

			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_UFS_PHY_AHB_CLK>,
				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
			clock-names = "core_clk",
				      "bus_aggr_clk",
				      "iface_clk",
				      "core_clk_unipro",
				      "ref_clk",
				      "tx_lane0_sync_clk",
				      "rx_lane0_sync_clk",
				      "rx_lane1_sync_clk";
			freq-table-hz = <75000000 300000000>,
					<0 0>,
					<0 0>,
					<75000000 300000000>,
					<0 0>,
					<0 0>,
					<0 0>,
					<0 0>;
			qcom,ice = <&ice>;
			status = "disabled";
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
			reg = <0x0 0x01d87000 0x0 0xe10>;
			/*
			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
			 * enables the CXO clock to eDP *and* UFS PHY.
			 */
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
				 <&gcc GCC_EDP_REF_CLKREF_EN>;
			clock-names = "ref",
				      "ref_aux",
				      "qref";
			power-domains = <&gcc GCC_UFS_PHY_GDSC>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";

			#phy-cells = <0>;
			status = "disabled";
		};

		cryptobam: dma-controller@1dc4000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0x0 0x01dc4000 0x0 0x28000>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <20>;
			qcom,num-ees = <4>;
			iommus = <&apps_smmu 0x480 0x00>,
				 <&apps_smmu 0x481 0x00>;
		};

		crypto: crypto@1dfa000 {
			compatible = "qcom,qcs8300-qce", "qcom,qce";
			reg = <0x0 0x01dfa000 0x0 0x6000>;
			dmas = <&cryptobam 4>, <&cryptobam 5>;
			dma-names = "rx", "tx";
			iommus = <&apps_smmu 0x480 0x00>,
				 <&apps_smmu 0x481 0x00>;
			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "memory";
		};

		ice: crypto@1d88000 {
			compatible = "qcom,qcs8300-inline-crypto-engine",
				     "qcom,inline-crypto-engine";
			reg = <0x0 0x01d88000 0x0 0x18000>;
			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1fc0000 {
			compatible = "qcom,qcs8300-tcsr", "syscon";
			reg = <0x0 0x1fc0000 0x0 0x30000>;
		};

		remoteproc_adsp: remoteproc@3000000 {
			compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
			reg = <0x0 0x3000000 0x0 0x00100>;

			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_LCX>,
					<&rpmhpd RPMHPD_LMX>;
			power-domain-names = "lcx",
					     "lmx";

			memory-region = <&adsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_adsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			remoteproc_adsp_glink: glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_LPASS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "lpass";
				qcom,remote-pid = <2>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "adsp";
					memory-region = <&adsp_rpc_remote_heap_mem>;
					qcom,vmids = <QCOM_SCM_VMID_LPASS
						      QCOM_SCM_VMID_ADSP_HEAP>;
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x2003 0x0>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x2004 0x0>;
						dma-coherent;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x2005 0x0>;
						dma-coherent;
					};
				};
			};
		};

		lpass_ag_noc: interconnect@3c40000 {
			compatible = "qcom,qcs8300-lpass-ag-noc";
			reg = <0x0 0x03c40000 0x0 0x17200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		stm@4002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x0 0x04002000 0x0 0x1000>,
			      <0x0 0x16280000 0x0 0x180000>;
			reg-names = "stm-base",
				    "stm-stimulus-base";

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					stm_out: endpoint {
						remote-endpoint = <&funnel0_in7>;
					};
				};
			};
		};

		tpda@4004000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04004000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					reg = <1>;

					qdss_tpda_in1: endpoint {
						remote-endpoint = <&qdss_tpdm1_out>;
					};
				};
			};

			out-ports {
				port {
					qdss_tpda_out: endpoint {
						remote-endpoint = <&funnel0_in6>;
					};
				};
			};
		};

		tpdm@400f000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x0400f000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					qdss_tpdm1_out: endpoint {
						remote-endpoint = <&qdss_tpda_in1>;
					};
				};
			};
		};

		funnel@4041000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04041000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					funnel0_in6: endpoint {
						remote-endpoint = <&qdss_tpda_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel0_in7: endpoint {
						remote-endpoint = <&stm_out>;
					};
				};
			};

			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint = <&qdss_funnel_in0>;
					};
				};
			};
		};

		funnel@4042000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04042000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@4 {
					reg = <4>;

					funnel1_in4: endpoint {
						remote-endpoint = <&apss_funnel1_out>;
					};
				};

				port@5 {
					reg = <5>;

					funnel1_in5: endpoint {
						remote-endpoint = <&dlct0_funnel_out>;
					};
				};

				port@6 {
					reg = <6>;

					funnel1_in6: endpoint {
						remote-endpoint = <&dlmm_funnel_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel1_in7: endpoint {
						remote-endpoint = <&dlst_ch_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&qdss_funnel_in1>;
					};
				};
			};
		};

		funnel@4045000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04045000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					qdss_funnel_in0: endpoint {
						remote-endpoint = <&funnel0_out>;
					};
				};

				port@1 {
					reg = <1>;

					qdss_funnel_in1: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					qdss_funnel_out: endpoint {
						remote-endpoint = <&aoss_funnel_in7>;
					};
				};
			};
		};

		tpdm@4841000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04841000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					prng_tpdm_out: endpoint {
						remote-endpoint = <&dlct0_tpda_in19>;
					};
				};
			};
		};

		tpdm@4850000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04850000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;
			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					pimem_tpdm_out: endpoint {
						remote-endpoint = <&dlct0_tpda_in25>;
					};
				};
			};
		};

		tpdm@4860000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04860000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					dlst_ch_tpdm0_out: endpoint {
						remote-endpoint = <&dlst_ch_tpda_in8>;
					};
				};
			};
		};

		tpda@4864000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04864000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@8 {
					reg = <8>;

					dlst_ch_tpda_in8: endpoint {
						remote-endpoint = <&dlst_ch_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_ch_tpda_out: endpoint {
						remote-endpoint = <&dlst_ch_funnel_in0>;
					};
				};
			};
		};

		funnel@4865000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04865000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					dlst_ch_funnel_in0: endpoint {
						remote-endpoint = <&dlst_ch_tpda_out>;
					};
				};

				port@4 {
					reg = <4>;

					dlst_ch_funnel_in4: endpoint {
						remote-endpoint = <&dlst_funnel_out>;
					};
				};

				port@6 {
					reg = <6>;

					dlst_ch_funnel_in6: endpoint {
						remote-endpoint = <&gdsp_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_ch_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in7>;
					};
				};
			};
		};

		tpdm@4980000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04980000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					turing2_tpdm_out: endpoint {
						remote-endpoint = <&turing2_funnel_in0>;
					};
				};
			};
		};

		funnel@4983000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04983000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					turing2_funnel_in0: endpoint {
						remote-endpoint = <&turing2_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					turing2_funnel_out0: endpoint {
						remote-endpoint = <&gdsp_tpda_in5>;
					};
				};
			};
		};

		tpdm@4ac0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04ac0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					dlmm_tpdm0_out: endpoint {
						remote-endpoint = <&dlmm_tpda_in27>;
					};
				};
			};
		};

		tpda@4ac4000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04ac4000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1b {
					reg = <27>;

					dlmm_tpda_in27: endpoint {
						remote-endpoint = <&dlmm_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					dlmm_tpda_out: endpoint {
						remote-endpoint = <&dlmm_funnel_in0>;
					};
				};
			};
		};

		funnel@4ac5000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04ac5000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					dlmm_funnel_in0: endpoint {
						remote-endpoint = <&dlmm_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					dlmm_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in6>;
					};
				};
			};
		};

		tpdm@4ad0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04ad0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					dlct0_tpdm0_out: endpoint {
						remote-endpoint = <&dlct0_tpda_in26>;
					};
				};
			};
		};

		tpda@4ad3000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04ad3000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@13 {
					reg = <19>;

					dlct0_tpda_in19: endpoint {
						remote-endpoint = <&prng_tpdm_out>;
					};
				};

				port@19 {
					reg = <25>;

					dlct0_tpda_in25: endpoint {
						remote-endpoint = <&pimem_tpdm_out>;
					};
				};

				port@1a {
					reg = <26>;

					dlct0_tpda_in26: endpoint {
						remote-endpoint = <&dlct0_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					dlct0_tpda_out: endpoint {
						remote-endpoint = <&dlct0_funnel_in0>;
					};
				};
			};
		};

		funnel@4ad4000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04ad4000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					dlct0_funnel_in0: endpoint {
						remote-endpoint = <&dlct0_tpda_out>;
					};
				};

				port@4 {
					reg = <4>;

					dlct0_funnel_in4: endpoint {
						remote-endpoint = <&ddr_funnel5_out>;
					};
				};
			};

			out-ports {
				port {
					dlct0_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in5>;
					};
				};
			};
		};

		funnel@4b04000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04b04000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					aoss_funnel_in6: endpoint {
						remote-endpoint = <&aoss_tpda_out>;
					};
				};

				port@7 {
					reg = <7>;

					aoss_funnel_in7: endpoint {
						remote-endpoint = <&qdss_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					aoss_funnel_out: endpoint {
						remote-endpoint = <&etf0_in>;
					};
				};
			};
		};

		tmc_etf: tmc@4b05000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x0 0x04b05000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etf0_in: endpoint {
						remote-endpoint = <&aoss_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					etf0_out: endpoint {
						remote-endpoint = <&swao_rep_in>;
					};
				};
			};
		};

		replicator@4b06000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x0 0x04b06000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					swao_rep_in: endpoint {
						remote-endpoint = <&etf0_out>;
					};
				};
			};

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					reg = <1>;

					swao_rep_out1: endpoint {
						remote-endpoint = <&eud_in>;
					};
				};
			};
		};

		tpda@4b08000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04b08000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					aoss_tpda_in0: endpoint {
						remote-endpoint = <&aoss_tpdm0_out>;
					};
				};

				port@1 {
					reg = <1>;

					aoss_tpda_in1: endpoint {
						remote-endpoint = <&aoss_tpdm1_out>;
					};
				};

				port@2 {
					reg = <2>;

					aoss_tpda_in2: endpoint {
						remote-endpoint = <&aoss_tpdm2_out>;
					};
				};

				port@3 {
					reg = <3>;

					aoss_tpda_in3: endpoint {
						remote-endpoint = <&aoss_tpdm3_out>;
					};
				};

				port@4 {
					reg = <4>;

					aoss_tpda_in4: endpoint {
						remote-endpoint = <&aoss_tpdm4_out>;
					};
				};
			};

			out-ports {
				port {
					aoss_tpda_out: endpoint {
						remote-endpoint = <&aoss_funnel_in6>;
					};
				};
			};
		};

		tpdm@4b09000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b09000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm0_out: endpoint {
						remote-endpoint = <&aoss_tpda_in0>;
					};
				};
			};
		};

		tpdm@4b0a000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b0a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm1_out: endpoint {
						remote-endpoint = <&aoss_tpda_in1>;
					};
				};
			};
		};

		tpdm@4b0b000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b0b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm2_out: endpoint {
						remote-endpoint = <&aoss_tpda_in2>;
					};
				};
			};
		};

		tpdm@4b0c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b0c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm3_out: endpoint {
						remote-endpoint = <&aoss_tpda_in3>;
					};
				};
			};
		};

		tpdm@4b0d000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b0d000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm4_out: endpoint {
						remote-endpoint = <&aoss_tpda_in4>;
					};
				};
			};
		};

		cti@4b13000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x04b13000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@4b80000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04b80000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					turing0_tpdm0_out: endpoint {
						remote-endpoint = <&turing0_tpda_in0>;
					};
				};
			};
		};

		tpda@4b86000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04b86000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					turing0_tpda_in0: endpoint {
						remote-endpoint = <&turing0_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					turing0_tpda_out: endpoint {
						remote-endpoint = <&turing0_funnel_in0>;
					};
				};
			};
		};

		funnel@4b87000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04b87000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					turing0_funnel_in0: endpoint {
						remote-endpoint = <&turing0_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					turing0_funnel_out: endpoint {
						remote-endpoint = <&gdsp_funnel_in4>;
					};
				};
			};
		};

		cti@4b8b000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x04b8b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@4c40000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04c40000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					gdsp_tpdm0_out: endpoint {
						remote-endpoint = <&gdsp_tpda_in8>;
					};
				};
			};
		};

		tpda@4c44000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04c44000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@5 {
					reg = <5>;

					gdsp_tpda_in5: endpoint {
						remote-endpoint = <&turing2_funnel_out0>;
					};
				};

				port@8 {
					reg = <8>;

					gdsp_tpda_in8: endpoint {
						remote-endpoint = <&gdsp_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					gdsp_tpda_out: endpoint {
						remote-endpoint = <&gdsp_funnel_in0>;
					};
				};
			};
		};

		funnel@4c45000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04c45000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					gdsp_funnel_in0: endpoint {
						remote-endpoint = <&gdsp_tpda_out>;
					};
				};

				port@4 {
					reg = <4>;

					gdsp_funnel_in4: endpoint {
						remote-endpoint = <&turing0_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					gdsp_funnel_out: endpoint {
						remote-endpoint = <&dlst_ch_funnel_in6>;
					};
				};
			};
		};

		tpdm@4c50000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04c50000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					dlst_tpdm0_out: endpoint {
						remote-endpoint = <&dlst_tpda_in8>;
					};
				};
			};
		};

		tpda@4c54000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04c54000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@8 {
					reg = <8>;

					dlst_tpda_in8: endpoint {
						remote-endpoint = <&dlst_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_tpda_out: endpoint {
						remote-endpoint = <&dlst_funnel_in0>;
					};
				};
			};
		};

		funnel@4c55000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04c55000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					dlst_funnel_in0: endpoint {
						remote-endpoint = <&dlst_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_funnel_out: endpoint {
						remote-endpoint = <&dlst_ch_funnel_in4>;
					};
				};
			};
		};

		tpdm@4e00000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04e00000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					ddr_tpdm3_out: endpoint {
						remote-endpoint = <&ddr_tpda_in4>;
					};
				};
			};
		};

		tpda@4e03000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x04e03000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					ddr_tpda_in0: endpoint {
						remote-endpoint = <&ddr_funnel0_out0>;
					};
				};

				port@1 {
					reg = <1>;

					ddr_tpda_in1: endpoint {
						remote-endpoint = <&ddr_funnel1_out0>;
					};
				};

				port@4 {
					reg = <4>;

					ddr_tpda_in4: endpoint {
						remote-endpoint = <&ddr_tpdm3_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_tpda_out: endpoint {
						remote-endpoint = <&ddr_funnel5_in0>;
					};
				};
			};
		};

		funnel@4e04000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04e04000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					ddr_funnel5_in0: endpoint {
						remote-endpoint = <&ddr_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_funnel5_out: endpoint {
						remote-endpoint = <&dlct0_funnel_in4>;
					};
				};
			};
		};

		tpdm@4e10000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04e10000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					ddr_tpdm0_out: endpoint {
						remote-endpoint = <&ddr_funnel0_in0>;
					};
				};
			};
		};

		funnel@4e12000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04e12000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					ddr_funnel0_in0: endpoint {
						remote-endpoint = <&ddr_tpdm0_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_funnel0_out0: endpoint {
						remote-endpoint = <&ddr_tpda_in0>;
					};
				};
			};
		};

		tpdm@4e20000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x04e20000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					ddr_tpdm1_out: endpoint {
						remote-endpoint = <&ddr_funnel1_in0>;
					};
				};
			};
		};

		funnel@4e22000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x04e22000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					ddr_funnel1_in0: endpoint {
						remote-endpoint = <&ddr_tpdm1_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_funnel1_out0: endpoint {
						remote-endpoint = <&ddr_tpda_in1>;
					};
				};
			};
		};

		etm@6040000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06040000 0x0 0x1000>;
			cpu = <&cpu0>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&apss_funnel0_in0>;
					};
				};
			};
		};

		etm@6140000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06140000 0x0 0x1000>;
			cpu = <&cpu1>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&apss_funnel0_in1>;
					};
				};
			};
		};

		etm@6240000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06240000 0x0 0x1000>;
			cpu = <&cpu2>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&apss_funnel0_in2>;
					};
				};
			};
		};

		etm@6340000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06340000 0x0 0x1000>;
			cpu = <&cpu3>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&apss_funnel0_in3>;
					};
				};
			};
		};

		etm@6440000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06440000 0x0 0x1000>;
			cpu = <&cpu4>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm4_out: endpoint {
						remote-endpoint = <&apss_funnel0_in4>;
					};
				};
			};
		};

		etm@6540000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06540000 0x0 0x1000>;
			cpu = <&cpu5>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm5_out: endpoint {
						remote-endpoint = <&apss_funnel0_in5>;
					};
				};
			};
		};

		etm@6640000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06640000 0x0 0x1000>;
			cpu = <&cpu6>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm6_out: endpoint {
						remote-endpoint = <&apss_funnel0_in6>;
					};
				};
			};
		};

		etm@6740000 {
			compatible = "arm,primecell";
			reg = <0x0 0x06740000 0x0 0x1000>;
			cpu = <&cpu7>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm7_out: endpoint {
						remote-endpoint = <&apss_funnel0_in7>;
					};
				};
			};
		};

		funnel@6800000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06800000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					apss_funnel0_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;

					apss_funnel0_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;

					apss_funnel0_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;

					apss_funnel0_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};

				port@4 {
					reg = <4>;

					apss_funnel0_in4: endpoint {
						remote-endpoint = <&etm4_out>;
					};
				};

				port@5 {
					reg = <5>;

					apss_funnel0_in5: endpoint {
						remote-endpoint = <&etm5_out>;
					};
				};

				port@6 {
					reg = <6>;

					apss_funnel0_in6: endpoint {
						remote-endpoint = <&etm6_out>;
					};
				};

				port@7 {
					reg = <7>;

					apss_funnel0_in7: endpoint {
						remote-endpoint = <&etm7_out>;
					};
				};
			};

			out-ports {
				port {
					apss_funnel0_out: endpoint {
						remote-endpoint = <&apss_funnel1_in0>;
					};
				};
			};
		};

		funnel@6810000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06810000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					apss_funnel1_in0: endpoint {
						remote-endpoint = <&apss_funnel0_out>;
					};
				};

				port@3 {
					reg = <3>;

					apss_funnel1_in3: endpoint {
						remote-endpoint = <&apss_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					apss_funnel1_out: endpoint {
						remote-endpoint = <&funnel1_in4>;
					};
				};
			};
		};

		cti@682b000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0682b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@6860000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06860000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					apss_tpdm3_out: endpoint {
						remote-endpoint = <&apss_tpda_in3>;
					};
				};
			};
		};

		tpdm@6861000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06861000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					apss_tpdm4_out: endpoint {
						remote-endpoint = <&apss_tpda_in4>;
					};
				};
			};
		};

		tpda@6863000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x06863000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					apss_tpda_in0: endpoint {
						remote-endpoint = <&apss_tpdm0_out>;
					};
				};

				port@1 {
					reg = <1>;

					apss_tpda_in1: endpoint {
						remote-endpoint = <&apss_tpdm1_out>;
					};
				};

				port@2 {
					reg = <2>;

					apss_tpda_in2: endpoint {
						remote-endpoint = <&apss_tpdm2_out>;
					};
				};

				port@3 {
					reg = <3>;

					apss_tpda_in3: endpoint {
						remote-endpoint = <&apss_tpdm3_out>;
					};
				};

				port@4 {
					reg = <4>;

					apss_tpda_in4: endpoint {
						remote-endpoint = <&apss_tpdm4_out>;
					};
				};
			};

			out-ports {
				port {
					apss_tpda_out: endpoint {
						remote-endpoint = <&apss_funnel1_in3>;
					};
				};
			};
		};

		tpdm@68a0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x068a0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					apss_tpdm1_out: endpoint {
						remote-endpoint = <&apss_tpda_in1>;
					};
				};
			};
		};

		tpdm@68b0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x068b0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					apss_tpdm0_out: endpoint {
						remote-endpoint = <&apss_tpda_in0>;
					};
				};
			};
		};

		tpdm@68c0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x068c0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					apss_tpdm2_out: endpoint {
						remote-endpoint = <&apss_tpda_in2>;
					};
				};
			};
		};

		cti@68e0000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x068e0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@68f0000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x068f0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6900000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06900000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		usb_1_hsphy: phy@8904000 {
			compatible = "qcom,qcs8300-usb-hs-phy",
				     "qcom,usb-snps-hs-7nm-phy";
			reg = <0x0 0x08904000 0x0 0x400>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";

			resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_2_hsphy: phy@8906000 {
			compatible = "qcom,qcs8300-usb-hs-phy",
				     "qcom,usb-snps-hs-7nm-phy";
			reg = <0x0 0x08906000 0x0 0x400>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";

			resets = <&gcc GCC_USB2_PHY_SEC_BCR>;

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_qmpphy: phy@8907000 {
			compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
			reg = <0x0 0x08907000 0x0 0x2000>;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&gcc GCC_USB_CLKREF_EN>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "pipe";

			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
			reset-names = "phy", "phy_phy";

			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "usb3_prim_phy_pipe_clk_src";

			#phy-cells = <0>;

			status = "disabled";
		};

		serdes0: phy@8909000 {
			compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
			reg = <0x0 0x08909000 0x0 0x00000e10>;
			clocks = <&gcc GCC_SGMI_CLKREF_EN>;
			clock-names = "sgmi_ref";
			#phy-cells = <0>;
			status = "disabled";
		};

		gpucc: clock-controller@3d90000 {
			compatible = "qcom,qcs8300-gpucc";
			reg = <0x0 0x03d90000 0x0 0xa000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
			clock-names = "bi_tcxo",
				      "gcc_gpu_gpll0_clk_src",
				      "gcc_gpu_gpll0_div_clk_src";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		pmu@9091000 {
			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
			reg = <0x0 0x9091000 0x0 0x1000>;

			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&llcc_bwmon_opp_table>;

			llcc_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <762000>;
				};

				opp-1 {
					opp-peak-kBps = <1720000>;
				};

				opp-2 {
					opp-peak-kBps = <2086000>;
				};

				opp-3 {
					opp-peak-kBps = <2601000>;
				};

				opp-4 {
					opp-peak-kBps = <2929000>;
				};

				opp-5 {
					opp-peak-kBps = <5931000>;
				};

				opp-6 {
					opp-peak-kBps = <6515000>;
				};

				opp-7 {
					opp-peak-kBps = <7984000>;
				};

				opp-8 {
					opp-peak-kBps = <10437000>;
				};

				opp-9 {
					opp-peak-kBps = <12195000>;
				};
			};
		};

		pmu@90b5400 {
			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0x0 0x90b5400 0x0 0x600>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;

			cpu_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <9155000>;
				};

				opp-1 {
					opp-peak-kBps = <12298000>;
				};

				opp-2 {
					opp-peak-kBps = <14236000>;
				};

				opp-3 {
					opp-peak-kBps = <16265000>;
				};
			};
		};

		pmu@90b6400 {
			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0x0 0x90b6400 0x0 0x600>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;
		};

		dc_noc: interconnect@90e0000 {
			compatible = "qcom,qcs8300-dc-noc";
			reg = <0x0 0x090e0000 0x0 0x5080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		gem_noc: interconnect@9100000 {
			compatible = "qcom,qcs8300-gem-noc";
			reg = <0x0 0x9100000 0x0 0xf7080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		llcc: system-cache-controller@9200000 {
			compatible = "qcom,qcs8300-llcc";
			reg = <0x0 0x09200000 0x0 0x80000>,
			      <0x0 0x09300000 0x0 0x80000>,
			      <0x0 0x09400000 0x0 0x80000>,
			      <0x0 0x09500000 0x0 0x80000>,
			      <0x0 0x09a00000 0x0 0x80000>;
			reg-names = "llcc0_base",
				    "llcc1_base",
				    "llcc2_base",
				    "llcc3_base",
				    "llcc_broadcast_base";
			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
			reg = <0x0 0x0a6f8800 0x0 0x400>;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pwr_event",
					  "hs_phy_irq",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq",
					  "ss_phy_irq";

			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;
			interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "usb-ddr", "apps-usb";

			wakeup-source;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			usb_1_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x0a600000 0x0 0xe000>;
				interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x80 0x0>;
				phys = <&usb_1_hsphy>, <&usb_qmpphy>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,dis_enblslpm_quirk;
				snps,dis-u1-entry-quirk;
				snps,dis-u2-entry-quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
			};
		};

		usb_2: usb@a4f8800 {
			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
			reg = <0x0 0x0a4f8800 0x0 0x400>;

			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
				 <&gcc GCC_USB20_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
				 <&gcc GCC_USB20_SLEEP_CLK>,
				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB20_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;

			interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
			interrupt-names = "pwr_event",
					  "hs_phy_irq",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq";

			power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB20_PRIM_BCR>;

			interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
					 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "usb-ddr", "apps-usb";

			qcom,select-utmi-as-pipe-clk;
			wakeup-source;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			usb_2_dwc3: usb@a400000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x0a400000 0x0 0xe000>;

				interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x20 0x0>;

				phys = <&usb_2_hsphy>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";

				snps,dis-u1-entry-quirk;
				snps,dis-u2-entry-quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				snps,dis_enblslpm_quirk;
			};
		};

		videocc: clock-controller@abf0000 {
			compatible = "qcom,qcs8300-videocc";
			reg = <0x0 0x0abf0000 0x0 0x10000>;
			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		camcc: clock-controller@ade0000 {
			compatible = "qcom,qcs8300-camcc";
			reg = <0x0 0x0ade0000 0x0 0x20000>;
			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,sa8775p-dispcc0";
			reg = <0x0 0x0af00000 0x0 0x20000>;
			clocks = <&gcc GCC_DISP_AHB_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>,
				 <0>, <0>, <0>, <0>,
				 <0>, <0>, <0>, <0>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,qcs8300-pdc", "qcom,pdc";
			reg = <0x0 0xb220000 0x0 0x30000>,
			      <0x0 0x17c000f0 0x0 0x64>;
			interrupt-parent = <&intc>;
			#interrupt-cells = <2>;
			interrupt-controller;
			qcom,pdc-ranges = <0 480 40>,
					  <40 140 14>,
					  <54 263 1>,
					  <55 306 4>,
					  <59 312 3>,
					  <62 374 2>,
					  <64 434 2>,
					  <66 438 2>,
					  <70 520 1>,
					  <73 523 1>,
					  <118 568 6>,
					  <124 609 3>,
					  <159 638 1>,
					  <160 720 3>,
					  <169 728 30>,
					  <199 416 2>,
					  <201 449 1>,
					  <202 89 1>,
					  <203 451 1>,
					  <204 462 1>,
					  <205 264 1>,
					  <206 579 1>,
					  <207 653 1>,
					  <208 656 1>,
					  <209 659 1>,
					  <210 122 1>,
					  <211 699 1>,
					  <212 705 1>,
					  <213 450 1>,
					  <214 643 2>,
					  <216 646 5>,
					  <221 390 5>,
					  <226 700 2>,
					  <228 440 1>,
					  <229 663 1>,
					  <230 524 2>,
					  <232 612 3>,
					  <235 723 5>;
		};

		aoss_qmp: power-management@c300000 {
			compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
			reg = <0x0 0x0c300000 0x0 0x400>;
			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
					       IPCC_MPROC_SIGNAL_GLINK_QMP
					       IRQ_TYPE_EDGE_RISING>;
			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
			#clock-cells = <0>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,qcs8300-tlmm";
			reg = <0x0 0x0f100000 0x0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 134>;
			interrupt-controller;
			#interrupt-cells = <2>;
			wakeup-parent = <&pdc>;

			qup_uart7_default: qup-uart7-state {
				/* TX, RX */
				pins = "gpio43", "gpio44";
				function = "qup0_se7";
			};
		};

		sram: sram@146d8000 {
			compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
			reg = <0x0 0x146d8000 0x0 0x1000>;
			ranges = <0x0 0x0 0x146d8000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;

			pil-reloc@94c {
				compatible = "qcom,pil-reloc-info";
				reg = <0x94c 0xc8>;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";

			reg = <0x0 0x15000000 0x0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <2>;
			dma-coherent;

			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI  98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI  99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x17a00000 0x0 0x10000>,
			      <0x0 0x17a60000 0x0 0x100000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
		};

		watchdog@17c10000 {
			compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
			reg = <0x0 0x17c10000 0x0 0x1000>;
			clocks = <&sleep_clk>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
		};

		timer@17c20000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x17c20000 0x0 0x1000>;
			ranges = <0x0 0x0 0x0 0x20000000>;
			#address-cells = <1>;
			#size-cells = <1>;

			frame@17c21000 {
				reg = <0x17c21000 0x1000>,
				      <0x17c22000 0x1000>;
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			};

			frame@17c23000 {
				reg = <0x17c23000 0x1000>;
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@17c25000 {
				reg = <0x17c25000 0x1000>;
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@17c27000 {
				reg = <0x17c27000 0x1000>;
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@17c29000 {
				reg = <0x17c29000 0x1000>;
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@17c2b000 {
				reg = <0x17c2b000 0x1000>;
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@17c2d000 {
				reg = <0x17c2d000 0x1000>;
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@18200000 {
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x18200000 0x0 0x10000>,
			      <0x0 0x18210000 0x0 0x10000>,
			      <0x0 0x18220000 0x0 0x10000>;
			reg-names = "drv-0",
				    "drv-1",
				    "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

			power-domains = <&system_pd>;
			label = "apps_rsc";

			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS 2>,
					  <SLEEP_TCS 3>,
					  <WAKE_TCS 3>,
					  <CONTROL_TCS 0>;

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,sa8775p-rpmh-clk";
				#clock-cells = <1>;
				clocks = <&xo_board_clk>;
				clock-names = "xo";
			};

			rpmhpd: power-controller {
				compatible = "qcom,qcs8300-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp-0 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp-1 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp-2 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp-3 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp-4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp-5 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp-6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp-7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp-8 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp-9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		remoteproc_gpdsp: remoteproc@20c00000 {
			compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
			reg = <0x0 0x20c00000 0x0 0x10000>;

			interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_gpdsp_in 0 0>,
					      <&smp2p_gpdsp_in 1 0>,
					      <&smp2p_gpdsp_in 2 0>,
					      <&smp2p_gpdsp_in 3 0>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>,
					<&rpmhpd RPMHPD_MXC>;
			power-domain-names = "cx",
					     "mxc";

			interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS
					 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>;

			memory-region = <&gpdsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_gpdsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_GPDSP0
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "gpdsp";
				qcom,remote-pid = <17>;
			};
		};

		ethernet0: ethernet@23040000 {
			compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
			reg = <0x0 0x23040000 0x0 0x00010000>,
			      <0x0 0x23056000 0x0 0x00000100>;
			reg-names = "stmmaceth", "rgmii";

			interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "sfty";

			clocks = <&gcc GCC_EMAC0_AXI_CLK>,
				 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
				 <&gcc GCC_EMAC0_PTP_CLK>,
				 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
			clock-names = "stmmaceth",
				      "pclk",
				      "ptp_ref",
				      "phyaux";
			power-domains = <&gcc GCC_EMAC0_GDSC>;

			phys = <&serdes0>;
			phy-names = "serdes";

			iommus = <&apps_smmu 0x120 0xf>;
			dma-coherent;

			snps,tso;
			snps,pbl = <32>;
			rx-fifo-depth = <16384>;
			tx-fifo-depth = <20480>;

			status = "disabled";
		};

		nspa_noc: interconnect@260c0000 {
			compatible = "qcom,qcs8300-nspa-noc";
			reg = <0x0 0x260c0000 0x0 0x16080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		remoteproc_cdsp: remoteproc@26300000 {
			compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
			reg = <0x0 0x26300000 0x0 0x10000>;

			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>,
					<&rpmhpd RPMHPD_MXC>,
					<&rpmhpd RPMHPD_NSP0>;

			power-domain-names = "cx",
					     "mxc",
					     "nsp";

			interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			memory-region = <&cdsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_cdsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_CDSP
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "cdsp";
				qcom,remote-pid = <5>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "cdsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x19c1 0x0440>,
							 <&apps_smmu 0x1961 0x0400>;
						dma-coherent;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x19c2 0x0440>,
							 <&apps_smmu 0x1962 0x0400>;
						dma-coherent;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x19c3 0x0440>,
							 <&apps_smmu 0x1963 0x0400>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x19c4 0x0440>,
							 <&apps_smmu 0x1964 0x0400>;
						dma-coherent;
					};
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};