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HPLL VCO=%u kHz, CFGC=0x%04x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: (&((const struct drm_i915_private *)(display))->display), struct drm_i915_private *: (&((struct drm_i915_private *)(display))->display), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = (0x180000 + 0x650C) })) & (1 << 27))drm_WARN_ON((val & (1 << 30)) == 0)drm_WARN_ON((val & ((1 << ((0) * 6 + 5)) | (1 << ((0) * 6 + 4)) | (1 << ((0) * 6)))) != (1 << ((0) * 6)))cdctl & ((u32)(((((int)(sizeof(struct { int:(-!!(__builtin_choose_expr( (sizeof(int) == sizeof(*(8 ? ((void *)((long)((26) > (27)) * 0l)) : (int *)8))), (26) > (27), 0))); })))) + (((~((0UL))) - (((1UL)) << (26)) + 1) & (~((0UL)) >> (64 - 1 - (27))))) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(27) * 0l)) : (int *)8))) && (sizeof(int) == sizeof(*(8 ? ((void *)((long)(26) * 0l)) : (int *)8))) && ((26) < 0 || (27) > 31 || (26) > (27)))); })))))drm_WARN_ON_ONCE(!display->funcs.cdclk->set_cdclk)%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d %s %s: [drm] cdclk state doesn't match! [drm] *ERROR* timeout waiting for FREQ change request ack [drm] *ERROR* timeout waiting for CDCLK PLL unlock [drm] *ERROR* timeout waiting for CDCLK PLL lock [drm] *ERROR* timeout waiting for DE PLL unlock [drm] *ERROR* timeout waiting for DE PLL lock drm_WARN_ON(!new_cdclk_state->base.changed)required cdclk (%d kHz) exceeds max (%d kHz) drm_WARN_ON(cdclk_pll_is_unknown(a->vco))Can change cdclk via crawling and squashing Can change cdclk via squashing Can change cdclk via crawling Can change cdclk cd2x divider with pipe %c active Modeset required for cdclk change New cdclk calculated to be logical %u kHz, actual %u kHz New voltage level calculated to be logical %u, actual %u drm_WARN_ON(vco != 8100000 && vco != 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (err %d, freq %d) drm_WARN_ON(old_div != new_div)drm_WARN_ON(mid_cdclk_config->cdclk < ({ __auto_type __UNIQUE_ID_x_1099 = (old_cdclk_config->cdclk); __auto_type __UNIQUE_ID_y_1100 = (new_cdclk_config->cdclk); do { __attribute__((__noreturn__)) extern void __compiletime_assert_1101(void) __attribute__((__error__("min""(""old_cdclk_config->cdclk"", ""new_cdclk_config->cdclk"") signedness error"))); if (!(!(!(((((typeof(__UNIQUE_ID_x_1099))(-1)) < ( typeof(__UNIQUE_ID_x_1099))1)? (2+(__builtin_constant_p((long)(old_cdclk_config->cdclk)>=0) && ((long)(old_cdclk_config->cdclk)>=0))):(1+2*(sizeof(__UNIQUE_ID_x_1099)<4))) & ((((typeof(__UNIQUE_ID_y_1100))(-1)) < ( typeof(__UNIQUE_ID_y_1100))1)? (2+(__builtin_constant_p((long)(new_cdclk_config->cdclk)>=0) && ((long)(new_cdclk_config->cdclk)>=0))):(1+2*(sizeof(__UNIQUE_ID_y_1100)<4))))))) __compiletime_assert_1101(); } while (0); ((__UNIQUE_ID_x_1099) < (__UNIQUE_ID_y_1100) ? (__UNIQUE_ID_x_1099) : (__UNIQUE_ID_y_1100)); }))drm_WARN_ON(mid_cdclk_config->cdclk > display->cdclk.max_cdclk_freq)drm_WARN_ON(cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != mid_waveform)[drm] *ERROR* PCode CDCLK freq set failed, (err %d, freq %d) drm_WARN_ON_ONCE(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && vco == 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (%d) [drm] *ERROR* Couldn't disable DPLL0 [drm] *ERROR* DPLL0 not locked Sanitizing cdclk programmed by pre-os [drm] *ERROR* timed out waiting for CDclk change %s %s: [drm] trying to change cdclk frequency with cdclk not enabled [drm] *ERROR* failed to inform pcode about cdclk change [drm] *ERROR* Switching to FCLK failed [drm] *ERROR* Switching back to LCPLL failed drm_WARN_ON(((&_Generic(dev_priv, const struct drm_i915_private *: (&((const struct drm_i915_private *)(dev_priv))->display), struct drm_i915_private *: (&((struct drm_i915_private *)(dev_priv))->display), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv))->info.__runtime_info)->step) == STEP_NONE)%s %s: [drm] Unknown platform. Assuming i830   o     R T u       o 0     w  U S   > S  b cdclkMissing case (%s == %ld) %s %s: [drm] %sdrm_WARN_ON(vco != 0)HPLL VCO %u kHz val & (7 << ((0) * 6 + 1))[hw state][sw state]dssmdividerPre changing CDCLK toPost changing CDCLK toCDCLK changeMax CD clock rate: %d kHz Max dotclock rate: %d kHz Current CDCLKhrawclki915_cdclk_infoS       0 =UaQ>Ia0 =UaQ>I(0 =UaQa2Kl6A0 =UaQ>I0 =UaQa(A  XZ9eF'rS4 ` ! "A # $ "XZ9e @~phS o@"V " "ZS "}"H"@"[J""`Z"9" "x""@"V " "KKK SK2K: KD]]]S](@l].@ ]6 S "KKK K: KD]]]@l].@ ]6  "K K: KD]@l].@ P_6 "K$K(K@KKt K ]] ]4]l@l]\@ ]l D: DKKK KDK: KD ]]]]6@l].@ ]6  " "`5K!jK!K!2K<eK<K<K< KAi915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU&0=PTpk" 00 P,9NRc0r0pF]@ F+ I F`~ E` e ;  `   0 @'<20=BH6S`b`Vz R`pz  1m22_+@5B`6Y09p00GLZP]u^  @h +T;N xf v``  `   ` ` 0  H  (@ 8 H X h  `  @       ` 0@ B  S@*<J\ekz  " 1 B [ l z         2 R  'h @'+ '* 'F  (j   (? +a -~      %  ;"B d `;}   @<B <P   & =? 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