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ED־ T$H $T$ HHHXH|$ AHD$D\$ !H|$ D\$H$ HHH8H|$ AL$DD\$H|$  ЁEADDH$ DHHHXH|$ A_Ll$0=H$HxLoPMuL/HLHH zf.AWAVAUATIUSH@H/H4$eH%(HD$81AA$D$41I$H4$HT$4LHD$HDLd$ H D,D$D,D|$DHLDMI8LDL߉IXEuDHADHLDMI8LDL߉IXDHD$A9:D$Ld$ AD$,DHH4$AWLHL$DHHH@HH@D$LDII8H|$DH|$‹D$ IXEuDHAH4$DLHL$DHHH@HH@D$HDHHL$ H8H|$HL$ H|$D‹D$ HXDHAt_A tG1 xI$pHD$8eH+%(H@[]A\A]A^A_L4D$,L|$Ld$ADDH4$H|$AUDHHH@IHD @AA HDA@HHL$H8H|$HL$DH|$%HXD EfDHAH4$H|$DDHHH@IHR @D$HDHHL$ H8H|$HL$ H|$D‹D$ HXDHAt AD$,D$DL$H$DE1H߁ߓALDA MI8LDLIXD DHAD9d${D$E1D$ DL$H$E$HD!ALωL$LDII8H|$L$DH|$IX ʹDHAH$DH߁!ELLDII8H|$DH|$%IXD DHAD9d$D$ DLL$DHLDMI8LDLIXEl$DHADHLDMI8LDLIXDHD9$$<=H}H_PHt(HHHH cH@AWAVAUIATUSH@L'H4$eH%(HD$81AD$41}IH4$HT$4LIHh1Ll$ A DD%AAD$ DD$ DT$$T$D$|$G|- % L % 1҉ƉD$H4$H|$DLHH@IHHP ыT$ % Ӻ Á ÉH4$H|$AW|$$HH@IHHP э D$ % L % кƉD$1L t$AAD A$tPH$hD$,@D$(T$AL% кxD %D ƉD$(EuMAF=u9I|$H_PHt{HHHH HD$8eH+%(uMH@[]A\A]A^A_ t(1 CI7AɃȃx!LHff.AWAVIAUATUSHHHH|$Ht$eH%(H$1H $HLD$<HT$Hu.f HHHDILx f jDAAWAGAMAA@Hfx $HωHL$H4$HH84$H|$D$D$%AHt AAdžIfx wEAA!E$LA$LAIDHA(x f dIdžLE]A|$#AHH1@LAH([]A\A]A^A_HD$#HA|$#EEGAHHtHsH54$HHL$H4$HH84$H|$D$D$%"€u@PpK1ABD8zIdžHIdžEOAf .$APILHHAXLH1|$#tWEHEGAHHDIHLDHt HKHL$PHt$1HAZIdžLIdžIdžIdžCLLH([]A\A]A^A_L@DD$$LLL$H $H $@HHL$HH8H|$@$$HL$tDD$$1EA]AOIpAGAAG f tE(Idž#HE$HAsH{HoPHuH/HHHH ~LH(H$HAcAGA4AG+tnIdžHIdžIdži@3EIdžLeHf tvIdžIdžIdžHH#f t#f u %DHBAGA"/A{IdžIdžIdžIdžkAf vLf AIdžHIdžIdžIdžHf tHIdžHIdžIdžAf~IdžHIdžIdžedrm_WARN_ON(!pll)%s %s: [drm] %slane_countMissing case (%s == %ld) drm_WARN_ON(n_entries < 1)port_clock[ENCODER:%d:%s] [CRTC:%d:%s] drm_WARN_ON(ret)disableenableddisabledcrtc_state->pipe_bpppipepll->info->ididclockpin_assignmenttmp & (7 << 12)drm_WARN_ON_ONCE(!trans)drm_WARN_ON(ctl & (1 << 9))drm_WARN_ON(!wakeref)Using signal levels %08x drm_WARN_ON(is_mst)Retry FEC enabling tmpdrm_WARN_ON(!pll_active)valencoder->portTC (TC)non-legacyyeslegacynoportPort %c strap not detected Port %c already claimed VBT says port %c has lspcon DDI %c/PHY %cDDI %s%c/PHY %s%cDDI %c%s/PHY %s%c&dig_port->hdcp_mutexdrm_WARN_ON(port > PORT_I)drivers/gpu/drm/i915/display/intel_ddi.cconn_state->connector->connector_typedrm_WARN_ON(n_entries > (sizeof(index_to_dp_signal_levels) / sizeof((index_to_dp_signal_levels)[0]) + ((int)sizeof(struct {_Static_assert(!(__builtin_types_compatible_p(typeof((index_to_dp_signal_levels)), typeof(&(index_to_dp_signal_levels)[0]))), "must be array");}))))drm_WARN_ON(dig_port->aux_wakeref)drm_WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))drm_WARN_ON(dig_port->ddi_io_wakeref)[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs drm_WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))[drm] *ERROR* [CONNECTOR:%d:%s] Failed to read TMDS config: %d drm_WARN_ON(!dig_port->dp.attached_connector)[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio Failed to %s MSA_TIMING_PAR_IGNORE in the sink Failed to set FEC_READY to %s in the sink Failed to clear FEC detected flags drm_WARN_ON(master == INVALID_TRANSCODER)[drm] *ERROR* Timeout waiting for DDI BUF %c to get active [drm] *ERROR* Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c drm_WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))drm_WARN_ON(!intel_tc_port_in_legacy_mode(dig_port))No pipe for [ENCODER:%d:%s] found Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x) Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x) [drm] *ERROR* [ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x) [drm] *ERROR* Timeout waiting for DDI BUF %c to get idle drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)Quirk Increase DDI disabled time %s %s: [drm] Unsupported voltage swing/pre-emphasis level: 0x%x drm_WARN_ON_ONCE(level >= n_entries)[drm] *ERROR* Invalid I_boost value %u drm_WARN_ON(port_mask & ((((1UL))) << (other_encoder->port)))[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it [drm] *ERROR* Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c [drm] *ERROR* Timed out waiting for DP idle patterns [drm] *ERROR* Timeout waiting for FEC live state to get %s Failed waiting for FEC %s to get detected: %d (status %d) [drm] *ERROR* Failed to enable FEC after retries drm_WARN_ON(crtc_state->has_pch_encoder)drm_WARN_ON(is_mst && (port == PORT_A || port == PORT_E))drm_WARN_ON(is_mst && port == PORT_A)[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio drm_WARN_ON(port < PORT_A || port > PORT_E)drm_WARN_ON(!(intel_ddi_splitter_pipe_mask(i915) & ((((1UL))) << (pipe))))%s %s: [drm] Invalid splitter configuration, dss1=0x%08x drm_WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)%s %s: [drm] Platform does not support DSI PORT %c / PHY %c reserved by HTI VBT says port %c is not DVI/HDMI/DP compatible, respect it SNPS PHY %c failed to calibrate, proceeding anyway Forcing DDI_A_4_LANES for port A VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s (  > @ E         8   _   .   $  a Z v L          #  B h   x U O z   s D 8 u P    Q   U `@   i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU &0c?RR Lph DW`u f)puHd@ `@   p Y@ RgppPr/rJprer~@ P@ .#D#Zp$p@%P&a&() +,2-L.-a/|124&7@9 `;p>x1BSSizX`Bci%q9uOvhw{@<[8 `W * 2D ]8 r=@PзZ  , *@ @(P X    : S          " 8 L j {       8 F e        ( A S i        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intel_ddi.cintel_ddi_dp_preemph_maxicl_ddi_tc_port_pll_typemtl_get_port_widthintel_ddi_compute_output_typeintel_ddi_dp_voltage_maxindex_to_dp_signal_levelsintel_ddi_tc_encoder_shutdown_completeintel_ddi_tc_encoder_suspend_completeintel_ddi_init_dp_buf_regintel_ddi_main_link_aux_domainmain_link_aux_power_domain_getintel_ddi_get_power_domainsintel_ddi_encoder_shutdownintel_ddi_encoder_suspendintel_ddi_initial_fastset_checkintel_ddi_sync_stateintel_ddi_post_pll_disableintel_ddi_power_up_lanesintel_ddi_compute_config_lateintel_ddi_encoder_late_registerintel_ddi_hotplugintel_ddi_link_checkintel_ddi_encoder_destroyintel_ddi_encoder_resetintel_disable_ddiintel_dp_sink_set_fec_ready.isra.0intel_ddi_transcoder_func_reg_val_get.isra.0skl_ddi_is_clock_enabledlpt_digital_port_connectedhsw_digital_port_connectedbdw_digital_port_connectedrkl_ddi_is_clock_enableddg1_ddi_is_clock_enabledicl_ddi_combo_is_clock_enabledjsl_ddi_tc_is_clock_enabledintel_ddi_config_transcoder_func.isra.0adls_ddi_is_clock_enabledintel_wait_ddi_buf_activeskl_ddi_disable_clockrkl_ddi_disable_clockdg1_ddi_disable_clockicl_ddi_combo_disable_clockjsl_ddi_tc_disable_clockadls_ddi_disable_clockCSWTCH.284icl_ddi_tc_is_clock_enabledicl_ddi_tc_disable_clockintel_ddi_mso_configurebdw_transcoder_master_readoutmtl_ddi_enable_d2d.isra.0skl_ddi_enable_clockicl_ddi_combo_enable_clockjsl_ddi_tc_enable_clockrkl_ddi_enable_clockadls_ddi_enable_clockicl_ddi_tc_enable_clockdg1_ddi_enable_clockicl_program_mg_dp_modeintel_ddi_get_encoder_pipes__already_done.13__already_done.5__already_done.4hsw_set_signal_levels__already_done.9icl_mg_phy_set_signal_levels__already_done.7tgl_dkl_phy_set_signal_levels__already_done.6icl_ddi_combo_vswing_program__already_done.8icl_combo_phy_set_signal_levelsmtl_disable_ddi_bufintel_ddi_disable_fecintel_ddi_set_link_trainintel_ddi_prepare_link_retrainmtl_ddi_prepare_link_retrainintel_ddi_set_idle_link_trainintel_disable_ddi_bufintel_ddi_post_disableintel_ddi_enable_fecintel_ddi_pre_enableintel_enable_dditrans.0__already_done.12intel_ddi_pre_pll_enableintel_ddi_get_configicl_ddi_tc_get_configdg2_ddi_get_configmtl_ddi_get_configintel_ddi_compute_configskl_ddi_get_configbxt_ddi_get_configicl_ddi_combo_get_configdg1_ddi_get_configrkl_ddi_get_configadls_ddi_get_configintel_ddi_funcs__key.1__UNIQUE_ID___addressable___SCK__preempt_schedule1217.2__UNIQUE_ID___addressable___SCK__preempt_schedule1191.3__UNIQUE_ID___addressable___SCK__preempt_schedule1004.10__UNIQUE_ID___addressable___SCK__preempt_schedule1002.11__UNIQUE_ID_import_ns960__UNIQUE_ID___addressable___SCK__might_resched2.14.LC2__x86_return_thunkdev_driver_string__warn_printk__x86_indirect_thunk_rax__stack_chk_failintel_tc_port_cleanupintel_encoder_link_check_flush_workintel_tc_port_suspendintel_encoder_is_tcintel_tc_port_in_tbt_alt_modeintel_dp_is_uhbrintel_psr_needs_aux_io_powerintel_aux_power_domainintel_display_power_aux_io_domainintel_display_power_getintel_dp_encoder_shutdownintel_hdmi_encoder_shutdownintel_dp_encoder_suspend__drm_dev_dbgintel_dp_initial_fastset_checkintel_tc_port_sanitize_modeintel_dp_sync_stateintel_display_power_put_uncheckedintel_tc_port_put_linkintel_encoder_is_combointel_encoder_to_phyintel_combo_phy_power_up_lanesdrm_mode_matchintel_tc_port_link_resetintel_dp_test_phyintel_encoder_hotplugintel_dp_check_link_state_intel_modeset_lock_begin_intel_modeset_lock_loop_intel_modeset_lock_enddrm_modeset_locktry_wait_for_completiondrm_scdc_readintel_modeset_commit_pipes_dev_errintel_dp_link_checkintel_dp_encoder_flush_workintel_display_power_flush_workdrm_encoder_cleanupkfreeintel_dp_invalidate_source_ouiintel_pps_encoder_resetintel_tc_port_init_modeintel_tc_port_link_cancel_reset_workintel_hdcp_disableintel_hdmi_handle_sink_scramblingintel_psr_disableintel_edp_backlight_offintel_dp_sink_disable_decompressiondrm_dp_dpcd_writehsw_ddi_disable_clockintel_dmc_wl_getintel_dmc_wl_puthsw_ddi_is_clock_enabledktime_get_raw__SCT__might_reschedusleep_range_statemutex_lockmutex_unlockhsw_ddi_enable_clockintel_encoder_to_tcintel_dkl_phy_readintel_tc_port_get_pin_assignment_maskintel_dkl_phy_writeintel_tc_port_in_legacy_modeintel_display_power_get_if_enabled__sw_hweight32intel_ddi_get_hw_statehsw_prepare_dp_ddi_buffersintel_bios_dp_boost_levelintel_wait_ddi_buf_idlepcpu_hotlocal_clock__SCT__preempt_schedule__const_udelayintel_ddi_set_dp_msaintel_dp_needs_vsc_sdpintel_ddi_update_pipeintel_hdmi_fastset_infoframesintel_hdcp_update_pipeintel_dp_set_infoframesintel_backlight_updatedrm_connector_update_privacy_screenintel_ddi_enable_transcoder_funcintel_ddi_disable_transcoder_funcintel_has_quirkmsleepintel_dp_mst_is_master_transintel_ddi_toggle_hdcp_bitsintel_ddi_connector_get_hw_stateintel_ddi_enable_transcoder_clockintel_ddi_disable_transcoder_clockintel_ddi_levelintel_bios_hdmi_level_shiftintel_bios_hdmi_boost_levelintel_dkl_phy_rmwis_hobl_buf_transicl_ddi_combo_get_pllintel_get_shared_dpll_by_idintel_ddi_enable_clockintel_ddi_disable_clockintel_ddi_sanitize_encoder_pll_mappingdp_tp_ctl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