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fA$lAƄ$nLA$A$?t8H H tAL$ AƄ$nfA$lA$H{AA9IcHH)HS(HH0H fA9$RfA9$RƅnA9$`A9$LA9$8 A9$ $ƅmL tƅne Hp@*H}HtHHWPHuHH$HH=H$HL AA$HHVAL$ AƄ$nfA$lXLcHC(DJ4L)L H8L9/HHtHpQtދxIsF tAL$ AƄ$nfA$lH{ b MAYAA+xD|$AI9HH#IHt<$0LL$(L\$LT$0LL$(L\$HfxAAxt vA9vEAƅYLL\$ MuL\$օHLA5HD$ H8HtHH_PHuHHH=HHI~H}HtHHWPHHT$L$HH=HT$HL$HAąHAąrHt"H{HtHƃG M HAą1H{1IHtH{IHDEIcHC(HH)LIHt HM>LHD$ HD$fx!HtApsH $pf@ tLAmAnIL8Mt LIMcA@PAEED$AAxtAAfAx DIpASLMXDT$ ‹A,BDLL\$+ALT$Ɖ$I?T$4$HH4$LLDT$ L\$LAADEЋD$D ЉD$IpP,BT +HLΉ $I?T$4$HH4$LLLL1HHHH1LuMt LIƋHH)HU(HLxEG AfAfAxvyEuyL1AG uAlLuLfAxvAL7LHL111M$HEtHHeu)HHH(LH[]A\A]A^A_LͨtPApLH$H$fxI>HtHHWPHuHHT$D$HH=HT$HD$I?HtHHWPHuHHT$DL$HH=HT$HDL$AIL?IpARLD\$$DT$ A,BDLLD$|+ALT$Ɖ$I?T$4$HH4$L1LD$DT$ D\$$ELH$H$ARL$DHHD$HD$sI?HtHHWPHuHHT$D$HH=HT$HLc$fHOATU1SHHcHH)HS(HL Mt'H@PtLHKLH0JHK9~D1HcHH)HS(HH0HtH@Pt HvHK9[]A\fAWIAVAUATUSH8HeHHD$01H|$HtIHD$HHD$ HcHD$(Iw(D$E1H H)HLL@A EDD H8I9t7HHtL@APtHcxHHA@ tH8T$I9u1AIw(HcHH)H4HtxHs LHI9LEIxHcЉHH)H)H,HH)HH$HpHhDHt$HHt$ IcDLLT HHIuHt$E!f9Dl$E,HCH9$t:HIG(HL0MtExALNHCH9$uELE1I\$%9xtUAD9IcHH)IW(HL2MtAxHsLjAIuuLu2Au(IELLxHA !IAD9iE1 DA9tTAD9~lIcHH)IW(HH2HtӋxHsHRHxuHLAH !ID9~KDd$1HcHH)IW(HH0HtxIs LEI9HcЉH,H)H)L$HI)IHIG(HL0MtiExT$LsWLPDHt$ IL$L$AIcDLLT HH D$HEL9x |$HD$0eH+-H8[]A\A]A^A_f9EHCH9$LEHD$H8HtHHWPHt2HT$L$HH=HT$HL$ HLD$HD$H8HtHH_PHuHHH=HHHD$H8HtHH_PHuHHH=HHfAVIAUATAU1SHHtHHH{HfxwSCtM~CHs(1HcHH)HH:tHR$u qtc9HAŅHAHAŅt*HLHH[D]A\A]A^HAŅuǾHAŅuHE1HHK~_IcHHS HHt?HJ`HHtHHRHHtHHKAD;|P HHCxHC`HChHChHCpEt`HS`tuH@HuHtHvEH1HHD[]A\A]A^t HHKH@pH-HATUSHt[]A\H?nAHtHLgPMuL'HH=L[]A\AUATUHSQHp@*oEfE ;E xPffHEAHHHZH9L MLL H0HHHBH9D1xIs D HPHBH9uډ{HMeLH01HHƨHBH9tBH9t&HsHs HDD HPHBH9u{LHEHSHHZH9 HH}[]A\A]fxwffE @u^}=@HH}@HH@HujtHHHHH#E=H0H4%HHHBH9fCH1[]A\A]1vE t jRHHAHAH}AHHAHAAE@HH}@HH@HAAuEtrHHBHAH}BHHBHAALEC`HH}`HH`HAAuEtE  HCHH}CHHCHAAutCHlHH}lHHlHAAuVlH?AH!BH!HHHEt^@HH}@HH@HAAtE 1Ҿ@H@HH}@HH@HAANPHH}PHHPHAABHH}BHHBHCHH}CHHCHCHHE HH\HHGBHJ@H@HAHH}AHHAHAA=AH&`HH}`HH`H0`HPHEH@HH}@HH@HHuHtHvH1@HÄuPEtJHuHtHv1H@HEtAH@HH}@HH@HAAt4HuHtHvH1`HÄEHpx+H@Hw`H# HH} HH H@|@HH}@HH@H`HH}`HH`HEHuHtHv1H`HEBHs HH} HH HAA(CHH}CHHCHCHH_HSHHtHf{ S,M3xGf9{ A @@DKA9WS9OS9GS 9?KD91K9)K9!K9iDA@[f wf v"]ɸ9W[9fwfG t A 5f fEAAD[fxNHv@f?v.v )~ Pp)ֺ~ 1f9HRv )ֺ~Pp)ֺ~1GuDx1fv-fv,R N9F9f v  ̿ff.fxHwHpHB*t HG(WHufG HHHDHG(ff.@AWAVIAUATUSHPeHHD$H1H|$HI>H1H|$IAAƅHD$IEPIHHHjH9HLHH=PHLuuK I6HHHLxH9uxI6IGHHLxH9t^AODD#CtIpHtHLuHLtuFLH|$ƀtIHEHHhH9LtAUtB~PH|$D$H|$D$HT$HeH+uCHP[]A\A]A^A_D$LD$밾LD$D$뙸ff.AWAVAUATAUSHH@eHHD$81H$Ht$HHD$H HD$$HD$,HD$D$ =BbH3D$$ED$ADL$(HtHvPH1McMoH|$L$$H߉D$HpDAh,BlLA+hLEDD$AH;HHHHpHߋh,Bl +hLH;HHHHpHߋh,Bl +hLH;HHHHpHߋh,Bl +hLH; HHHHpHߋh,Bl +hLH; HHHHpHߋh,Bl +hLH;HHHHpHߋh,Bl +hLH;HHHB,@`HH;Dl$HHDH߃HH;DHHH߽`DD$ZHpAA@,EE~ CTd,`D$(HDH;DDHHADHHpHD`,ADH;DDHHDHHpHD`,ADH;1DHHDH HpHD`,ADH;DDHHDHHpHD`,ADH;DDHHDHHpHD`,ADH;1DHHHD AfHpHMg h,Bl0+h0H;HHHHpHߋh,B,+h0H;1҉HHH߉H<$HD$8eH+uNH@[]A\A]A^A_H;HtHHoPHuH/HH=HHAVAUATIUHSH_Ht HHËDxHH)IT$(fxHLhHL,LLLHL)AuC u{C tkDHHLfxt 1DHHCHHxtJCu []A\A]A^DH[]A\A]A^HQLDHHAVAUAATUSHH3EEAIHtHvH1HpHߋh,ŀH;HHHAEHpHߋh,h4ŀ+h0H;HHHAErHpHߋh,h8ŀ+h0H;HHHAEYHpHߋh,ŀH;HHHAA'EHpHߋh,hlŀ+hhH;HHHAA'+HpIcHLr h,l0+h0H;1҉HHHHpHߋh,B,+h0H;1҉HHH߽`LHpD`,E~ CDm,`AHDH;DHHDHHpHh,H;1HHH[]A\A]A^H;HtHHoPHuH/HH=HH:H;HtHHoPHuH/HH=HHSH;HtHHoPHuH/HH=HHlH;HtHHoPHuH/HH=HHH;HtHHoPHuH/HH=HHxfv1onoff73infoframeexpected: found: Missing case (%s == %ld) crtc_state->pipe_bpp%s %s: [drm] %stmpdrm_WARN_ON(active)enabling pipe %c disabling pipe %c drm_WARN_ON(ret)drm_WARN_ON(disable_pipes)14011503117enableddisableddrm_WARN_ON(crtc->active)yesnoC10C20(expected %s, found %s)hw.enablehw.active(expected %i, found %i)cpu_transcodermst_master_transcoderhas_pch_encoderfdi_lanesfdi_m_nlane_countlane_lat_optim_maskmin_hblankdp_m_ndp_m2_n2output_typesframestart_delaymsa_timing_delayhw.pipe_mode.crtc_hdisplayhw.pipe_mode.crtc_htotalhw.pipe_mode.crtc_hblank_endhw.pipe_mode.crtc_hsync_starthw.pipe_mode.crtc_hsync_endhw.pipe_mode.crtc_vdisplayhw.pipe_mode.crtc_vsync_starthw.pipe_mode.crtc_vsync_endhw.pipe_mode.crtc_vtotalhw.pipe_mode.crtc_vblank_endhw.adjusted_mode.crtc_htotalhw.adjusted_mode.crtc_vtotalpixel_multiplier(%x) (expected %i, found %i)hw.adjusted_mode.flagsoutput_formathas_hdmi_sinklimited_color_rangehdmi_scramblinghdmi_high_tmds_clock_ratiohas_infoframeenhanced_framingfec_enablehas_audiobuffereldexpected: found: gmch_pfit.controlgmch_pfit.pgm_ratiosgmch_pfit.lvds_border_bitspch_pfit.force_thrupipe_src.x1pipe_src.x2pipe_src.y1pipe_src.y2pch_pfit.enabledpch_pfit.dst.x1pch_pfit.dst.x2pch_pfit.dst.y1pch_pfit.dst.y2scaler_state.scaler_idpixel_ratehw.casf_params.casf_enablehw.casf_params.win_sizehw.casf_params.strengthgamma_modecgm_modecsc_modegamma_enablecsc_enablewgc_enablelinetimeips_linetimepre_csc_lutpost_csc_lutcsc.preoff[0]csc.preoff[1]csc.preoff[2]csc.coeff[0]csc.coeff[1]csc.coeff[2]csc.coeff[3]csc.coeff[4]csc.coeff[5]csc.coeff[6]csc.coeff[7]csc.coeff[8]csc.postoff[0]csc.postoff[1]csc.postoff[2]output_csc.preoff[0]output_csc.preoff[1]output_csc.preoff[2]output_csc.coeff[0]output_csc.coeff[1]output_csc.coeff[2]output_csc.coeff[3]output_csc.coeff[4]output_csc.coeff[5]output_csc.coeff[6]output_csc.coeff[7]output_csc.coeff[8]output_csc.postoff[0]output_csc.postoff[1]output_csc.postoff[2]double_wide(expected %p, found %p)intel_dpll dpll_hw_stateLTPHYdpll_hw_state.ltplldpll_hw_state.cx0plldsi_pll.ctrldsi_pll.divpipe_bpphw.pipe_mode.crtc_clockhw.adjusted_mode.crtc_clockport_clockmin_voltage_levelinfoframes.enableinfoframes.gcpavispdhdmidrmdp as sdpas_sdpdp vsc sdpvscsync_mode_slaves_maskmaster_transcoderjoiner_pipesdsc.config.block_pred_enabledsc.config.convert_rgbdsc.config.simple_422dsc.config.native_422dsc.config.native_420dsc.config.vbr_enabledsc.config.line_buf_depthdsc.config.bits_per_componentdsc.config.pic_widthdsc.config.pic_heightdsc.config.slice_widthdsc.config.slice_heightdsc.config.initial_dec_delaydsc.config.initial_xmit_delaydsc.config.flatness_min_qpdsc.config.flatness_max_qpdsc.config.slice_bpg_offsetdsc.config.nfl_bpg_offsetdsc.config.initial_offsetdsc.config.final_offsetdsc.config.rc_model_sizedsc.config.slice_chunk_sizedsc.config.nsl_bpg_offsetdsc.compression_enabledsc.num_streamsdsc.compressed_bpp_x16splitter.enablesplitter.link_countsplitter.pixel_overlapvrr.enablevrr.vminvrr.vmaxvrr.fliplinevrr.vsync_startvrr.vsync_end(expected %lli, found %lli)cmrr.cmrr_mcmrr.cmrr_ncmrr.enablevrr.pipeline_fullvrr.guardbandset_context_latencymodesetfastset[CRTC:%d:%s] not active conn_state->max_bpcfaileddrm_WARN_ON(modeset_pipes)drm_WARN_ON(update_pipes)probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC ABCDEDPDSI ADSI C%s %s: [drm] %s assertion failure (expected %s, current %s) drivers/gpu/drm/i915/display/intel_display.c[drm] *ERROR* %s assertion failure (expected %s, current %s) [CRTC:%d:%s] fastset requirement not met in %s %pV [CRTC:%d:%s] mismatch in %s %pV [CRTC:%d:%s] Full modeset due to %s drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != secondary_ultrajoiner_pipes)drm_WARN_ON((primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0)drm_WARN_ON((primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0)drm_WARN_ON((primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0)%s %s: [drm] Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x) %s %s: [drm] Wrong secondary ultrajoiner pipes(expected %#x, current %#x) %s %s: [drm] Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect %s %s: [drm] Wrong secondary bigjoiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong secondary uncompressed joiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] unknown pipe linked to transcoder %s drm_WARN_ON(has_edp_transcoders(enabled_transcoders) + has_dsi_transcoders(enabled_transcoders) + has_pipe_transcoders(enabled_transcoders) > 1)drm_WARN_ON(!has_dsi_transcoders(enabled_transcoders) && !is_power_of_2(enabled_transcoders))drm_WARN_ON((tmp & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((26) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (26) >= (sizeof(u32) * 8), false)), "const_true((26) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (26))))) == 0)%s %s: [drm] transcoder %s assertion failure (expected %s, current %s) [drm] *ERROR* transcoder %s assertion failure (expected %s, current %s) drm_WARN_ON(!display->platform.i830)%s %s: [drm] pipe_off wait timed out Disabling [PLANE:%d:%s] on [CRTC:%d:%s] %s %s: [drm] %d encoders for pipe %c drm_WARN_ON(!intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF))SSC %s by BIOS, overriding VBT which says %s drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)(expected tu %i data %i/%i link %i/%i, found tu %i, data %i/%i link %i/%i)(expected 0x%08x, found 0x%08x)hw.pipe_mode.crtc_hblank_starthw.pipe_mode.crtc_vblank_starthw.adjusted_mode.crtc_hdisplayhw.adjusted_mode.crtc_hblank_starthw.adjusted_mode.crtc_hblank_endhw.adjusted_mode.crtc_hsync_starthw.adjusted_mode.crtc_hsync_endhw.adjusted_mode.crtc_vdisplayhw.adjusted_mode.crtc_vblank_starthw.adjusted_mode.crtc_vsync_starthw.adjusted_mode.crtc_vsync_endhw.adjusted_mode.crtc_vblank_endhw_state doesn't match sw_statedsc.config.scale_decrement_intervaldsc.config.scale_increment_intervaldsc.config.initial_scale_valuedsc.config.first_line_bpg_offsetdsc.config.rc_quant_incr_limit0dsc.config.rc_quant_incr_limit1dsc.config.second_line_bpg_offset[CRTC:%d:%s] modeset required [CRTC:%d:%s] async flip disallowed with joiner [CRTC:%d:%s] async flip disallowed with PSR2 selective fetch [PLANE:%d:%s] async flip not supported [PLANE:%d:%s] no old or new framebuffer drm_WARN_ON(intel_crtc_is_joiner_secondary(new_crtc_state))[CONNECTOR:%d:%s] Limiting display bpp to %d (EDID bpp %d, max requested bpp %d, max platform bpp %d) [CRTC:%d:%s] Link bpp limited to %d.%04d [ENCODER:%d:%s] rejecting invalid cloning configuration [ENCODER:%d:%s] config failure: %d [CRTC:%d:%s] set context latency (%d) exceeds max (%d) [CRTC:%d:%s] Odd pipe source width not supported with double wide pipe [CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS [CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s) [CRTC:%d:%s] config failure: %d [CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i drm_WARN_ON(new_crtc_state->uapi.enable)drm_WARN_ON(primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))[CRTC:%d:%s] Cannot act as joiner primary (need 0x%x as pipes, only 0x%x possible) [CRTC:%d:%s] secondary is enabled as normal CRTC, but [CRTC:%d:%s] claiming this CRTC for joiner. [CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s] [CRTC:%d:%s] fastset requirement not met, forcing full modeset drm_WARN_ON(!connector_state->crtc)drm_WARN_ON(!(((display)->info.__device_info)->has_ddi))rejecting conflicting digital port configuration [CRTC:%d:%s] watermarks are invalid [CRTC:%d:%s] atomic driver check failed [CRTC:%d:%s] Active planes cannot be in async flip drm_WARN_ON(new_crtc_state->do_async_flip && !plane->async_flip)[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip [PLANE:%d:%s] Stride cannot be changed in async flip [PLANE:%d:%s] Modifier cannot be changed in async flip [PLANE:%d:%s] Pixel format cannot be changed in async flip [PLANE:%d:%s] Rotation cannot be changed in async flip [PLANE:%d:%s] AUX_DIST cannot be changed in async flip [PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip [PLANES:%d:%s] Alpha value cannot be changed in async flip [PLANE:%d:%s] Pixel blend mode cannot be changed in async flip [PLANE:%d:%s] Color encoding cannot be changed in async flip [PLANE:%d:%s] Color range cannot be changed in async flip [PLANE:%d:%s] Decryption cannot be changed in async flip drm_WARN_ON(intel_crtc_needs_modeset(new_crtc_state) && intel_crtc_needs_fastset(new_crtc_state))drm_WARN_ON(new_crtc_state->use_dsb || new_crtc_state->use_flipq)drm_WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, entries, I915_MAX_PIPES, pipe))Preparing state failed with %i %s %s: [drm] Platform does not support port %c drm_WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154)enabling pipe %c due to force quirk (vco=%d dot=%d) disabling pipe %c due to force quirk drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = (((display)->info.__device_info)->pipe_offsets[(PLANE_A)] - ((display)->info.__device_info)->pipe_offsets[PIPE_A] + (((display)->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = (((display)->info.__device_info)->pipe_offsets[(PLANE_B)] - ((display)->info.__device_info)->pipe_offsets[PIPE_A] + (((display)->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = (((display)->info.__device_info)->pipe_offsets[(PLANE_C)] - ((display)->info.__device_info)->pipe_offsets[PIPE_A] + (((display)->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((int)sizeof(struct {_Static_assert(!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((31) >= (sizeof(u32) * 8)) * 0l)) : (int *)8))), (31) >= (sizeof(u32) * 8), false)), "const_true((31) >= BITS_PER_TYPE(u32))" " is true");})) + ((((1ULL))) << (31)))))drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = ((((display))->info.__device_info)->cursor_offsets[((PIPE_A))] - (((display))->info.__device_info)->cursor_offsets[PIPE_A] + ((((display))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27)drm_WARN_ON(intel_de_read(display, ((const i915_reg_t){ .reg = ((((display))->info.__device_info)->cursor_offsets[((PIPE_B))] - (((display))->info.__device_info)->cursor_offsets[PIPE_A] + ((((display))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27)  r  E  4 < @ F J P ^ m " ) | .    h     l   ` J f    `  D       N 1   ? J    G )      ~       $$$$$i915.import_ns=PWMi915_reg_rwGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU)GPa}0_r   0`rPP1PcS{    @ >`Rdew0@ `z@2Jbwp  ,12v5 )@840CEpGfPw}W^` iN  + `W ВL0?27B,M _|0@0000@6) :j (*0Z8@HPXL`}hpx A r    5 e    % U     E u     (5 0e 8 @ H P%XU`hpxEu5e =w   @ * Y Z   `    `  8 $ * 0  6 =Pix"0S|3Nl8Je&7Zz 6I\p(@ABpA!ZAmz0BjBd`D/D.0DiR`EiwE+ F,`F,F(F GE  H2JvJfM5ZQ? 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3:D:b:::::intel_display.cintel_crtc_vrr_enablingintel_encoders_pre_pll_enableintel_encoders_pre_enableintel_encoders_post_disableintel_encoders_post_pll_disableintel_cpu_transcoders_need_modesetintel_joiner_adjust_pipe_srcassert_planeassert_planes_disabledallow_vblank_delay_fastsetpipe_config_mismatchpipe_config_infoframe_mismatchintel_modeset_pipeneeds_async_flip_vtd_waintel_old_crtc_state_disablesintel_enable_crtcintel_encoders_disableintel_encoders_enableintel_crtc_compute_pixel_rateintel_splitter_adjust_timings.isra.0intel_joiner_adjust_timings.isra.0is_bigjoiner.isra.0bdw_set_pipe_miscneeds_cursorclk_waintel_atomic_cleanup_workintel_crtc_readout_derived_stateintel_crtc_copy_uapi_to_hw_state_nomodesetintel_crtc_copy_uapi_to_hw_state_modesethsw_set_linetime_wmintel_async_flip_vtd_waintel_get_pipe_src_sizeintel_set_pipe_src_sizeicl_set_pipe_chickentranscoder_ddi_func_is_enabledintel_set_transcoder_timingsenabled_joiner_pipesintel_get_transcoder_timings.isra.0ilk_get_pipe_configi9xx_get_pipe_confighsw_get_pipe_configCSWTCH.426hsw_crtc_disablecopy_joiner_crtc_state_nomodesetilk_crtc_disable.LC16intel_pre_plane_updateintel_pre_update_crtcintel_atomic_commit_tailintel_atomic_commit_workhsw_crtc_enablei9xx_configure_cpu_transcoderi9xx_crtc_enablevalleyview_crtc_enableilk_crtc_enableCSWTCH.526intel_update_crtcintel_commit_modeset_enablesskl_commit_modeset_enablesskl_display_funcsddi_display_funcspch_split_display_funcsvlv_display_funcsi9xx_display_funcsi9xx_crtc_disable__UNIQUE_ID_addressable___SCK__WARN_trap_1188.0__UNIQUE_ID_addressable___SCK__WARN_trap_1187.1__UNIQUE_ID_addressable___SCK__WARN_trap_1186.2__UNIQUE_ID_addressable___SCK__WARN_trap_1185.3__UNIQUE_ID_addressable___SCK__WARN_trap_1184.4__UNIQUE_ID_addressable___SCK__WARN_trap_1183.5__UNIQUE_ID_addressable___SCK__WARN_trap_1182.6__UNIQUE_ID_addressable___SCK__WARN_trap_1181.7__UNIQUE_ID_addressable___SCK__WARN_trap_1180.8__UNIQUE_ID_addressable___SCK__WARN_trap_1179.9__UNIQUE_ID_addressable___SCK__WARN_trap_1178.10__UNIQUE_ID_addressable___SCK__WARN_trap_1177.11__UNIQUE_ID_addressable___SCK__WARN_trap_1176.12__UNIQUE_ID_addressable___SCK__WARN_trap_1175.13__UNIQUE_ID_addressable___SCK__WARN_trap_1174.14__UNIQUE_ID_addressable___SCK__WARN_trap_1173.15__UNIQUE_ID_addressable___SCK__WARN_trap_1172.16__UNIQUE_ID_addressable___SCK__WARN_trap_1171.17__UNIQUE_ID_addressable___SCK__WARN_trap_1170.18__UNIQUE_ID_addressable___SCK__WARN_trap_1169.19__UNIQUE_ID_addressable___SCK__WARN_trap_1166.20__UNIQUE_ID_addressable___SCK__WARN_trap_994.21__UNIQUE_ID_addressable___SCK__WARN_trap_993.22__UNIQUE_ID_addressable___SCK__WARN_trap_992.23__UNIQUE_ID_addressable___SCK__WARN_trap_967.24__UNIQUE_ID_addressable___SCK__WARN_trap_966.25__UNIQUE_ID_addressable___SCK__WARN_trap_965.26__UNIQUE_ID_addressable___SCK__WARN_trap_964.27__UNIQUE_ID_addressable___SCK__WARN_trap_963.28__UNIQUE_ID_addressable___SCK__WARN_trap_962.29__UNIQUE_ID_addressable___SCK__WARN_trap_961.30__UNIQUE_ID_addressable___SCK__WARN_trap_960.31__UNIQUE_ID_addressable___SCK__WARN_trap_959.32__UNIQUE_ID_addressable___SCK__WARN_trap_958.33__UNIQUE_ID_addressable___SCK__WARN_trap_957.34__UNIQUE_ID_addressable___SCK__WARN_trap_956.35__UNIQUE_ID_addressable___SCK__WARN_trap_955.36__UNIQUE_ID_addressable___SCK__WARN_trap_954.37__UNIQUE_ID_addressable___SCK__WARN_trap_953.38__UNIQUE_ID_addressable___SCK__WARN_trap_952.39__UNIQUE_ID_addressable___SCK__WARN_trap_931.40__UNIQUE_ID_addressable___SCK__WARN_trap_930.41__UNIQUE_ID_addressable___SCK__WARN_trap_929.42__UNIQUE_ID_addressable___SCK__WARN_trap_928.43__UNIQUE_ID_addressable___SCK__WARN_trap_917.44__UNIQUE_ID_addressable___SCK__WARN_trap_916.45__UNIQUE_ID_addressable___SCK__WARN_trap_915.46__UNIQUE_ID_addressable___SCK__WARN_trap_844.47__UNIQUE_ID_addressable___SCK__WARN_trap_843.48__UNIQUE_ID_addressable___SCK__WARN_trap_837.49__UNIQUE_ID_addressable___SCK__WARN_trap_836.50__UNIQUE_ID_addressable___SCK__WARN_trap_835.51__UNIQUE_ID_addressable___SCK__WARN_trap_834.52__UNIQUE_ID_addressable___SCK__WARN_trap_833.53__UNIQUE_ID_addressable___SCK__WARN_trap_831.54__UNIQUE_ID_addressable___SCK__WARN_trap_830.55__UNIQUE_ID_addressable___SCK__WARN_trap_829.56__UNIQUE_ID_addressable___SCK__WARN_trap_828.57__UNIQUE_ID_modinfo_827__UNIQUE_ID_addressable___SCK__WARN_trap_808.58__UNIQUE_ID_addressable___SCK__tp_func_i915_reg_rw_807.59__trace_check_i915_reg_rw.60__UNIQUE_ID_addressable___SCK__preempt_schedule_notrace_57.61.LC2.LC3.LC13.LC15.LC17.LC23.LC24.LC25.LC26.LC27.LC28.LC29.LC30.LC32.LC38.LC43.LC45.LC306__x86_return_thunk__x86_indirect_thunk_rax__sw_hweight32__ref_stack_chk_guard__drm_to_display_dev_errdev_driver_string__SCT__WARN_trap__stack_chk_failintel_vrr_always_use_vrr_tgdrm_printf__drm_debughdmi_infoframe_log__drm_dev_dbgdrm_atomic_add_affected_connectorsintel_dp_mst_add_topology_state_for_crtcintel_plane_add_affectedintel_display_vtd_activeintel_crtc_disable_pipe_crcintel_psr_notify_pipe_changeintel_fbc_disableintel_initial_watermarksintel_crtc_update_active_timingsintel_crtc_enable_pipe_crcintel_opregion_notify_encoderintel_adjusted_rateintel_dsb_reg_writeicl_hdr_plane_mask__tracepoint_i915_reg_rwto_intel_uncorecpu_number__cpu_online_mask__preempt_count__SCT__tp_func_i915_reg_rw__SCT__preempt_schedule_notraceintel_dsb_cleanupintel_color_cleanup_commitdrm_atomic_helper_cleanup_planesdrm_atomic_helper_commit_cleanup_done__drm_atomic_state_freerefcount_warn_saturatedrm_mode_copydrm_mode_set_namedrm_property_replace_blobintel_dmc_wl_getintel_dmc_wl_putintel_display_power_get_if_enabled__intel_display_power_put_async__x86_indirect_thunk_r10intel_dsc_power_domainintel_color_get_configilk_pch_get_configilk_pfit_get_configintel_display_power_put_uncheckedi9xx_pfit_get_configi9xx_dpll_get_hw_statevlv_crtc_clock_getchv_crtc_clock_geti9xx_crtc_clock_getintel_display_power_get_in_set_if_enabledintel_dsc_get_configintel_vrr_get_configskl_scaler_get_confighsw_ips_get_configintel_display_power_put_mask_in_setbxt_dsi_pll_is_enabledis_trans_port_sync_masteris_trans_port_sync_modeintel_crtc_is_bigjoiner_primaryintel_crtc_is_bigjoiner_secondary_intel_modeset_primary_pipesintel_dpll_disableintel_crtc_for_pipeintel_dmc_disable_pipe_intel_modeset_secondary_pipesintel_crtc_is_ultrajoinerintel_crtc_is_ultrajoiner_primaryintel_crtc_ultrajoiner_enable_neededintel_crtc_joiner_secondary_pipesintel_crtc_is_joiner_secondaryintel_crtc_is_joiner_primaryintel_crtc_num_joined_pipesintel_crtc_joined_pipe_maskintel_primary_crtcassert_transcoderintel_enable_transcoderintel_crtc_max_vblank_countintel_wait_for_pipe_scanline_movingassert_dsi_pll_enabledassert_pll_enabledintel_crtc_pch_transcoderassert_fdi_rx_pll_enabledassert_fdi_tx_pll_enabledintel_disable_transcoder__intel_wait_for_registerintel_wait_for_pipe_scanline_stoppedintel_set_cpu_fifo_underrun_reportingintel_set_pch_fifo_underrun_reportingintel_crtc_vblank_offilk_pfit_disableilk_pch_disableilk_pch_post_disableintel_plane_fb_max_strideintel_first_crtcintel_dumb_fb_max_stridedrm_get_format_infointel_set_plane_visibleintel_plane_fixup_bitmasksintel_plane_disable_noatomicintel_plane_set_invisibleskl_wm_plane_disable_noatomicintel_plane_disable_armintel_plane_initial_vblank_waithsw_ips_disableintel_set_memory_cxsrintel_plane_fence_y_offsetintel_plane_adjust_aligned_offsetintel_has_pending_fb_unpin_raw_spin_locktry_wait_for_completion_raw_spin_unlockintel_crtc_wait_for_next_vblankintel_get_crtc_new_encoderintel_crtc_vrr_disablingintel_alpm_pre_plane_updateintel_psr_pre_plane_updateintel_drrs_deactivatehsw_ips_pre_updateintel_fbc_pre_updateintel_casf_disable__x86_indirect_thunk_rcxilk_disable_cxsrintel_plane_async_flipintel_update_watermarksintel_vrr_disablememcmpintel_color_load_lutsintel_vrr_set_transcoder_timingsintel_casf_update_strengthintel_fbc_updateintel_display_power_is_enabledintel_dpt_configureintel_casf_enableintel_color_commit_noarmintel_crtc_planes_update_noarm__x86_indirect_thunk_r9intel_phy_is_combointel_phy_is_tcintel_phy_is_snpsintel_port_to_phyintel_port_to_tcintel_encoder_to_phyintel_encoder_is_combointel_encoder_is_snpsintel_encoder_is_tcintel_encoder_to_tcintel_aux_power_domainintel_tc_port_in_tbt_alt_modeintel_display_power_legacy_aux_domainintel_display_power_tbt_aux_domainintel_modeset_get_crtc_power_domains__bitmap_andnotintel_display_power_get_in_setintel_flipq_supportedintel_color_prepare_commiti915_fence_context_timeoutdma_fence_wait_timeoutdma_fence_releaseintel_fb_rc_ccs_cc_planeintel_fb_bointel_bo_read_from_pageintel_fbc_prepare_dirty_rectintel_dsb_prepareintel_psr_trigger_frame_change_eventintel_psr_wait_for_idle_dsbintel_color_commit_armintel_psr2_program_trans_man_trk_ctlintel_crtc_planes_update_armintel_color_uses_chained_dsbintel_dsb_chainintel_dsb_finishdrm_atomic_helper_wait_for_dependenciesdrm_dp_mst_atomic_wait_for_dependenciesintel_atomic_global_state_wait_for_dependenciesintel_display_power_getintel_overlay_switch_offintel_frontbuffer_flipdrm_vblank_work_flush_allintel_pmdemand_pre_plane_updateintel_set_cdclk_pre_plane_updateintel_sagv_pre_plane_update_raw_spin_lock_irqdrm_crtc_send_vblank_event_raw_spin_unlock_irqintel_dbuf_pre_plane_updateintel_color_uses_gosub_dsbintel_dsb_gosubintel_dsb_wait_vblanksintel_vrr_send_pushintel_dsb_wait_for_delayed_vblankintel_vrr_check_push_sentintel_dsb_interruptintel_program_dpkgc_latencyintel_wait_for_vblank_workersdrm_atomic_helper_wait_for_flip_doneintel_dsb_waitintel_color_wait_commitintel_flipq_disableintel_dbuf_post_plane_updateintel_fbc_post_updateintel_color_post_update__intel_display_waadl_scaler_ecc_unmaskintel_alpm_post_plane_updateintel_psr_post_plane_updateintel_modeset_verify_crtchsw_ips_post_updateintel_drrs_activateintel_check_cpu_fifo_underrunsintel_check_pch_fifo_underrunsintel_sagv_post_plane_updateintel_set_cdclk_post_plane_updateintel_pmdemand_post_plane_updatedrm_atomic_helper_commit_hw_doneintel_atomic_global_state_commit_doneintel_display_rpm_putqueue_work_onintel_optimize_watermarksintel_dp_mst_is_slave_transintel_dsb_vblank_evadeintel_flipq_wait_dmc_haltintel_flipq_unhalt_dmcskl_detach_scalersdrm_atomic_helper_update_legacy_modeset_stateintel_uncore_arm_unclaimed_mmio_detectionintel_modeset_verify_disabledintel_modeset_put_crtc_power_domainsintel_encoder_destroydrm_encoder_cleanupkfreeintel_encoder_get_configintel_link_compute_m_nintel_dp_link_symbol_clockintel_dp_effective_data_ratedrm_dp_max_dprx_data_rateintel_panel_sanitize_sscintel_zero_m_nintel_set_m_nintel_cpu_transcoder_has_m2_n2intel_cpu_transcoder_set_m1_n1intel_cpu_transcoder_set_m2_n2intel_dmc_enable_pipeintel_dpll_enableintel_dsc_enableskl_pfit_enableintel_color_modesetilk_pfit_enableintel_uncompressed_joiner_enablei9xx_set_pipeconfi9xx_enable_plli9xx_pfit_enableintel_crtc_vblank_onvlv_enable_pllchv_enable_pllilk_set_pipeconfassert_fdi_tx_disabledassert_fdi_rx_disabledilk_pch_pre_enableilk_pch_enablebdw_get_pipe_misc_bppilk_get_lanes_requiredintel_get_m_nintel_cpu_transcoder_get_m1_n1intel_cpu_transcoder_get_m2_n2intel_crtc_get_pipe_config__x86_indirect_thunk_rdxintel_dotclock_calculateintel_dp_link_symbol_sizeintel_crtc_dotclockintel_encoder_current_modekmalloc_caches__kmalloc_cache_noprofintel_crtc_state_allocintel_crtc_destroy_stateintel_display_min_pipe_bppintel_display_max_pipe_bppintel_fuzzy_clock_checkintel_pipe_config_compare__drm_printfn_dbgintel_dpll_compare_hw_statedrm_dp_as_sdp_logdrm_dp_vsc_sdp_logintel_hdmi_infoframe_enableintel_dpll_dump_hw_stateintel_cx0pll_compare_hw_stateintel_cx0pll_dump_hw_state__drm_printfn_errintel_lt_phy_pll_compare_hw_stateintel_lt_phy_dump_hw_statedrm_print_hex_dumpintel_color_lut_equalintel_modeset_pipes_in_mask_earlyintel_atomic_get_crtc_stateintel_modeset_all_pipes_lateintel_modeset_commit_pipesdrm_atomic_state_allocdrm_atomic_commitintel_calc_enabled_pipesintel_calc_active_pipesintel_atomic_checkintel_display_driver_check_accessintel_vrr_check_modesetdrm_atomic_helper_check_modesetintel_link_bw_init_limitsintel_link_bw_set_bpp_limit_for_pipeintel_fdi_add_affected_crtcsintel_crtc_free_hw_statedrm_mode_get_hv_timingintel_dpll_crtc_compute_clockintel_psr_min_set_context_latencyilk_fdi_compute_configdrm_mode_set_crtcinfointel_link_bw_atomic_checkkmemdup_noprofintel_vrr_compute_guardbandintel_dpll_releaseintel_any_crtc_needs_modesetdrm_connector_list_iter_begindrm_connector_list_iter_nextdrm_connector_list_iter_endintel_plane_atomic_checkintel_crtc_min_cdclkintel_compute_global_watermarksintel_crtc_state_dumpintel_dp_mst_crtc_needs_modesetintel_is_dual_link_lvdsintel_bw_atomic_checkintel_cdclk_atomic_checkintel_pmdemand_atomic_checkintel_dpll_crtc_get_dpllintel_color_checkintel_casf_compute_configskl_update_scaler_crtcintel_atomic_setup_scalershsw_crtc_supports_ipsintel_atomic_get_cdclk_stateintel_cdclk_logicalintel_psr2_sel_fetch_updateintel_fbc_atomic_checkintel_color_assert_lutsintel_plane_can_async_flipskl_plane_aux_distintel_wm_computeskl_watermark_ipc_enabledhsw_ips_compute_configintel_casf_needs_scalerintel_crtc_arm_fifo_underrunintel_crtc_prepare_vblank_eventintel_dsb_commitintel_pipe_update_startintel_vrr_set_fixed_rr_timingsintel_vrr_transcoder_enableintel_atomic_update_watermarksintel_color_uses_dsbintel_flipq_enableintel_flipq_addintel_pipe_update_endintel_vrr_enableintel_dbuf_mbus_pre_ddb_updateskl_ddb_allocation_overlapsintel_dbuf_mbus_post_ddb_updateintel_atomic_commitintel_display_rpm_getdrm_atomic_helper_prepare_planesdrm_atomic_helper_setup_commitdrm_atomic_helper_unprepare_planesintel_atomic_global_state_setup_commitdrm_atomic_helper_swap_stateintel_atomic_swap_global_stateintel_dpll_swap_stateintel_frontbuffer_track__flush_workqueueassert_port_validintel_setup_outputsintel_pps_unlock_regs_waintel_init_pch_refclkdrm_helper_move_panel_connectors_to_headintel_crt_initintel_ddi_initintel_bios_for_each_encodervlv_dsi_initintel_dp_is_port_edpintel_bios_is_port_presentg4x_dp_initg4x_hdmi_initintel_lvds_initintel_dvo_initintel_sdvo_initintel_tv_initintel_mode_validintel_cpu_transcoder_mode_validintel_mode_valid_max_plane_sizeintel_init_display_hooksintel_initial_commitdrm_modeset_acquire_initdrm_atomic_add_affected_planesdrm_atomic_state_cleardrm_modeset_backoffdrm_modeset_drop_locksdrm_modeset_acquire_finii830_enable_pipei9xx_calc_dpll_paramsi9xx_dpll_compute_fp__const_udelayi9xx_pfit_disablevlv_disable_plli9xx_disable_pllchv_disable_plli830_disable_pipeintel_scanout_needs_vtd_wa__SCK__WARN_trapi9xx_get_initial_plane_configi9xx_fixup_initial_plane_configskl_get_initial_plane_configskl_fixup_initial_plane_config__SCK__tp_func_i915_reg_rw__SCK__preempt_schedule_notrace%eG[z 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