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((((unsigned int) ((!!((mask) & (1ULL << 0))) + (!!((mask) & (1ULL << 1))) + (!!((mask) & (1ULL << 2))) + (!!((mask) & (1ULL << 3))) + (!!((mask) & (1ULL << 4))) + (!!((mask) & (1ULL << 5))) + (!!((mask) & (1ULL << 6))) + (!!((mask) & (1ULL << 7))))) + ((unsigned int) ((!!(((mask) >> 8) & (1ULL << 0))) + (!!(((mask) >> 8) & (1ULL << 1))) + (!!(((mask) >> 8) & (1ULL << 2))) + (!!(((mask) >> 8) & (1ULL << 3))) + (!!(((mask) >> 8) & (1ULL << 4))) + (!!(((mask) >> 8) & (1ULL << 5))) + (!!(((mask) >> 8) & (1ULL << 6))) + (!!(((mask) >> 8) & (1ULL << 7)))))) + (((unsigned int) ((!!(((mask) >> 16) & (1ULL << 0))) + (!!(((mask) >> 16) & (1ULL << 1))) + (!!(((mask) >> 16) & (1ULL << 2))) + (!!(((mask) >> 16) & (1ULL << 3))) + (!!(((mask) >> 16) & (1ULL << 4))) + (!!(((mask) >> 16) & (1ULL << 5))) + (!!(((mask) >> 16) & (1ULL << 6))) + (!!(((mask) >> 16) & (1ULL << 7))))) + ((unsigned int) ((!!((((mask) >> 16) >> 8) & (1ULL << 0))) + (!!((((mask) >> 16) >> 8) & (1ULL << 1))) + (!!((((mask) >> 16) >> 8) & (1ULL << 2))) + (!!((((mask) >> 16) >> 8) & (1ULL << 3))) + (!!((((mask) >> 16) >> 8) & (1ULL << 4))) + (!!((((mask) >> 16) >> 8) & (1ULL << 5))) + (!!((((mask) >> 16) >> 8) & (1ULL << 6))) + (!!((((mask) >> 16) >> 8) & (1ULL << 7))))))) : __arch_hweight32(mask)) > 1)[drm] *ERROR* Port %s: timeout waiting for PHY ready drm_WARN_ON(phy_is_owned && !phy_is_ready)drm_WARN_ON(!intel_display_power_is_enabled(i915, tc_port_power_domain(tc)))drm_WARN_ON(live_mode == TC_PORT_TBT_ALT)Port %s: PHY mode: %s (ready: %s, owned: %s, HPD: %s) drm_WARN_ON(tc->mode != TC_PORT_DISCONNECTED)Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag Port %s: TC port mode reset (%s -> %s) drm_WARN_ON(tc->mode == TC_PORT_DISCONNECTED)drm_WARN_ON(tc->mode != TC_PORT_TBT_ALT && !tc_phy_is_owned(tc))Port %s: TypeC DP-alt sink disconnected, resetting link Port %s: PHY in TCCOLD, nothing connected Port %s: PHY in TCCOLD, assume not owned Port %s: PHY in TCCOLD, assuming not ready Port %s: timeout waiting for TCSS power to get %s drm_WARN_ON(tc->mode == TC_PORT_LEGACY)Port %s: PHY in TCCOLD, can't %s ownership drm_WARN_ON(!intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE))drm_WARN_ON((tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) && !xelpdp_tc_phy_tcss_power_is_enabled(tc))drm_WARN_ON(val == 0xffffffff)drm_WARN_ON(pin_mask == 0xffffffff)drm_WARN_ON(lane_mask == 0xffffffff)drm_WARN_ON(tc->mode != TC_PORT_DP_ALT)Port %s: PHY sudden disconnect Port %s: PHY max lanes %d < required lanes %d Port %s: can't take PHY ownership (ready %s) Port %s: can't take PHY ownership drm_WARN_ON(lane_reversal && tc->mode != TC_PORT_LEGACY)drm_WARN_ON(tc->link_refcount)[drm] *ERROR* Port %s: PHY disconnected on enabled port, connecting it drm_WARN_ON(tc->link_refcount != 1)[drm] *ERROR* Port %s: PHY disconnected with %d active link(s) Port %s: PHY left in %s mode on disabled port, disconnecting it Port %s: PHY connected: %s (ready: %s, owned: %s, pll_type: %s) drm_WARN_ON(!intel_tc_port_ref_held(dig_port))drm_WARN_ON(tc_port == TC_PORT_NONE)T      1  k       z  L  " M b 8  r v  s z        H @ i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU '0(Bp(^$p xa0pyc`X;4L7]&mPP ` O P  8,PGq\ouq`04QpjpRf` `! '8)R*%,; @MU`@e@t@ &EWet-8LYp,CTl"%"%#%P#(=#?[#$`-`/#1" - 4E U 5ot 06   6(07 `7,   7N1 8*H @8j_ 8vv P9#        ;[ intel_tc.ctgl_tc_phy_cold_off_domainicl_tc_phy_cold_off_domainadlp_tc_phy_cold_off_domaintc_port_mode_namenames.1assert_tc_cold_blocked__already_done.2tc_phy_wait_for_readytc_phy_is_ready_and_owned.isra.0assert_tc_port_power_enabled.isra.0adlp_tc_phy_take_ownership.isra.0tc_phy_get_target_modetc_phy_get_current_modeadlp_tc_phy_initicl_tc_phy_initintel_tc_port_reset_mode__intel_tc_port_lockintel_tc_port_disconnect_phy_workintel_tc_port_link_reset_workadlp_tc_phy_disconnectadlp_tc_phy_hpd_live_statusxelpdp_tc_phy_hpd_live_statusicl_tc_phy_hpd_live_statusadlp_tc_phy_is_ownedadlp_tc_phy_get_hw_stateicl_tc_phy_get_hw_stateicl_tc_phy_is_ownedicl_tc_phy_is_readyxelpdp_tc_phy_is_ownedxelpdp_tc_phy_tcss_power_is_enabledxelpdp_tc_phy_wait_for_tcss_power__xelpdp_tc_phy_enable_tcss_powerxelpdp_tc_phy_take_ownershipxelpdp_tc_phy_disconnecticl_tc_phy_take_ownershipicl_tc_phy_disconnectadlp_tc_phy_is_readyxelpdp_tc_phy_get_hw_statetgl_tc_phy_inittc_phy_verify_legacy_or_dp_alt_modeicl_tc_phy_connectadlp_tc_phy_connectxelpdp_tc_phy_connectxelpdp_tc_phy_ops__key.0adlp_tc_phy_opstgl_tc_phy_opsicl_tc_phy_ops__UNIQUE_ID_import_ns960__UNIQUE_ID___addressable___SCK__might_resched29.3.LC1__x86_return_thunkintel_display_power_legacy_aux_domain__x86_indirect_thunk_raxintel_display_power_is_enableddev_driver_string__warn_printk__sw_hweight32ktime_get_raw__SCT__might_reschedusleep_range_state_dev_errintel_encoder_to_tcintel_dmc_wl_getintel_dmc_wl_put__drm_dev_dbgintel_display_power_flush_workintel_aux_power_domainmutex_lockcancel_delayed_workmutex_unlockdrm_atomic_state_alloc_intel_modeset_lock_begin_intel_modeset_lock_loopdrm_modeset_lockintel_dp_get_active_pipesintel_atomic_get_crtc_state_intel_modeset_lock_enddrm_atomic_commit__drm_atomic_state_freerefcount_warn_saturate__stack_chk_failintel_display_power_getintel_display_power_put_unchecked__intel_display_power_put_asyncintel_tc_port_in_tbt_alt_modeintel_encoder_is_tcintel_tc_port_in_dp_alt_modeintel_tc_port_in_legacy_modeintel_tc_port_handles_hpd_glitchesintel_tc_cold_requires_aux_pwintel_tc_port_get_pin_assignment_maskintel_tc_port_max_lane_countintel_tc_port_set_fia_lane_countintel_tc_port_init_modeintel_tc_port_sanitize_modeintel_dp_mst_encoder_active_linksintel_ddi_port_pll_typeintel_tc_port_connectedmutex_is_lockedintel_tc_port_link_needs_resetintel_tc_port_link_resetsystem_unbound_wqqueue_delayed_work_onintel_tc_port_link_cancel_reset_workintel_tc_port_suspendcancel_delayed_work_syncflush_delayed_workintel_tc_port_unlockintel_tc_port_ref_heldintel_tc_port_get_linkintel_tc_port_put_linkintel_tc_port_initkmalloc_caches__kmalloc_cache_noprofkasprintf__mutex_initdelayed_work_timer_fninit_timer_keykfreeintel_tc_port_cleanup__SCK__might_resched 9 @ A)B0  : #BC@D::B ( #C#E/FJGZEx@ XHB % #-CeIpAB  #CJ&@H@RK@,@p 3 7 @L : DCS :\ DaCB  #CIIzM@?@ L6N@A^Be ^o #wCD  Lh @ @ B w # C B! x( #0 Cd Om P @ B P # C B  & #. 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