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Ƀ*( & Ƀ*  Ƀ*  LxHDžp*  Ƀ*  EA A* A$ Ƀ*A$ MgLEgX*DLeMt Md$LpHXPAQPPAPHPW@1PV8PAS4PP0PP,PP(PP$PP PPPPPPPPPP PPPPPPPPPARPQHPRLDHpHiӚH`I L,  D| Dt p$ X P H @ 8 4H 0 ,| (t $, $   HxLeMOEGX    1MtIt$HHiۚW1ARASpPXPPPHP@P8P4P0P,P(P$P PPPPP PQHRIL D Hİz r p * D" X P  HH @ 8z 4r 0* ," ( $   Le MOEGXHx Mt Md$L`ARWVQHASpWXWPWHWR@W8W4W0W,W(W$W WWW1SPH`HİA|A8|A|A8|A<fA9|HH9HiÚI|Lw Dw  D  D D8Dx D8x Dv D8v Dt fD9t D8D D8 D~ D8~ lD| fD9| VD8M 8 :HiÚLD D8  f9 ]DHhLx"A@p8Bp@H0IHWPHuHLPLXHUHUHHH LXLP4ILhH9EM1AfAx ~MHME1D^H11D]jpipeMissing case (%s == %ld) %s %s: [drm] %syesnoenableddisabledSAGV available: %s SAGV modparam: %s SAGV status: %s SAGV block time: %d usec wp->cppdrm_WARN_ON(pixel_rate == 0)Disabling SAGV Enabling SAGV Gen9 Planei915_ipc_statusi915_sagv_statusdrm_WARN_ON(ret)minimum required %d/%d unknownnot controlleddrivers/gpu/drm/i915/display/skl_watermark.cdrm_WARN_ON(!dbuf_state->joined_mbus)drm_WARN_ON(!is_power_of_2(dbuf_state->active_pipes))Isochronous Priority Control: %s Changing mbus joined: %s -> %s (pipe: %c) Non planar format have single plane drivers/gpu/drm/i915/display/intel_fixed.hNo SAGV found on system, ignoring [drm] *ERROR* Failed to disable SAGV (%d) [CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s BIOS has misprogrammed the DBUF, disabling all planes drm_WARN_ON(crtc_state->active_planes != 0)Restricting QGV points: 0x%x -> 0x%x Relaxing QGV points: 0x%x -> 0x%x [drm] *ERROR* Failed to enable SAGV [drm] *ERROR* mismatch in DBUF Slices (expected 0x%x, got 0x%x) [drm] *ERROR* [PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u) [drm] *ERROR* [PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u)) [drm] Enabling IPC: WM will be proper only after next commit drm_WARN_ON(i915->display.sagv.status == I915_SAGV_UNKNOWN)Couldn't read SAGV block time! SAGV supported: %s, original SAGV block time: %u us %s %s: [drm] Excessive SAGV block time %u, ignoring [drm] *ERROR* SKL Mailbox read error = %d Updating dbuf ratio to %d (mbus joined: %s) drm_WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state))drm_WARN_ON(!fb->format->is_yuv || fb->format->num_planes == 1)Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s [CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x drm_WARN_ON(wm->wm[level].min_ddb_alloc != ((u16)~0U))Requested display configuration exceeds system DDB limitationsdrm_WARN_ON(iter.size != 0 || iter.data_rate != 0)[PLANE:%d:%s] Can't change DDB during async flip [PLANE:%d:%s] Can't change watermarks during async flip [PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d [PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm [PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d [PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d [PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d !  % $    @ @ @ Q @ @ @ )  '  W z m     O                                 i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU *0@A\s0 @4@i;xT@pJ `0l`   p@r-C]00npn`.0`8 P;z?@] t?- "3FTcw5L]ox#$0$,Jh&2P(0(`)6P)0)C )#2Il//p1E+1Z7F]@8yp8O81  92 R ;q P<  `=  > >y! : 0?RT k        + O Y b skl_watermark.cintel_dbuf_destroy_stateintel_mbus_dbox_updateintel_dbuf_duplicate_stateintel_mbus_joined_pipeintel_sagv_status_openintel_sagv_status_showskl_watermark_ipc_status_openskl_watermark_ipc_status_showadjust_wm_latency.isra.0skl_compute_transition_wm.part.0.isra.0intel_dbuf_slice_size.isra.0skl_ddb_entry_for_slicesintel_dbuf_mbus_join_updateskl_compute_dbuf_slices.isra.0dg2_allowed_dbufsicl_allowed_dbufsadlp_allowed_dbufstgl_allowed_dbufssagv_status.0skl_compute_wm_paramsskl_compute_plane_wm_paramsskl_compute_plane_wmskl_compute_wm_levelsskl_build_plane_wm_singleskl_sagv_disableintel_crtc_can_enable_sagvskl_ddb_get_hw_plane_stateskl_pipe_wm_get_hw_stateskl_wm_get_hw_state_and_sanitizeskl_watermark_ipc_status_writeskl_wm_funcsintel_dbuf_funcsintel_dbuf_mdclk_min_tracker_updateskl_watermark_ipc_status_fopsintel_sagv_status_fopsskl_compute_wm__UNIQUE_ID_import_ns960.LC2.LC18kfreeintel_atomic_get_new_global_obj_stateintel_atomic_get_old_global_obj_stateintel_dmc_wl_get__x86_indirect_thunk_r9intel_dmc_wl_put__x86_return_thunk__warn_printkkmemdup_noprofintel_crtc_for_pipedev_driver_stringsingle_openseq_printfmemset__sw_hweight32__drm_dev_dbg__x86_indirect_thunk_raxintel_fb_is_ccs_modifierintel_format_info_is_yuv_semiplanarintel_fb_is_tiled_modifierintel_plane_pixel_rate__stack_chk_failskl_pcode_request_dev_errintel_mdclk_cdclk_ratiodrm_mode_get_hv_timingintel_plane_disable_noatomicintel_enabled_dbuf_slices_maskintel_has_sagvintel_sagv_pre_plane_updateintel_atomic_get_old_bw_stateintel_atomic_get_new_bw_stateicl_pcode_restrict_qgv_pointsintel_sagv_post_plane_updatesnb_pcode_write_timeoutintel_can_enable_sagvskl_ddb_dbuf_slice_maskskl_plane_wm_levelskl_plane_trans_wmskl_ddb_allocation_overlapsintel_wm_state_verifykmalloc_caches__kmalloc_cache_noprofintel_display_power_get_if_enabledintel_display_power_put_uncheckedskl_watermark_ipc_enabledskl_watermark_ipc_updatekstrtobool_from_userintel_runtime_pm_get_dev_infointel_runtime_pm_put_uncheckedskl_watermark_ipc_initskl_wm_initsnb_pcode_readintel_print_wm_latencyintel_atomic_get_dbuf_stateintel_atomic_get_global_obj_stateintel_dbuf_initintel_atomic_global_obj_initintel_dbuf_state_set_mdclk_cdclk_ratiointel_atomic_lock_global_stateintel_dbuf_mdclk_cdclk_ratio_updateintel_cdclk_is_decreasing_laterintel_dbuf_mbus_pre_ddb_updateintel_dbuf_mbus_post_ddb_updateintel_crtc_wait_for_next_vblankintel_dbuf_pre_plane_updategen9_dbuf_slices_updateintel_dbuf_post_plane_updateskl_watermark_debugfs_registerdebugfs_create_file_fullskl_watermark_max_latencyintel_wm_plane_visibleintel_usecs_to_scanlinesintel_calc_active_pipesintel_atomic_get_crtc_stateintel_atomic_get_bw_stateintel_cdclk_state_set_joined_mbusdrm_atomic_get_plane_state__drm_debugdrm_format_infointel_atomic_serialize_global_stateseq_lseekseq_readsingle_releasek/0K1p2z3  57V8] Xg o58 0 5 0  @K 3R ` /i:;<0/ 3 / #=]1>> * * * 1 * Y *t *{ * * * * * * *8 3` Ge :s 6z > [ : n * :  : /Y ?l @   5 @ A' ?7 @ 8 $ , 5  = BC =D =D& h> @M=/1Q>b31>301Q>]3b1>31>+3_1>3 1,>831>3>1`>l31>3 1/>;3FG / 3  =" "=y"H"8" (" "5"1">#3#CD$1f$>s$3$C:%LF%M% X%=%MJ&LV&M& &=&M#' ('=B'P' '='P' ( @(=Q*WTc*X*Y*Z*I + %+E+ +E- x'-E- -EY. ^.E/ 8/E01?0>_0>0]0^1  1_1\&1`O1Cp2 32 2= 3cg3c3 3E3 3d3 *`*4cD4 pP4=414>53+51O5>^53515>53*61N6>]636 36 36 /6 3s78z7 07 75787 758C{8W8X8 *P8h8fl9 39 09=:1A:>b:>m:3{: /:1:>:>:3:C5;0Y;/d;l;/;0w</<0*=7=/=0(>/L>0> *@> >t? * ? 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