Marvell Armada AP80x System Controller
======================================

The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
7K/8K/931x SoCs. It contains system controllers, which provide several
registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
these system controllers.

For the top level node:
 - compatible: must be: "syscon", "simple-mfd";
 - reg: register area of the AP80x system controller

SYSTEM CONTROLLER 0
===================

Clocks:
-------


The Device Tree node representing the AP806/AP807 system controller
provides a number of clocks:

 - 0: reference clock of CPU cluster 0
 - 1: reference clock of CPU cluster 1
 - 2: fixed PLL at 1200 Mhz
 - 3: MSS clock, derived from the fixed PLL

Required properties:

 - compatible: must be one of:
   * "marvell,ap806-clock"
   * "marvell,ap807-clock"
 - #clock-cells: must be set to 1

Pinctrl:
--------

For common binding part and usage, refer to
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.

Required properties:
- compatible must be "marvell,ap806-pinctrl",

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name	pins	functions
================================================================================
mpp0	0	gpio, sdio(clk), spi0(clk)
mpp1	1	gpio, sdio(cmd), spi0(miso)
mpp2	2	gpio, sdio(d0), spi0(mosi)
mpp3	3	gpio, sdio(d1), spi0(cs0n)
mpp4	4	gpio, sdio(d2), i2c0(sda)
mpp5	5	gpio, sdio(d3), i2c0(sdk)
mpp6	6	gpio, sdio(ds)
mpp7	7	gpio, sdio(d4), uart1(rxd)
mpp8	8	gpio, sdio(d5), uart1(txd)
mpp9	9	gpio, sdio(d6), spi0(cs1n)
mpp10	10	gpio, sdio(d7)
mpp11	11	gpio, uart0(txd)
mpp12	12	gpio, sdio(pw_off), sdio(hw_rst)
mpp13	13	gpio
mpp14	14	gpio
mpp15	15	gpio
mpp16	16	gpio
mpp17	17	gpio
mpp18	18	gpio
mpp19	19	gpio, uart0(rxd), sdio(pw_off)

GPIO:
-----
For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.

Required properties:

- compatible: "marvell,armada-8k-gpio"

- offset: offset address inside the syscon block

Optional properties:

- marvell,pwm-offset: offset address of PWM duration control registers inside
  the syscon block

Example:
ap_syscon: system-controller@6f4000 {
	compatible = "syscon", "simple-mfd";
	reg = <0x6f4000 0x1000>;

	ap_clk: clock {
		compatible = "marvell,ap806-clock";
		#clock-cells = <1>;
	};

	ap_pinctrl: pinctrl {
		compatible = "marvell,ap806-pinctrl";
	};

	ap_gpio: gpio {
		compatible = "marvell,armada-8k-gpio";
		offset = <0x1040>;
		ngpios = <19>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&ap_pinctrl 0 0 19>;
		marvell,pwm-offset = <0x10c0>;
		#pwm-cells = <2>;
		clocks = <&ap_clk 3>;
	};
};

SYSTEM CONTROLLER 1
===================

Cluster clocks:
---------------

Device Tree Clock bindings for cluster clock of Marvell
AP806/AP807. Each cluster contain up to 2 CPUs running at the same
frequency.

Required properties:
 - compatible: must be one of:
   * "marvell,ap806-cpu-clock"
   * "marvell,ap807-cpu-clock"
- #clock-cells : should be set to 1.

- clocks : shall be the input parent clock(s) phandle for the clock
           (one per cluster)

- reg: register range associated with the cluster clocks

ap_syscon1: system-controller@6f8000 {
	compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
	reg = <0x6f8000 0x1000>;

	cpu_clk: clock-cpu@278 {
		compatible = "marvell,ap806-cpu-clock";
		clocks = <&ap_clk 0>, <&ap_clk 1>;
		#clock-cells = <1>;
		reg = <0x278 0xa30>;
	};
};