// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2021-2025 NXP
 *
 * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
 */

/dts-v1/;

#include "s32g3.dtsi"
#include "s32gxxxa-rdb.dtsi"

/ {
	model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
	compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";

	aliases {
		ethernet0 = &gmac0;
		mmc0 = &usdhc0;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* 4GiB RAM */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>,
		      <0x8 0x80000000 0 0x80000000>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&stm0 {
	status = "okay";
};

&stm1 {
	status = "okay";
};

&stm2 {
	status = "okay";
};

&stm3 {
	status = "okay";
};

&stm4 {
	status = "okay";
};

&stm5 {
	status = "okay";
};

&stm6 {
	status = "okay";
};

&stm8 {
	status = "okay";
};

&swt0 {
	status = "okay";
};

&i2c4 {
	current-sensor@40 {
		compatible = "ti,ina231";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};
};

&usdhc0 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
	bus-width = <8>;
	disable-wp;
	status = "okay";
};

&gmac0 {
	clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
	clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
	phy-mode = "rgmii-id";
	phy-handle = <&rgmiiaphy1>;
	status = "okay";
};

&gmac0mdio {
	/* KSZ 9031 on RGMII */
	rgmiiaphy1: ethernet-phy@1 {
		reg = <1>;
	};
};