// SPDX-License-Identifier: GPL-2.0-only or MIT
/*
 * Device Tree Source for AM62L SoC Family
 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "k3-pinctrl.h"

/ {
	model = "Texas Instruments K3 AM62L3 SoC";
	compatible = "ti,am62l3";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};

		scmi: scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0x82004000>;
			shmem = <&scmi_shmem>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
				bootph-all;
			};

			scmi_pds: protocol@11 {
				reg = <0x11>;
				#power-domain-cells = <1>;
				bootph-all;
			};
		};
	};

	a53_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@f0000 {
		compatible = "simple-bus";
		ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */
			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */
			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */
			 <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */
			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */
			 <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
			 <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */
			 <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */
			 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */
			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */
			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */
			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */
			 <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */
			 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */
			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */
			 <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */
			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
			 <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */
			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */

			 /* Wakeup Domain Range */
			 <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
			 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
			 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
			 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
			 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
		#address-cells = <2>;
		#size-cells = <2>;

		cbass_wakeup: bus@a80000 {
			compatible = "simple-bus";
			ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */
				 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */
				 <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */
				 <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */
				 <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */
				 <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */
				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */
			#address-cells = <2>;
			#size-cells = <2>;
		};
	};
};

/* Now include peripherals for each bus segment */
#include "k3-am62l-main.dtsi"
#include "k3-am62l-wakeup.dtsi"