// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (C) 2024 Henry Bell */ /dts-v1/; #include "jh7110-common.dtsi" / { model = "Pine64 Star64"; compatible = "pine64,star64", "starfive,jh7110"; aliases { ethernet1 = &gmac1; }; }; &gmac0 { starfive,tx-use-rgmii-clk; assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; status = "okay"; }; &gmac1 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; starfive,tx-use-rgmii-clk; assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy1: ethernet-phy@1 { reg = <1>; }; }; }; &i2c0 { status = "okay"; }; &mmc0 { cap-mmc-highspeed; cap-mmc-hw-reset; mmc-ddr-1_8v; mmc-hs200-1_8v; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&emmc_vdd>; }; &mmc0_pins { rst-pins { pinmux = ; bias-pull-up; drive-strength = <12>; input-disable; input-schmitt-disable; slew-rate = <0>; }; }; &mmc1 { cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; disable-wp; }; &pcie1 { status = "okay"; }; &phy0 { rx-internal-delay-ps = <1500>; motorcomm,rx-clk-drv-microamp = <2910>; motorcomm,rx-data-drv-microamp = <2910>; motorcomm,tx-clk-adj-enabled; motorcomm,tx-clk-10-inverted; motorcomm,tx-clk-100-inverted; motorcomm,tx-clk-1000-inverted; }; &phy1 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <300>; motorcomm,rx-clk-drv-microamp = <2910>; motorcomm,rx-data-drv-microamp = <2910>; motorcomm,tx-clk-adj-enabled; motorcomm,tx-clk-10-inverted; motorcomm,tx-clk-100-inverted; }; &pwm { status = "okay"; }; &pwmdac { status = "okay"; }; &spi0 { status = "okay"; }; &sysgpio { usb0_pins: usb0-0 { vbus-pins { pinmux = ; bias-disable; input-disable; input-schmitt-disable; slew-rate = <0>; }; }; }; &usb0 { dr_mode = "host"; pinctrl-names = "default"; pinctrl-0 = <&usb0_pins>; status = "okay"; }; &usb_cdns3 { phys = <&usbphy0>, <&pciephy0>; phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; };