// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
 */

#include <dt-bindings/pinctrl/rockchip.h>
#include <arm64/rockchip/rockchip-pinconf.dtsi>

/*
 * This file is auto generated by pin2dts tool, please keep these code
 * by adding changes at end of this file.
 */
&pinctrl {
	clk_out_ethernet {
		/omit-if-no-ref/
		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
			rockchip,pins =
				/* clk_out_ethernet_m1 */
				<2 RK_PC5 2 &pcfg_pull_none>;
		};
	};
	emmc {
		/omit-if-no-ref/
		emmc_rstnout: emmc-rstnout {
			rockchip,pins =
				/* emmc_rstn */
				<1 RK_PA3 2 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		emmc_bus8: emmc-bus8 {
			rockchip,pins =
				/* emmc_d0 */
				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d1 */
				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d2 */
				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d3 */
				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d4 */
				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d5 */
				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d6 */
				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
				/* emmc_d7 */
				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		emmc_clk: emmc-clk {
			rockchip,pins =
				/* emmc_clko */
				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		emmc_cmd: emmc-cmd {
			rockchip,pins =
				/* emmc_cmd */
				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
		};
	};
	fspi {
		/omit-if-no-ref/
		fspi_pins: fspi-pins {
			rockchip,pins =
				/* fspi_clk */
				<1 RK_PA3 3 &pcfg_pull_down>,
				/* fspi_cs0n */
				<0 RK_PD4 3 &pcfg_pull_up>,
				/* fspi_d0 */
				<1 RK_PA0 3 &pcfg_pull_up>,
				/* fspi_d1 */
				<1 RK_PA1 3 &pcfg_pull_up>,
				/* fspi_d2 */
				<0 RK_PD6 3 &pcfg_pull_up>,
				/* fspi_d3 */
				<1 RK_PA2 3 &pcfg_pull_up>;
		};
	};
	i2c0 {
		/omit-if-no-ref/
		i2c0_xfer: i2c0-xfer {
			rockchip,pins =
				/* i2c0_scl */
				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
				/* i2c0_sda */
				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
		};
	};
	i2c2 {
		/omit-if-no-ref/
		i2c2_xfer: i2c2-xfer {
			rockchip,pins =
				/* i2c2_scl */
				<0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
				/* i2c2_sda */
				<0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
		};
	};
	i2c3 {
		/omit-if-no-ref/
		i2c3m0_xfer: i2c3m0-xfer {
			rockchip,pins =
				/* i2c3_scl_m0 */
				<3 RK_PA4 5 &pcfg_pull_none>,
				/* i2c3_sda_m0 */
				<3 RK_PA5 5 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		i2c3m1_xfer: i2c3m1-xfer {
			rockchip,pins =
				/* i2c3_scl_m1 */
				<2 RK_PD4 7 &pcfg_pull_none>,
				/* i2c3_sda_m1 */
				<2 RK_PD5 7 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		i2c3m2_xfer: i2c3m2-xfer {
			rockchip,pins =
				/* i2c3_scl_m2 */
				<1 RK_PD6 3 &pcfg_pull_none>,
				/* i2c3_sda_m2 */
				<1 RK_PD7 3 &pcfg_pull_none>;
		};
	};
	i2s0 {
		i2s0m0_lrck_tx: i2s0m0-lrck-tx {
			rockchip,pins =
			/* i2s0_lrck_tx_m0 */
			<3 RK_PD3 1 &pcfg_pull_none>;
		};
		i2s0m0_lrck_rx: i2s0m0-lrck-rx {
			rockchip,pins =
			/* i2s0_lrck_rx_m0 */
			<3 RK_PD4 1 &pcfg_pull_none>;
		};
		i2s0m0_mclk: i2s0m0-mclk {
			rockchip,pins =
			/* i2s0_mclk_m0 */
			<3 RK_PD2 1 &pcfg_pull_none>;
		};
		i2s0m0_sclk_rx: i2s0m0-sclk-rx {
			rockchip,pins =
			/* i2s0_sclk_rx_m0 */
			<3 RK_PD1 1 &pcfg_pull_none>;
		};
		i2s0m0_sclk_tx: i2s0m0-sclk-tx {
			rockchip,pins =
			/* i2s0_sclk_tx_m0 */
			<3 RK_PD0 1 &pcfg_pull_none>;
		};
		i2s0m0_sdi0: i2s0m0-sdi0 {
			rockchip,pins =
			/* i2s0_sdi0_m0 */
			<3 RK_PD6 1 &pcfg_pull_none>;
		};
		i2s0m0_sdo0: i2s0m0-sdo0 {
			rockchip,pins =
			/* i2s0_sdo0_m0 */
			<3 RK_PD5 1 &pcfg_pull_none>;
		};
		i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
			rockchip,pins =
			/* i2s0_sdo1_sdi3_m0 */
			<3 RK_PD7 1 &pcfg_pull_none>;
		};
		i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
			rockchip,pins =
			/* i2s0_sdo2_sdi2_m0 */
			<4 RK_PA0 1 &pcfg_pull_none>;
		};
		i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
			rockchip,pins =
			/* i2s0_sdo3_sdi1_m0 */
			<4 RK_PA1 1 &pcfg_pull_none>;
		};
		i2s0m1_lrck_tx: i2s0m1-lrck-tx {
			rockchip,pins =
			/* i2s0_lrck_tx_m1 */
			<3 RK_PA5 3 &pcfg_pull_none>;
		};
		i2s0m1_lrck_rx: i2s0m1-lrck-rx {
			rockchip,pins =
			/* i2s0_lrck_rx_m1 */
			<3 RK_PB2 3 &pcfg_pull_none>;
		};
		i2s0m1_mclk: i2s0m1-mclk {
			rockchip,pins =
			/* i2s0_mclk_m1 */
			<3 RK_PB0 3 &pcfg_pull_none>;
		};
		i2s0m1_sclk_rx: i2s0m1-sclk-rx {
			rockchip,pins =
			/* i2s0_sclk_rx_m1 */
			<3 RK_PB1 3 &pcfg_pull_none>;
		};
		i2s0m1_sclk_tx: i2s0m1-sclk-tx {
			rockchip,pins =
			/* i2s0_sclk_tx_m1 */
			<3 RK_PA4 3 &pcfg_pull_none>;
		};
		i2s0m1_sdi0: i2s0m1-sdi0 {
			rockchip,pins =
			/* i2s0_sdi0_m1 */
			<3 RK_PA7 3 &pcfg_pull_none>;
		};
		i2s0m1_sdo0: i2s0m1-sdo0 {
			rockchip,pins =
			/* i2s0_sdo0_m1 */
			<3 RK_PA6 3 &pcfg_pull_none>;
		};
		i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
			rockchip,pins =
			/* i2s0_sdo1_sdi3_m1 */
			<3 RK_PB3 3 &pcfg_pull_none>;
		};
		i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
			rockchip,pins =
			/* i2s0_sdo2_sdi2_m1 */
			<3 RK_PB4 3 &pcfg_pull_none>;
		};
		i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
			rockchip,pins =
			/* i2s0_sdo3_sdi1_m1 */
			<3 RK_PB5 3 &pcfg_pull_none>;
		};
	};
	pwm0 {
		/omit-if-no-ref/
		pwm0m0_pins: pwm0m0-pins {
			rockchip,pins =
				/* pwm0_pin_m0 */
				<0 RK_PB6 3 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm0m1_pins: pwm0m1-pins {
			rockchip,pins =
				/* pwm0_pin_m1 */
				<2 RK_PB3 5 &pcfg_pull_none>;
		};
	};
	pwm1 {
		/omit-if-no-ref/
		pwm1m0_pins: pwm1m0-pins {
			rockchip,pins =
				/* pwm1_pin_m0 */
				<0 RK_PB7 3 &pcfg_pull_none>;
		};
	};
	pwm2 {
		/omit-if-no-ref/
		pwm2m0_pins: pwm2m0-pins {
			rockchip,pins =
				/* pwm2_pin_m0 */
				<0 RK_PC0 3 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm2m1_pins: pwm2m1-pins {
			rockchip,pins =
				/* pwm2_pin_m1 */
				<2 RK_PB1 5 &pcfg_pull_none>;
		};
	};
	pwm3 {
		/omit-if-no-ref/
		pwm3m0_pins: pwm3m0-pins {
			rockchip,pins =
				/* pwm3_pin_m0 */
				<0 RK_PC1 3 &pcfg_pull_none>;
		};
	};
	pwm4 {
		/omit-if-no-ref/
		pwm4m0_pins: pwm4m0-pins {
			rockchip,pins =
				/* pwm4_pin_m0 */
				<0 RK_PC2 3 &pcfg_pull_none>;
		};
	};
	pwm5 {
		/omit-if-no-ref/
		pwm5m0_pins: pwm5m0-pins {
			rockchip,pins =
				/* pwm5_pin_m0 */
				<0 RK_PC3 3 &pcfg_pull_none>;
		};
	};
	pwm6 {
		/omit-if-no-ref/
		pwm6m0_pins: pwm6m0-pins {
			rockchip,pins =
				/* pwm6_pin_m0 */
				<0 RK_PB2 3 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm6m1_pins: pwm6m1-pins {
			rockchip,pins =
				/* pwm6_pin_m1 */
				<2 RK_PD4 5 &pcfg_pull_none>;
		};
	};
	pwm7 {
		/omit-if-no-ref/
		pwm7m0_pins: pwm7m0-pins {
			rockchip,pins =
				/* pwm7_pin_m0 */
				<0 RK_PB1 3 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm7m1_pins: pwm7m1-pins {
			rockchip,pins =
				/* pwm7_pin_m1 */
				<3 RK_PA0 5 &pcfg_pull_none>;
		};
	};
	pwm8 {
		/omit-if-no-ref/
		pwm8m0_pins: pwm8m0-pins {
			rockchip,pins =
				/* pwm8_pin_m0 */
				<3 RK_PA4 6 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm8m1_pins: pwm8m1-pins {
			rockchip,pins =
				/* pwm8_pin_m1 */
				<2 RK_PD7 5 &pcfg_pull_none>;
		};
	};
	pwm9 {
		/omit-if-no-ref/
		pwm9m0_pins: pwm9m0-pins {
			rockchip,pins =
				/* pwm9_pin_m0 */
				<3 RK_PA5 6 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm9m1_pins: pwm9m1-pins {
			rockchip,pins =
				/* pwm9_pin_m1 */
				<2 RK_PD6 5 &pcfg_pull_none>;
		};
	};
	pwm10 {
		/omit-if-no-ref/
		pwm10m0_pins: pwm10m0-pins {
			rockchip,pins =
				/* pwm10_pin_m0 */
				<3 RK_PA6 6 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm10m1_pins: pwm10m1-pins {
			rockchip,pins =
				/* pwm10_pin_m1 */
				<2 RK_PD5 5 &pcfg_pull_none>;
		};
	};
	pwm11 {
		/omit-if-no-ref/
		pwm11m0_pins: pwm11m0-pins {
			rockchip,pins =
				/* pwm11_pin_m0 */
				<3 RK_PA7 6 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		pwm11m1_pins: pwm11m1-pins {
			rockchip,pins =
				/* pwm11_pin_m1 */
				<3 RK_PA1 5 &pcfg_pull_none>;
		};
	};
	rgmii {
		/omit-if-no-ref/
		rgmiim1_miim: rgmiim1-miim {
			rockchip,pins =
				/* rgmii_mdc_m1 */
				<2 RK_PC2 2 &pcfg_pull_none>,
				/* rgmii_mdio_m1 */
				<2 RK_PC1 2 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		rgmiim1_rxer: rgmiim1-rxer {
			rockchip,pins =
				/* rgmii_rxer_m1 */
				<2 RK_PC0 2 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		rgmiim1_bus2: rgmiim1-bus2 {
			rockchip,pins =
				/* rgmii_rxd0_m1 */
				<2 RK_PB5 2 &pcfg_pull_none>,
				/* rgmii_rxd1_m1 */
				<2 RK_PB6 2 &pcfg_pull_none>,
				/* rgmii_rxdv_m1 */
				<2 RK_PB4 2 &pcfg_pull_none>,
				/* rgmii_txd0_m1 */
				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
				/* rgmii_txd1_m1 */
				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
				/* rgmii_txen_m1 */
				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
		};
		/omit-if-no-ref/
		rgmiim1_bus4: rgmiim1-bus4 {
			rockchip,pins =
				/* rgmii_rxclk_m1 */
				<2 RK_PD3 2 &pcfg_pull_none>,
				/* rgmii_rxd2_m1 */
				<2 RK_PC7 2 &pcfg_pull_none>,
				/* rgmii_rxd3_m1 */
				<2 RK_PD0 2 &pcfg_pull_none>,
				/* rgmii_txclk_m1 */
				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
				/* rgmii_txd2_m1 */
				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
				/* rgmii_txd3_m1 */
				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
		};
		/omit-if-no-ref/
		rgmiim1_mclkinout: rgmiim1-mclkinout {
			rockchip,pins =
				/* rgmii_clk_m1 */
				<2 RK_PB7 2 &pcfg_pull_none>;
		};
	};
	sdmmc0 {
		/omit-if-no-ref/
		sdmmc0_bus4: sdmmc0-bus4 {
			rockchip,pins =
				/* sdmmc0_d0 */
				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d1 */
				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d2 */
				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d3 */
				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc0_clk: sdmmc0-clk {
			rockchip,pins =
				/* sdmmc0_clk */
				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc0_cmd: sdmmc0-cmd {
			rockchip,pins =
				/* sdmmc0_cmd */
				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc0_det: sdmmc0-det {
			rockchip,pins =
				<0 RK_PA3 1 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		sdmmc0_pwr: sdmmc0-pwr {
			rockchip,pins =
				<0 RK_PC0 1 &pcfg_pull_none>;
		};
	};
	sdmmc1 {
		/omit-if-no-ref/
		sdmmc1_bus4: sdmmc1-bus4 {
			rockchip,pins =
				/* sdmmc1_d0 */
				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d1 */
				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d2 */
				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d3 */
				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc1_clk: sdmmc1-clk {
			rockchip,pins =
				/* sdmmc1_clk */
				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc1_cmd: sdmmc1-cmd {
			rockchip,pins =
				/* sdmmc1_cmd */
				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
		};
		/omit-if-no-ref/
		sdmmc1_det: sdmmc1-det {
			rockchip,pins =
				<1 RK_PD0 2 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		sdmmc1_pwr: sdmmc1-pwr {
			rockchip,pins =
				<1 RK_PD1 2 &pcfg_pull_none>;
		};
	};
	uart0 {
		/omit-if-no-ref/
		uart0_xfer: uart0-xfer {
			rockchip,pins =
				/* uart0_rx */
				<1 RK_PC2 1 &pcfg_pull_up>,
				/* uart0_tx */
				<1 RK_PC3 1 &pcfg_pull_up>;
		};
		/omit-if-no-ref/
		uart0_ctsn: uart0-ctsn {
			rockchip,pins =
				<1 RK_PC1 1 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		uart0_rtsn: uart0-rtsn {
			rockchip,pins =
				<1 RK_PC0 1 &pcfg_pull_none>;
		};
		/omit-if-no-ref/
		uart0_rtsn_gpio: uart0-rts-pin {
			rockchip,pins =
				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
	uart1 {
		/omit-if-no-ref/
		uart1m0_xfer: uart1m0-xfer {
			rockchip,pins =
				/* uart1_rx_m0 */
				<0 RK_PB7 2 &pcfg_pull_up>,
				/* uart1_tx_m0 */
				<0 RK_PB6 2 &pcfg_pull_up>;
		};
	};
	uart2 {
		/omit-if-no-ref/
		uart2m1_xfer: uart2m1-xfer {
			rockchip,pins =
				/* uart2_rx_m1 */
				<3 RK_PA3 1 &pcfg_pull_up>,
				/* uart2_tx_m1 */
				<3 RK_PA2 1 &pcfg_pull_up>;
		};
	};
	uart3 {
		/omit-if-no-ref/
		uart3m0_xfer: uart3m0-xfer {
			rockchip,pins =
				/* uart3_rx_m0 */
				<3 RK_PC7 4 &pcfg_pull_up>,
				/* uart3_tx_m0 */
				<3 RK_PC6 4 &pcfg_pull_up>;
		};
		/omit-if-no-ref/
		uart3m2_xfer: uart3m2-xfer {
			rockchip,pins =
				/* uart3_rx_m2 */
				<3 RK_PA1 4 &pcfg_pull_up>,
				/* uart3_tx_m2 */
				<3 RK_PA0 4 &pcfg_pull_up>;
		};
	};
	uart4 {
		/omit-if-no-ref/
		uart4m0_xfer: uart4m0-xfer {
			rockchip,pins =
				/* uart4_rx_m0 */
				<3 RK_PA5 4 &pcfg_pull_up>,
				/* uart4_tx_m0 */
				<3 RK_PA4 4 &pcfg_pull_up>;
		};
		/omit-if-no-ref/
		uart4m2_xfer: uart4m2-xfer {
			rockchip,pins =
				/* uart4_rx_m2 */
				<1 RK_PD4 3 &pcfg_pull_up>,
				/* uart4_tx_m2 */
				<1 RK_PD5 3 &pcfg_pull_up>;
		};
	};
	uart5 {
		/omit-if-no-ref/
		uart5m0_xfer: uart5m0-xfer {
			rockchip,pins =
				/* uart5_rx_m0 */
				<3 RK_PA7 4 &pcfg_pull_up>,
				/* uart5_tx_m0 */
				<3 RK_PA6 4 &pcfg_pull_up>;
		};
		/omit-if-no-ref/
		uart5m2_xfer: uart5m2-xfer {
			rockchip,pins =
				/* uart5_rx_m2 */
				<2 RK_PA1 3 &pcfg_pull_up>,
				/* uart5_tx_m2 */
				<2 RK_PA0 3 &pcfg_pull_up>;
		};
	};
};
