// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Copyright (c) 2017-2019 Andreas Färber
 */

/memreserve/ 0x00000000 0x0000a800; /* boot code */
/memreserve/ 0x0000a800 0x000f5800;
/memreserve/ 0x17fff000 0x00001000;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/realtek,rtd1195.h>

/ {
	compatible = "realtek,rtd1195";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clock-frequency = <1000000000>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rpc_comm: rpc@b000 {
			reg = <0x0000b000 0x1000>;
		};

		audio@1b00000 {
			reg = <0x01b00000 0x400000>;
		};

		rpc_ringbuf: rpc@1ffe000 {
			reg = <0x01ffe000 0x4000>;
		};

		secure@10000000 {
			reg = <0x10000000 0x100000>;
			no-map;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <27000000>;
	};

	osc27M: osc {
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
		#clock-cells = <0>;
		clock-output-names = "osc27M";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x0000a800>,
			 <0x18000000 0x18000000 0x00070000>,
			 <0x18100000 0x18100000 0x01000000>,
			 <0x80000000 0x80000000 0x80000000>;

		rbus: bus@18000000 {
			compatible = "simple-bus";
			reg = <0x18000000 0x70000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x18000000 0x70000>;

			crt: syscon@0 {
				compatible = "syscon", "simple-mfd";
				reg = <0x0 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x0 0x1000>;
			};

			iso: syscon@7000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x7000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x7000 0x1000>;
			};

			sb2: syscon@1a000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1a000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1a000 0x1000>;
			};

			misc: syscon@1b000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1b000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1b000 0x1000>;
			};

			scpu_wrapper: syscon@1d000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1d000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1d000 0x1000>;
			};
		};

		gic: interrupt-controller@ff011000 {
			compatible = "arm,cortex-a7-gic";
			reg = <0xff011000 0x1000>,
			      <0xff012000 0x2000>,
			      <0xff014000 0x2000>,
			      <0xff016000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};

&crt {
	reset1: reset-controller@0 {
		compatible = "snps,dw-low-reset";
		reg = <0x0 0x4>;
		#reset-cells = <1>;
	};

	reset2: reset-controller@4 {
		compatible = "snps,dw-low-reset";
		reg = <0x4 0x4>;
		#reset-cells = <1>;
	};

	reset3: reset-controller@8 {
		compatible = "snps,dw-low-reset";
		reg = <0x8 0x4>;
		#reset-cells = <1>;
	};
};

&iso {
	iso_reset: reset-controller@88 {
		compatible = "snps,dw-low-reset";
		reg = <0x88 0x4>;
		#reset-cells = <1>;
	};

	wdt: watchdog@680 {
		compatible = "realtek,rtd1295-watchdog";
		reg = <0x680 0x100>;
		clocks = <&osc27M>;
	};

	uart0: serial@800 {
		compatible = "snps,dw-apb-uart";
		reg = <0x800 0x400>;
		reg-shift = <2>;
		reg-io-width = <4>;
		resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
		clock-frequency = <27000000>;
		status = "disabled";
	};
};

&misc {
	uart1: serial@200 {
		compatible = "snps,dw-apb-uart";
		reg = <0x200 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		resets = <&reset2 RTD1195_RSTN_UR1>;
		clock-frequency = <27000000>;
		status = "disabled";
	};
};
