// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"

/ {
	compatible = "brcm,bcm2836";

	soc {
		ranges = <0x7e000000 0x3f000000 0x1000000>,
			 <0x40000000 0x40000000 0x00001000>;
		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;

		local_intc: interrupt-controller@40000000 {
			compatible = "brcm,bcm2836-l1-intc";
			reg = <0x40000000 0x100>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&local_intc>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupt-parent = <&local_intc>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&local_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
		always-on;
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "brcm,bcm2836-smp";

		/* Source for d/i-cache-line-size and d/i-cache-sets
		 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
		 * /About-the-L1-memory-system?lang=en
		 *
		 * Source for d/i-cache-size
		 * https://forums.raspberrypi.com/viewtopic.php?t=98428
		 */

		v7_cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			clock-frequency = <800000000>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <32>;
			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
			next-level-cache = <&l2>;
		};

		v7_cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			clock-frequency = <800000000>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <32>;
			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
			next-level-cache = <&l2>;
		};

		v7_cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			clock-frequency = <800000000>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <32>;
			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
			next-level-cache = <&l2>;
		};

		v7_cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
			clock-frequency = <800000000>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <32>;
			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
			next-level-cache = <&l2>;
		};

		/* Source for cache-line-size + cache-sets
		 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
		 * /About-the-L2-Memory-system?lang=en
		 * Source for cache-size
		 * https://forums.raspberrypi.com/viewtopic.php?t=98428
		 */
		l2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
			cache-level = <2>;
		};
	};
};

/* Make the BCM2835-style global interrupt controller be a child of the
 * CPU-local interrupt controller.
 */
&intc {
	compatible = "brcm,bcm2836-armctrl-ic";
	reg = <0x7e00b200 0x200>;
	interrupt-parent = <&local_intc>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};

&cpu_thermal {
	coefficients = <(-538)	407000>;
};

/* enable thermal sensor with the correct compatible property set */
&thermal {
	compatible = "brcm,bcm2836-thermal";
	status = "okay";
};
