trial-ttcn3_bts_tests:sysmo 101

Took 59 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	46 sec
TC_chan_act_a52	1	45 sec
TC_chan_act_a53	39	46 sec
TC_chan_act_stress	1	24 sec
TC_conn_fail_crit Regression	3	48 sec
TC_deact_sacch	39	35 sec
TC_encr_cmd_a51	1	46 sec
TC_encr_cmd_a52	1	45 sec
TC_encr_cmd_a53	39	46 sec
TC_ho_rach	39	38 sec
TC_meas_res_sign_sdcch4	39	45 sec
TC_meas_res_sign_sdcch8	39	46 sec
TC_meas_res_sign_tchf	39	46 sec
TC_meas_res_sign_tchh	39	46 sec
TC_meas_res_sign_tchh_toa256	39	46 sec
TC_meas_res_speech_tchf	13	33 sec
TC_meas_res_speech_tchf_facch	10	45 sec
TC_meas_res_speech_tchh	13	46 sec
TC_meas_res_speech_tchh_facch	10	45 sec
TC_meas_res_speech_tchh_toa256	12	45 sec
TC_ms_pwr_ctrl_constant	14	45 sec
TC_ms_pwr_ctrl_pf_ewma	13	45 sec
TC_paging_imsi_200percent	1	46 sec
TC_paging_imsi_80percent	1	46 sec
TC_paging_tmsi_200percent	1	46 sec
TC_paging_tmsi_80percent	1	46 sec
TC_rach_load_count	39	2 sec
TC_rach_load_idle_below_thresh	39	2 sec
TC_rach_load_idle_thresh0	39	2 sec
TC_rach_max_ta	39	26 sec
TC_rll_est_ind	1	37 sec
TC_rll_est_req_ACCH_3	39	46 sec
TC_rll_est_req_DCCH_3	1	45 sec
TC_rll_rel_ind_ACCH_0	39	46 sec
TC_rll_rel_ind_ACCH_3	39	45 sec
TC_rll_rel_ind_DCCH_0	1	46 sec
TC_rll_rel_ind_DCCH_3	1	45 sec
TC_rll_rel_req	39	44 sec
TC_rll_unit_data_ind_ACCH	1	46 sec
TC_rll_unit_data_ind_DCCH	1	45 sec
TC_rll_unit_data_req_ACCH	39	46 sec
TC_rll_unit_data_req_DCCH	1	45 sec
TC_rsl_bs_pwr_static_ass	1	38 sec
TC_rsl_bs_pwr_static_power_control Regression	1	45 sec
TC_rsl_chan_initial_ms_pwr	39	36 sec
TC_rsl_chan_initial_ta	39	44 sec
TC_rsl_modify_encr	39	46 sec
TC_rsl_ms_pwr_ctrl	1	45 sec
TC_rsl_ms_pwr_dyn_active	39	25 sec
TC_rsl_ms_pwr_dyn_active2	39	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	39	15 sec
TC_rsl_ms_pwr_dyn_down	39	15 sec
TC_rsl_ms_pwr_dyn_max	39	16 sec
TC_rsl_ms_pwr_dyn_up	39	15 sec
TC_sacch_chan_act	39	36 sec
TC_sacch_chan_act_ho_async	39	25 sec
TC_sacch_chan_act_ho_sync	39	16 sec
TC_sacch_filling	39	38 sec
TC_sacch_info_mod	39	38 sec
TC_sacch_multi	39	28 sec
TC_sacch_multi_chg	39	25 sec
TC_si_sched_1 Regression	1	46 sec
TC_si_sched_13	1	46 sec
TC_si_sched_13_2bis_2ter_2quater	1	46 sec
TC_si_sched_2bis Regression	1	46 sec
TC_si_sched_2quater Regression	1	46 sec
TC_si_sched_2ter Regression	1	46 sec
TC_si_sched_2ter_2bis	1	46 sec
TC_si_sched_default Regression	1	37 sec
TC_speech_no_rtp_tchf	1	46 sec
TC_speech_no_rtp_tchh	1	45 sec
TC_tch_sign_l2_fill_frame	39	33 sec
TC_tch_sign_l2_fill_frame_dtxd	39	45 sec
TC_tx_power_ramp_adm_state_change	39	20 sec
TC_tx_power_start_ramp_down_bcch	39	28 sec
TC_tx_power_start_ramp_up_bcch	39	45 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	76+7	0	25-7	101	59 min