All Tests
| Name | Age | Duration | |
|---|---|---|---|
| TC_cbc_sdcch4_load_idle | 0 | 15 sec | |
| TC_cbc_sdcch4_load_overload | 0 | 17 sec | |
| TC_cbc_sdcch8_load_idle | 0 | 16 sec | |
| TC_cbc_sdcch8_load_overload | 0 | 18 sec | |
| TC_cbch_load_idle_no_cbch | 0 | 11 sec | |
| TC_etws_p1ro | 0 | 16 sec | |
| TC_etws_p1ro_end | 0 | 16 sec | |
| TC_etws_pcu | 0 | 4.8 sec | |
| TC_sms_cb_cmd_sdcch4_1block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch4_2block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch4_3block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch4_4block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch4_default_and_normal | 0 | 17 sec | |
| TC_sms_cb_cmd_sdcch4_default_only | 0 | 16 sec | |
| TC_sms_cb_cmd_sdcch4_default_then_null | 0 | 26 sec | |
| TC_sms_cb_cmd_sdcch4_multi | 0 | 20 sec | |
| TC_sms_cb_cmd_sdcch4_schedule | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch8_1block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch8_2block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch8_3block | 0 | 14 sec | |
| TC_sms_cb_cmd_sdcch8_4block | 0 | 13 sec | |
| TC_sms_cb_cmd_sdcch8_default_and_normal | 0 | 17 sec | |
| TC_sms_cb_cmd_sdcch8_default_only | 0 | 16 sec | |
| TC_sms_cb_cmd_sdcch8_multi Regression | 1 | 20 sec | |
| TC_sms_cb_cmd_sdcch8_schedule | 0 | 13 sec |