Timing Advance mismatch: expected 2, but received 0 PCU_Tests.ttcn:7640 PCU_Tests control part PCU_Tests.ttcn:572 TC_ta_ul_ack_nack_first_block testcase Timing Advance value doesn't match PCU_Tests.ttcn:7641 PCU_Tests control part PCU_Tests.ttcn:607 TC_ta_idle_dl_tbf_ass testcase Failed to match Timing Advance Index for #0 PCU_Tests.ttcn:7642 PCU_Tests control part PCU_Tests.ttcn:807 TC_ta_ptcch_ul_multi_tbf testcase Failed to match DL DATA: { ctrl := { mac_hdr := { payload_type := MAC_PT_RLCMAC_NO_OPT (1), rrbp := RRBP_Nplus13_mod_2715648 (0), rrbp_valid := false, usf := 7 }, opt := omit, payload := { msg_type := PACKET_DL_DUMMY_CTRL (37), u := { dl_dummy := { page_mode := PAGE_MODE_NORMAL (0), persistence_levels_present := '0'B, persistence_levels := omit } } } } } vs ({ data := { cs := ?, mac_hdr := { mac_hdr := { payload_type := MAC_PT_RLC_DATA (0), rrbp := ?, rrbp_valid := ?, usf := ? }, hdr_ext := ? }, blocks := ? } }, { data_egprs := { mcs := ?, mac_hdr := ?, fbi := ?, e := ?, blocks := ? } }) PCU_Tests.ttcn:7676 PCU_Tests control part PCU_Tests.ttcn:3336 TC_dl_llc_sapi_priority testcase Expected 8 PDCH slots allocated but got 4 PCU_Tests.ttcn:7717 PCU_Tests control part PCU_Tests.ttcn:3442 TC_dl_multislot_tbf_ms_class_from_sgsn testcase Expected 1 PDCH slots allocated but got 4 PCU_Tests.ttcn:7718 PCU_Tests control part PCU_Tests.ttcn:3512 TC_dl_multislot_tbf_ms_class_unknown testcase "Unexpected PKT UL ASS after T3168 timeout: { bts_nr := 0, raw := { sapi := PCU_IF_SAPI_PDTCH (5), len := 23, data := '4F28400000002301E6CE8800082B2B2B2B2B2B2B2B2B2B'O, fn := 3406, arfcn := 871, trx_nr := 0, ts_nr := 7, block_nr := 6, rssi := 0, ber10k := 0, ta_offs_qbits := 0, lqual_cb := 0 }, dl_block := { ctrl := { mac_hdr := { payload_type := MAC_PT_RLCMAC_NO_OPT (1), rrbp := RRBP_Nplus13_mod_2715648 (0), rrbp_valid := true, usf := 7 }, opt := omit, payload := { msg_type := PACKET_UL_ASSIGNMENT (10), u := { ul_assignment := { page_mode := PAGE_MODE_NORMAL (0), persistence_levels_present := '0'B, persistence_levels := omit, identity := { tlli := { presence := '10'B, tlli := '00000001'O } }, is_egprs := '0'B, gprs := { ch_coding_cmd := CH_CODING_CS1 (0), tlli_block_chan_coding := '1'B, pkt_ta := { val_present := '1'B, val := 0, idx_present := '0'B, idx := omit, timeslot_nr := omit }, freq_par_present := '1'B, freq_par := { tsc := 7, presence := '00'B, arfcn := 871, indirect := omit, direct1 := omit, direct2 := omit }, alloc_present := '01'B, dyn_block_alloc := { extd_dyn_alloc := '0'B, p0_present := '0'B, p0 := omit, pr_mode := omit, usf_granularity := '0'B, ul_tfi_ass_present := '1'B, ul_tfi_assignment := 0, reserved := '0'B, tbf_starting_time_present := '0'B, tbf_starting_time := omit, ts_allocation := { presence := '0'B, ts := { { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '0'B, usf_tn := omit }, { presence := '1'B, usf_tn := 0 } }, ts_with_pwr := omit } }, sgl_block_alloc := omit }, egprs := omit } } } } } }" PCU_Tests.ttcn:7722 PCU_Tests control part PCU_Tests.ttcn:3764 TC_ul_tbf_reestablish_with_pkt_resource_req_t3168 testcase