Started by upstream project "master-osmo-ccid-firmware" build number 2,4072407master-osmo-ccid-firmwarejob/master-osmo-ccid-firmware/000065736657361.0583858380715745836583644347ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/master7ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/master3827db9d29ae7c0a2a3c5effe727295f2d607bce3b64db9d29ae7c0a2a3c5effe727295f2d607bce3b64refs/remotes/origin/masterdb9d29ae7c0a2a3c5effe727295f2d607bce3b64db9d29ae7c0a2a3c5effe727295f2d607bce3b64refs/remotes/origin/master7ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/masterhttps://gerrit.osmocom.org/osmo-ccid-firmwarehttps://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/4434/artifacthttps://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/changeshttps://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/4434/https://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/4434/testReportfalse#443465736625271octsim_osmo-ccid-firmware #44344434falsefalse443474737FAILURE1774825754327https://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/4434/- sysmoOCTSIM/libosmo_emb.hsysmoOCTSIM/libosmo_emb.c2e49ae297ea4669f5d8359165845101ef4d40b441774546264000https://jenkins.osmocom.org/jenkins/user/ewildewildewild@sysmocom.defirmware: add tear-free 64bit load/store helpers for jiffies
On Cortex-M4 a 64bit load may compile to two separate LDR
instructions which can lead to torn reads due to interrupts.
LDRD/STRD are restartable, they either complete or restart from
scratch, so the result is always consistent. The only "downside" is the
required alignment, which is fine.
Change-Id: I729c0fdfb5b228b03c2df1cf098743100b1ea625
2026-03-26 18:31:04 +01002e49ae297ea4669f5d8359165845101ef4d40b44firmware: add tear-free 64bit load/store helpers for jiffiesaddsysmoOCTSIM/libosmo_emb.heditsysmoOCTSIM/libosmo_emb.c
- .checkpatch.confccid_common/iso7816_fsm.cccid_common/ccid_slot_fsm.csysmoOCTSIM/main.cccid_common/cuart.hccid_host/Makefileccid_host/libosmo_emb.cccid_common/cuart.cccid_host/libosmo_emb.h7ae9a65c7fadf3d9d89370761c7352cbcac83a001774641259000https://jenkins.osmocom.org/jenkins/user/ewildewildewild@sysmocom.defirmware: replace libosmocore fsm timers
Concurrent access from main loop and the different uart irqs was not
going well and caused crashes. The libosmocore fsm does still allocate
one internal timer, but it is not used by the firmware, so libosmocore
will not touch the rbtree.
Additionally ignore checkpatch jiffies complaints because we're trying
to do firmware here.
Closes: SYS#7877
Change-Id: Id2bd67b3946bb451008965f0b68b4a919f4d10bd
2026-03-27 20:54:19 +01007ae9a65c7fadf3d9d89370761c7352cbcac83a00firmware: replace libosmocore fsm timerseditccid_common/ccid_slot_fsm.caddccid_host/libosmo_emb.cedit.checkpatch.confeditccid_common/iso7816_fsm.ceditccid_host/Makefileaddccid_host/libosmo_emb.heditsysmoOCTSIM/main.ceditccid_common/cuart.ceditccid_common/cuart.h
githttps://jenkins.osmocom.org/jenkins/user/ewildewildewildStarted by upstream project "octsim_osmo-ccid-firmware" build number 4,4344434octsim_osmo-ccid-firmwarejob/octsim_osmo-ccid-firmware/000064785647851.000044347ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/master7ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/master3827db9d29ae7c0a2a3c5effe727295f2d607bce3b64db9d29ae7c0a2a3c5effe727295f2d607bce3b64refs/remotes/origin/masterdb9d29ae7c0a2a3c5effe727295f2d607bce3b64db9d29ae7c0a2a3c5effe727295f2d607bce3b64refs/remotes/origin/master7ae9a65c7fadf3d9d89370761c7352cbcac83a007ae9a65c7fadf3d9d89370761c7352cbcac83a00origin/masterhttps://gerrit.osmocom.org/osmo-ccid-firmwarefalse#443464785623465octsim_osmo-ccid-firmware ยป octsimtest #44344434falsefalse443474738FAILURE1774825754327https://jenkins.osmocom.org/jenkins/view/gerrit/job/octsim_osmo-ccid-firmware/label=octsimtest/4434/octsimtest- sysmoOCTSIM/libosmo_emb.hsysmoOCTSIM/libosmo_emb.c2e49ae297ea4669f5d8359165845101ef4d40b441774546264000https://jenkins.osmocom.org/jenkins/user/ewildewildewild@sysmocom.defirmware: add tear-free 64bit load/store helpers for jiffies
On Cortex-M4 a 64bit load may compile to two separate LDR
instructions which can lead to torn reads due to interrupts.
LDRD/STRD are restartable, they either complete or restart from
scratch, so the result is always consistent. The only "downside" is the
required alignment, which is fine.
Change-Id: I729c0fdfb5b228b03c2df1cf098743100b1ea625
2026-03-26 18:31:04 +01002e49ae297ea4669f5d8359165845101ef4d40b44firmware: add tear-free 64bit load/store helpers for jiffieseditsysmoOCTSIM/libosmo_emb.caddsysmoOCTSIM/libosmo_emb.h
- .checkpatch.confccid_common/iso7816_fsm.cccid_common/ccid_slot_fsm.csysmoOCTSIM/main.cccid_common/cuart.hccid_host/Makefileccid_host/libosmo_emb.cccid_common/cuart.cccid_host/libosmo_emb.h7ae9a65c7fadf3d9d89370761c7352cbcac83a001774641259000https://jenkins.osmocom.org/jenkins/user/ewildewildewild@sysmocom.defirmware: replace libosmocore fsm timers
Concurrent access from main loop and the different uart irqs was not
going well and caused crashes. The libosmocore fsm does still allocate
one internal timer, but it is not used by the firmware, so libosmocore
will not touch the rbtree.
Additionally ignore checkpatch jiffies complaints because we're trying
to do firmware here.
Closes: SYS#7877
Change-Id: Id2bd67b3946bb451008965f0b68b4a919f4d10bd
2026-03-27 20:54:19 +01007ae9a65c7fadf3d9d89370761c7352cbcac83a00firmware: replace libosmocore fsm timerseditccid_common/ccid_slot_fsm.ceditccid_host/Makefileaddccid_host/libosmo_emb.haddccid_host/libosmo_emb.ceditsysmoOCTSIM/main.cedit.checkpatch.confeditccid_common/cuart.heditccid_common/cuart.ceditccid_common/iso7816_fsm.c
githttps://jenkins.osmocom.org/jenkins/user/ewildewild