trial-ttcn3_bts_tests:sysmo 101

Took 49 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51 Regression	1	35 sec
TC_chan_act_a52	1	28 sec
TC_chan_act_a53	33	23 sec
TC_chan_act_stress	1	24 sec
TC_deact_sacch	33	28 sec
TC_encr_cmd_a52	1	29 sec
TC_encr_cmd_a53	33	23 sec
TC_ho_rach	33	32 sec
TC_meas_res_sign_sdcch4	33	39 sec
TC_meas_res_sign_sdcch8	33	40 sec
TC_meas_res_sign_tchf	33	40 sec
TC_meas_res_sign_tchh	33	39 sec
TC_meas_res_sign_tchh_toa256	33	35 sec
TC_meas_res_speech_tchf	7	28 sec
TC_meas_res_speech_tchf_facch	4	39 sec
TC_meas_res_speech_tchh	7	39 sec
TC_meas_res_speech_tchh_facch	4	40 sec
TC_meas_res_speech_tchh_toa256	6	39 sec
TC_ms_pwr_ctrl_constant	8	26 sec
TC_ms_pwr_ctrl_pf_ewma	7	18 sec
TC_paging_tmsi_200percent	1	52 sec
TC_paging_tmsi_80percent	1	46 sec
TC_rach_load_count	33	2 sec
TC_rach_load_idle_below_thresh	33	2 sec
TC_rach_load_idle_thresh0	33	2 sec
TC_rach_max_ta	33	25 sec
TC_rll_est_ind Regression	1	28 sec
TC_rll_est_req_ACCH_3	33	23 sec
TC_rll_rel_ind_ACCH_0	33	24 sec
TC_rll_rel_ind_ACCH_3	33	32 sec
TC_rll_rel_req	33	44 sec
TC_rll_unit_data_req_ACCH	33	39 sec
TC_rll_unit_data_req_DCCH	1	37 sec
TC_rsl_chan_initial_ms_pwr	33	20 sec
TC_rsl_chan_initial_ta	33	21 sec
TC_rsl_modify_encr	33	24 sec
TC_rsl_ms_pwr_ctrl	1	39 sec
TC_rsl_ms_pwr_dyn_active	33	24 sec
TC_rsl_ms_pwr_dyn_active2	33	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	33	15 sec
TC_rsl_ms_pwr_dyn_down	33	15 sec
TC_rsl_ms_pwr_dyn_max	33	15 sec
TC_rsl_ms_pwr_dyn_up	33	15 sec
TC_sacch_chan_act	33	42 sec
TC_sacch_chan_act_ho_async	33	24 sec
TC_sacch_chan_act_ho_sync	33	16 sec
TC_sacch_filling	33	36 sec
TC_sacch_info_mod	33	43 sec
TC_sacch_multi	33	52 sec
TC_sacch_multi_chg	33	36 sec
TC_si_sched_13	1	32 sec
TC_si_sched_13_2bis_2ter_2quater	33	39 sec
TC_tch_sign_l2_fill_frame	33	23 sec
TC_tch_sign_l2_fill_frame_dtxd	33	27 sec
TC_tx_power_ramp_adm_state_change	33	19 sec
TC_tx_power_start_ramp_down_bcch	33	19 sec
TC_tx_power_start_ramp_up_bcch	33	25 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	57-1	0	44+1	101	49 min