trial-ttcn3_bts_tests:sysmo 101

Took 51 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	8	37 sec
TC_chan_act_a52	8	37 sec
TC_chan_act_a53	15	37 sec
TC_chan_act_stress	8	24 sec
TC_conn_fail_crit	3	37 sec
TC_deact_sacch	15	1 min 1 sec
TC_encr_cmd_a51	8	37 sec
TC_encr_cmd_a52	8	37 sec
TC_encr_cmd_a53	15	37 sec
TC_ho_rach	15	37 sec
TC_meas_res_sign_sdcch4	15	37 sec
TC_meas_res_sign_sdcch8	15	37 sec
TC_meas_res_sign_tchf	15	37 sec
TC_meas_res_sign_tchh	15	37 sec
TC_meas_res_sign_tchh_toa256	15	37 sec
TC_meas_res_speech_tchf	15	24 sec
TC_meas_res_speech_tchf_facch	15	37 sec
TC_meas_res_speech_tchh	15	37 sec
TC_meas_res_speech_tchh_facch	15	37 sec
TC_meas_res_speech_tchh_toa256	15	37 sec
TC_ms_pwr_ctrl_constant	15	37 sec
TC_ms_pwr_ctrl_pf_ewma	15	37 sec
TC_paging_imsi_200percent	8	36 sec
TC_paging_imsi_80percent	8	37 sec
TC_paging_tmsi_200percent	8	37 sec
TC_paging_tmsi_80percent	8	37 sec
TC_rach_content Regression	1	37 sec
TC_rach_content_emerg Regression	1	37 sec
TC_rach_count Regression	1	38 sec
TC_rach_load_count	15	2 sec
TC_rach_load_idle_below_thresh	15	2 sec
TC_rach_load_idle_thresh0	15	2 sec
TC_rach_max_ta	15	37 sec
TC_rll_est_ind	8	29 sec
TC_rll_est_req_ACCH_3	15	37 sec
TC_rll_est_req_DCCH_3	8	37 sec
TC_rll_rel_ind_ACCH_0	15	37 sec
TC_rll_rel_ind_ACCH_3	15	37 sec
TC_rll_rel_ind_DCCH_0	8	37 sec
TC_rll_rel_ind_DCCH_3	8	37 sec
TC_rll_rel_req	15	37 sec
TC_rll_unit_data_ind_ACCH	8	37 sec
TC_rll_unit_data_ind_DCCH	8	37 sec
TC_rll_unit_data_req_ACCH	15	37 sec
TC_rll_unit_data_req_DCCH	8	37 sec
TC_rsl_bs_pwr_static_ass	5	30 sec
TC_rsl_bs_pwr_static_power_control	8	37 sec
TC_rsl_chan_initial_ms_pwr	15	28 sec
TC_rsl_chan_initial_ta	15	37 sec
TC_rsl_modify_encr	15	37 sec
TC_rsl_ms_pwr_ctrl	8	37 sec
TC_rsl_ms_pwr_dyn_active	15	25 sec
TC_rsl_ms_pwr_dyn_active2	15	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	15	16 sec
TC_rsl_ms_pwr_dyn_down	15	16 sec
TC_rsl_ms_pwr_dyn_max	15	16 sec
TC_rsl_ms_pwr_dyn_up	15	16 sec
TC_sacch_chan_act	15	37 sec
TC_sacch_chan_act_ho_async	15	37 sec
TC_sacch_chan_act_ho_sync	15	37 sec
TC_sacch_filling	15	37 sec
TC_sacch_info_mod	15	37 sec
TC_sacch_multi	15	37 sec
TC_sacch_multi_chg	15	37 sec
TC_si_sched_1	3	37 sec
TC_si_sched_13	8	37 sec
TC_si_sched_13_2bis_2ter_2quater	8	37 sec
TC_si_sched_2bis	3	37 sec
TC_si_sched_2quater	3	37 sec
TC_si_sched_2ter	3	37 sec
TC_si_sched_2ter_2bis	8	36 sec
TC_si_sched_default	3	28 sec
TC_speech_no_rtp_tchf	10	37 sec
TC_speech_no_rtp_tchh	8	37 sec
TC_tch_sign_l2_fill_frame	8	26 sec
TC_tch_sign_l2_fill_frame_dtxd	15	37 sec
TC_tx_power_ramp_adm_state_change	15	20 sec
TC_tx_power_start_ramp_down_bcch	15	27 sec
TC_tx_power_start_ramp_up_bcch	15	37 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+3	0	22-3	101	51 min