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A = = .   ! = !/MMIO64(addr) (*(volatile uint64_t *)(addr))ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8ADC_CHSELR(adc) MMIO32((adc) + 0x28)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1STM32G0 1ADC_CHANNEL_VREF 13ADC_TR1_HT_SHIFT 16ADC_AWD3TR(adc) MMIO32((adc) + 0x2c)ADC_CFGR1_EXTEN_MASK (0x3 << 10)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLLADC_AWDTR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAXADC_CFGR2_OVSR_MASK (0x7)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITLIBOPENCM3_ADC_COMMON_V2_H ADC_CHSELR_SQS_MAX_CHANNEL 14INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)LIBOPENCM3_ADC_H ADC_TR1_HT_MASK 0xFFF__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64ADC_CFGR1_DISCEN (1 << 16)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intADC_CFGR2_OVSS_SHIFT (5)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)ADC_CR_ADCAL (1 << 31)ADC_SMPR_SMPSEL_SMP1 0x0__UINT8_C(c) cADC_CFGR2_CKMODE_PCLK_DIV4 (0x2)__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64UINT_FAST32_MAXFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)adc_set_sample_time_on_all_channelsINT_FAST64_MAX __INT_FAST64_MAX__ADC_CFGR1_RES_8_BIT (0x2 << 3)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intstepdnADC_CLKSOURCE_PCLK ADC_CFGR2_CKMODE_PCLKADC_AW3CR_AWD3CHx_EN(x) (1 << x)INT32_MIN (-INT32_MAX - 1)ADC_ISR_EOS (1 << 3)__FLT32_MAX_10_EXP__ 38ADC_CCR_VBATEN (1 << 24)ADC_SMPR_SMPx_007DOT5CYC 0x2__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZadc_set_selection_sample_time__UINTPTR_MAX__ 0xffffffffUADC_SMPR1(adc) MMIO32((adc) + 0x14)__FLT32_MIN_EXP__ (-125)ADC_CR_ADSTP (1 << 4)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10)UINT32_MAX __UINT32_MAX__TIM3_BASE (PERIPH_BASE_APB + 0x0400)__DA_IBIT__ 32__ULFRACT_FBIT__ 32ADC_CFGR1_RES_10_BIT (0x1 << 3)__FLT64_MIN_10_EXP__ (-307)ADC_AWDTR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX____SFRACT_EPSILON__ 0x1P-7HRADC_CHANNEL_TEMP 12ADC_ISR_EOSEQ ADC_ISR_EOSadc_set_clk_sourceUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXADC_AWDTR3_LT_SHIFT 0__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__UHQ_FBIT__ 16ADC_CALFACT(adc) MMIO32((adc) + 0xB4)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffADC_SMPTIME_079DOT5 ADC_SMPR_SMPx_079DOT5CYC__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)INT64_C(c) __INT64_C(c)ADC_CCR_PRESC_DIV16 (0x7)INT_FAST64_MIN__GCC_IEC_559_COMPLEX 0ADC_TR1(adc) MMIO32((adc) + 0x20)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)cm3_assert_failed__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__ADC_TR1_LT_SHIFT 0__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xADC_CCR_PRESC_DIV6 (0x3)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffUADC_CFGR1_AWD1CH_SHIFT 26__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN____SIZEOF_DOUBLE__ 8__ARM_FEATURE_CMSE__FLT32X_MIN_EXP__ (-1021)TIM17_BASE (PERIPH_BASE_APB + 0x14800)BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9ADC_AWDTR3_LT_VAL(x) ((x) << ADC_TR3_LT_SHIFT)__thumb__ 1ADC_CHSELR_MAX_SQS 8LIBOPENCM3_MEMORYMAP_COMMON_H signed charADC_AWDTR2_LT_VAL(x) ((x) << ADC_TR2_LT_SHIFT)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15ADC_CFGR1_RES_12_BIT (0x0 << 3)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77ADC_SMPR_SMPx_012DOT5CYC 0x3__FLT64_MAX_10_EXP__ 308__WCHAR_WIDTH__ 32MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINadc_set_clk_prescale__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)selectionADC_CHANNEL_VBAT 14__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5ADC_CCR_PRESC_MASK (0xf)__ARM_ARCH_EXT_IDIV__ADC_SMPTIME_012DOT5 ADC_SMPR_SMPx_012DOT5CYC__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))ADC_CCR_PRESC_DIV32 (0x8)ADC_SMPR_SMPSEL_SHIFT 0x8__UINT16_MAX__ 0xffff__TQ_FBIT__ 127TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32INT_FAST16_MINWCHAR_MAX__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32_BoolSPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)UINT_LEAST8_MAXADC_AWDTR3_LT (0xFFF << ADC_TR3_LT_SHIFT)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)__USA_IBIT__ 16PTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)ADC_SMPR_SMPx_079DOT5CYC 0x6__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0UR__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2ADC_CFGR1_ALIGN (1 << 5)ADC_CCR_VREFEN (1 << 22)ADC_CCR_PRESC_DIV64 (0x9)adc_disable_regulator__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LADC_CCR_PRESC_DIV8 (0x4)__USFRACT_MIN__ 0.0UHR__ARM_NEONadc_enable_regulator__UINT8_MAX__ 0xffADC_SMPR_SMP2_MASK 0x7__LDBL_MAX_EXP__ 1024ADC_IER_EOSIE (1 << 3)LIBOPENCM3_MEMORYMAP_H ADC_AW2CR_AWD2CHx_EN(x) (1 << x)ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10)__DBL_HAS_DENORM__ 1source__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308L__ULLACCUM_EPSILON__ 0x1P-32ULLKCOMP_BASE (PERIPH_BASE_APB + 0x10200)__INT_LEAST32_WIDTH__ 32INT_LEAST8_MAX __INT_LEAST8_MAX__USART3_BASE (PERIPH_BASE_APB + 0x4800)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FADC_IER_EOCIE (1 << 2)__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8ADC_CFGR2_CKMODE_SHIFT (30)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8ADC_CR_ADVREGEN (1 << 28)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1ADC_CFGR1(adc) MMIO32((adc) + 0x0C)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_PCS 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)ADC_CFGR2_TOVS (1 << 9)__UINT_LEAST8_MAX__ 0xffADC_CCR_PRESC_SHIFT (18)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)ADC_AWDTR3_HT_SHIFT 16ADC_IER(adc) MMIO32((adc) + 0x04)ADC_SMPTIME_019DOT5 ADC_SMPR_SMPx_019DOT5CYCSYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)ADC_SMPR_SMPx_019DOT5CYC 0x4ADC_CR_ADSTART (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)ADC_CFGR2_OVSR_8x (0x2)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7f__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)adc_set_regular_sequence__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)ADC_CFGR1_CONT (1 << 13)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1ADC_CHSELR_SQx_MASK 0xf__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fINT_LEAST64_MAXBIT14 (1<<14)ADC_AWDTR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intADC_CFGR2_OVSR_128x (0x6)ADC_IER_EOSEQIE ADC_IER_EOSIEPERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXchannel__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLADC_CFGR2_OVSR_SHIFT (2)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXADC_CFGR1_EXTSEL_SHIFT 6LIBOPENCM3_ADC_COMMON_V2_SINGLE_H __LDBL_DENORM_MIN__ 4.9406564584124654e-324LADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__INT64_MAX__ 0x7fffffffffffffffLLADC_AWDTR2_LT (0xFFF << ADC_TR2_LT_SHIFT)ADC_CFGR1_AUTOFF (1 << 15)__ULLFRACT_IBIT__ 0ADC_OR(adc) MMIO32((adc) + 0xD0)MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12ADC_IER_AWD1IE (1 << 7)ADC_SMPR_SMPx_003DOT5CYC 0x1__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKADC_IER_ADRDYIE (1 << 0)__ARM_ARCH 6ADC_SMPTIME_001DOT5 ADC_SMPR_SMPx_001DOT5CYCADC_CCR_PRESC_DIV128 (0x10)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55ADC_CFGR2_OVSR_2x (0x0)ADC_IER_EOSMPIE (1 << 1)INT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLADC_CCR_PRESC_DIV1 (0x1)ADC_CR(adc) MMIO32((adc) + 0x08)__ARM_ARCH_PROFILEADC_ISR_EOSMP (1 << 1)__LFRACT_FBIT__ 31__CHAR_BIT__ 8ADC_CFGR2_LFTRIG (1 << 29)__SIZEOF_WCHAR_T__ 4ADC_SMPR_SMPx_039DOT5CYC 0x5ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sections__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0ADC_AWDTR3_HT (0xFFF << ADC_TR3_HT_SHIFT)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__ADC_IER_OVRIE (1 << 4)SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16ADC_AWDTR1_HT_SHIFT 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)ADC_CFGR1_SCANDIR (1 << 2)__INT_FAST32_TYPE__ intADC_AWDTR1_HT (0xFFF << ADC_TR1_HT_SHIFT)unsigned int__INT64_TYPE__ long long int__GCC_ASM_FLAG_OUTPUTS__adc.c__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKIOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKADC_CHSELR_MAX_CHANNELS 18ADC_ISR_AWD1 (1 << 7)__FLT_EVAL_METHOD__ 0ADC_SMPR_SMPSEL_SMP2 0x1__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charADC_CFGR1_AUTDLY (1 << 14)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)ADC_SMPR_SMP1_SHIFT 0x0__SIG_ATOMIC_TYPE__ intUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINADC_CCR_PRESC_DIV2 (0x2)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)cm3_assert_not_reached() cm3_assert_failed()__LFRACT_EPSILON__ 0x1P-31LRADC_ISR_CCRDY (1 << 13)ADC_TR1_LT_MASK 0xFFF__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1ADC_AWDTR1_LT_SHIFT 0ADC_SMPTIME_003DOT5 ADC_SMPR_SMPx_003DOT5CYC__FLT32_MIN_10_EXP__ (-37)ADC_CHSELR_SQx_SHIFT(seqnum) (4 * ((seqnum)-1))INFO_BASE (0x1fff7500U)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64stepup__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0LIBOPENCM3_CM3_ASSERT_H GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)__INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)ADC_CHSELR_CHSEL(x) (1 << (x))INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1ADC_CFGR2_CKMODE_MASK (0x3)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)ADC_ISR_ADRDY (1 << 0)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAXADC_CFGR2_OVSS_BITS(bits) (bits)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intADC_AWD2TR(adc) MMIO32((adc) + 0x22)ADC_CFGR2_CKMODE_PCLK (0x3)ADC_SMPR_SMPSEL_CHANNEL_MASK (1)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLADC_CFGR2_OVSS_MASK (0xf)__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63length__SACCUM_IBIT__ 8ADC_AWDTR2_HT (0xFFF << ADC_TR2_HT_SHIFT)reg32__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128ADC_AWDTR2_HT_SHIFT 16ADC_CFGR1_RES_MASK (0x3 << 3)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffADC_ISR_EOC (1 << 2)PTRDIFF_MAX __PTRDIFF_MAX____ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRADC_AWDTR2_LT_SHIFT 0_GCC_STDINT_H __DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intADC_CCR_PRESC_DIV256 (0x11)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)WCHAR_MINBEGIN_DECLS ADC_CR_ADEN (1 << 0)ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32x__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1ADC_CFGR1_DMAEN (1 << 0)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)__QQ_IBIT__ 0time__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intADC_CCR_PRESC_DIV10 (0x5)__USQ_IBIT__ 0ADC_SMPTIME_160DOT5 ADC_SMPR_SMPx_160DOT5CYC__UINT_LEAST32_TYPE__ long unsigned intADC_CCR_PRESC_NODIV (0x0)ADC_CFGR1_OVRMOD (1 << 12)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intADC_CCR_TSEN (1 << 23)__GCC_ATOMIC_INT_LOCK_FREE 1INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_ADCCLKADC_AWDTR3_HT_VAL(x) ((x) << ADC_TR3_HT_SHIFT)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)ADC_CFGR2_OVSR_4x (0x1)ADC_CFGR2_OVSR_64x (0x5)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16ADC_SMPR_SMPSEL_MASK 0x7ffffCORESIGHT_LAR_OFFSET 0xfb0ADC_SMPR_SMPx_160DOT5CYC 0x7short int__UINT16_C(c) c__UDA_IBIT__ 32ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)ADC1 ADC1_BASE__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53ADC_CFGR2(adc) MMIO32((adc) + 0x10)BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CADC_CFGR2_OVSR_32x (0x4)INT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1ADC_CFGR2_CKMODE_PCLK_DIV2 (0x1)ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)ADC_SMPTIME_007DOT5 ADC_SMPR_SMPx_007DOT5CYCINT16_C(c) __INT16_C(c)ADC_SMPR_SMPSEL_CHANNEL_SHIFT(channel) ((channel) + ADC_SMPR_SMPSEL_SHIFT)__INT16_MAX__ 0x7fff__INT_WIDTH__ 32ADC_CFGR1_WAIT (1<<14)__QQ_FBIT__ 7ADC_CFGR1_AWD1SGL (1 << 22)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRADC_CR_ADDIS (1 << 1)__SIZEOF_WINT_T__ 4ADC_CFGR2_OVSR_256x (0x7)ADC_CFGR1_CHSELRMOD (1 << 21)__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1ADC_DR(adc) MMIO32((adc) + 0x40)ADC_SMPTIME_039DOT5 ADC_SMPR_SMPx_039DOT5CYCADC_CFGR2_CKMODE_ADCCLK (0x0)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODADC_ISR(adc) MMIO32((adc) + 0x00)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H ADC_CFGR1_DMACFG (1 << 1)__GCC_CONSTRUCTIVE_SIZE 64ADC_SMPR_SMP2_SHIFT 0x4__LLFRACT_IBIT__ 0ADC_CCR_PRESC_DIV12 (0x6)uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKADC_CFGR2_OVSR_16x (0x3)ADC_CHSELR_SQx(seqnum,value) ((value) << ADC_CHSELR_SQx_SHIFT(seqnum))__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8ADC_SMPR_SMP1_MASK 0x7__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15ADC_IER_CCRDYIE (1 << 13)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINADC_TR1_LT_VAL(x) (((x) & ADC_TR1_LT_MASK) << ADC_TR1_LT_SHIFT)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308ADC_ISR_OVR (1 << 4)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT)__SIZE_MAX__ 0xffffffffUADC_SMPR_SMPx_001DOT5CYC 0x0__ARM_FEATURE_SATADC_AWDTR2_HT_VAL(x) ((x) << ADC_TR2_HT_SHIFT)__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1ADC_CFGR1_RES_6_BIT (0x3 << 3)prescaleINT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__LLFRACT_EPSILON__ 0x1P-63LLRADC_CHSELR_SQx_EOS 0xf__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__WINT_MAXADC_CFGR2_OVSE (1 << 0)__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)adc_set_channel_sample_time_selection__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)cm3_assert(expr) do { if (CM3_LIKELY(expr)) { (void)0; } else { cm3_assert_failed(); } } while (0)ADC_AWD1TR(adc) MMIO32((adc) + 0x20)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53ADC_CFGR1_AWD1EN (1 << 23)__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |   A  A  A+aeabi!6S-M M      !9;#%')+-/1357= 4e-a   <?   7J_  adc.c$t$dwm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.adc_common_v2.h.36.c29b9554df309f9d4822804bbb940b15wm4.adc_common_v2_single.h.43.b8a01d872eb95399a26fc4125c4a99d4wm4.adc.h.40.a85a4f906ebd5f6415e055c6aca6f0ccwm4.assert.h.49.015b362b73716e3cc7cc0fcda59cfa2eadc_set_clk_sourceadc_set_clk_prescaleadc_set_sample_time_on_all_channelsadc_set_channel_sample_time_selectionadc_set_selection_sample_timeadc_set_regular_sequencecm3_assert_failedadc_enable_regulatoradc_disable_regulator0 J "&-4;BGT[`mt  *.3=AFPTYkou %).8<BG cmqv @x   / H ax  ( 08@H % + 17>D !"'#-$7@H%N&Ya'j(p)z* #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy 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54532 ` ELF(|4(]\?@ABCDEFGHIJKLMNOPQRh@pGhpG#hC`pG#h@pG#"hBh CpG(!"h1B#hC` hB#hC` (#hC`pGhpGh+#hC`pGhJ@`pGF"hC C`pG #hC`pG "hC`pG#hC`pG"hC`pG#BhCC`pG"ChCC`pGhpG#`pG#BhCC`pG"ChCC`pGlpG#Jh C`pGF'@JIh @`pG'@#Jh C`pGF'@JIh @`pG'@#hC`pG#hC`pG"hC`pG#hC`pGhJ@`pGFsN3 R,O1 N1Wd EW4h )Dintq7e!adc3^PY adc2^PF adc-^P, adc,^P|] 8adc,^P #Dt k L_ -VyK ^adcK^ '= adc=)^P4 adc4(^P>+adc+&^P5DDadc^'#k  oadc-^PGQ adc,^PY adc^P+ adc^P? adc%^Pp adc$^PX Kadc"^PP0MQnOmadc.^PpG adc2^PWadc^@: ZX Pt*KD adc"^& )adc#^Pu&uadc^icdPt uPt _ Dadc ^dJl adcl#^r^=Ks^ZI^)adc^^)  a 7 CPt0TDC adcT^.I eadcI"^P nS?Dadc?^ R1Dadc1^)70Y  "lH&$1/=; uPtKG.?:!; 9!'@z$ > .?:!;9!'@z:!;9 I:!; 9 I:!; 9 IB1BI~ .?:!;9!'@z H} :!; 9 I .?:!; 9!'I@z :!; 9!I.?:!;9 'I@z:!;9!$IB1RB X!Y W .?:!; 9!'I !4:!; 9! I.1@z4141B% Uy$ > : ; 9 IH}.?: ; 9 ' 1RB UX Y W .1@zZPPPPPTPTPTPPPPTP TPPPPPPP.T.0P "T "4 "@PP$ 0      0               %?@*( !# $ :b OT[/< XP&-A]b-v--@w\02HNd4M?7D ^v5:( <x g[KJFM;<H44<;)2V\N=YC^fFCK,PF/79y*XMM9E^N?0tYYD[I*B)vS/1 @ X*^PP#Sl(YS*.~Y&&&@Y\,%T ;+N(# O>'}C,UU69Gj UJ  )2 f2h98(*E%0?-87Dc/j/TD, (?JP^N'Ab],sRZ6,`'66PLkXjNtZWU>\+.?A"13E+A @>?M]5+rUQZ~"1QcY  3VCU-%3S q87 D\G<&'#I=2vU[M:5(R %\K %CE*K6k@h4/Q4@':R= ^dHpFN=ZW L`\$.V.TBEmMyW!88(rL?OBN(KX/ -8&"W 1UFg Eu0HfXJ*7GCGU7KESJZT]P PEH59-0 $FKu6S-*GIPF2I)2]"?p%Xx<PZTM%h[T]=,AU>!KW0z2!MVAjB(K4wT:T2z[C*)?(nV&96b)V19f K\='!4#=[0E~7M9VJ ?Z) =2t)>9ML~[%Fs56N#J^ &\kP-OB_!+d+HT5JR!$I")$}@d*e`,f5<gAjk5ni1o5?p+Jqr%t3u"xBy/z3Z{~!%E  59cM$^+B 3F`:B:Y<Z@)Q_&9O;P QE{ \@CP 9&+&'0-=^Z! ]i*I*~@H5Ls1TV~1;K#L2Q3!+4#/\GX*@o@1 /IH,\Qe?9RMPhFfMM= [_ X^ [jZ<V!)#&q<']!2ZC"D//EoFI#LwQRQSLPT1U{VQW1XYRZL[< \L@]NW^_~(`7BaXb c[*dCeT)f\BgYhi*j[kZl'mv,nBFo-+pDX+*9"<6?BSE\WJ.L[<0\O_;a%c!1W<8>D_  B!5"#;$Q%_&6'(d )Q*]+x ,S-&./X90>1UA2,3415^67$8 9K8:;q<}D=O>W"?@!C DJEPF{?GH2I;\J(L1IMNHOP;QT :UlEVKW?X [g\ ]4$*V,6$.40"2dQ4 68U<1F8HZJ5K MGOxJQEBZ\6^_)a c;e0np r$taTvU~I [d^Y;'K-=< RG \V0o=X.#Y,9I*+.19S;.>7D|A(E- ./6]83C:=P?B E/NBVX]^#akKb3c><deCfKg+Wh~ijk0lHu!}MgIT"!AV0RXCs4}#CB+>1N%WQN)T\QOStC8;4XW][. 9$4O= (^6G7 {H.;GE[86([>W\: $L54M Mv-:QR>R X$t; g/{ ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32/commonadc_common_v2.cstdint.hadc.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hadc.hadc_common_v2.hadc_common_v2_single.h1 !/? !/! /!  ! !/u  s   /  ! ! !.,  ./  / >  . !/   </! = !! !/ t   /! = !/#!# :  !! /! /! /! /! /! / !/!!! /! / !!   /  !/!   /  !/! /! /! /! = !/MMIO64(addr) (*(volatile uint64_t *)(addr))ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8ADC_CHSELR(adc) MMIO32((adc) + 0x28)PERIPH_BASE_APB (PERIPH_BASE + 0x00000)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__INTMAX_C(c) c ## LL__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1__UINTPTR_MAX__ 0xffffffffUSTM32G0 1ADC_CHANNEL_VREF 13ADC_TR1_HT_SHIFT 16ADC_AWD3TR(adc) MMIO32((adc) + 0x2c)ADC_CFGR1_EXTEN_MASK (0x3 << 10)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLLADC_AWDTR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAXADC_CFGR2_OVSR_MASK (0x7)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITLIBOPENCM3_ADC_COMMON_V2_H ADC_CHSELR_SQS_MAX_CHANNEL 14INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)LIBOPENCM3_ADC_H ADC_TR1_HT_MASK 0xFFF__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64ADC_CFGR1_DISCEN (1 << 16)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intADC_CFGR2_OVSS_SHIFT (5)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)ADC_CR_ADCAL (1 << 31)ADC_SMPR_SMPSEL_SMP1 0x0__UINT8_C(c) cADC_CFGR2_CKMODE_PCLK_DIV4 (0x2)__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64UINT_FAST32_MAXadc_enable_eoc_interruptFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)INT_FAST64_MAX __INT_FAST64_MAX__ADC_CFGR1_RES_8_BIT (0x2 << 3)checks__ULLFRACT_FBIT__ 64__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intADC_CLKSOURCE_PCLK ADC_CFGR2_CKMODE_PCLKADC_AW3CR_AWD3CHx_EN(x) (1 << x)INT32_MIN (-INT32_MAX - 1)ADC_SMPR_SMPx_003DOT5CYC 0x1__FLT32_MAX_10_EXP__ 38adc_disable_overrun_interruptADC_SMPR_SMPx_007DOT5CYC 0x2__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZI2C2_BASE (PERIPH_BASE_APB + 0x5800)ADC_SMPR1(adc) MMIO32((adc) + 0x14)__FLT32_MIN_EXP__ (-125)ADC_CR_ADSTP (1 << 4)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10)UINT32_MAX __UINT32_MAX__TIM3_BASE (PERIPH_BASE_APB + 0x0400)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32ADC_CFGR1_RES_10_BIT (0x1 << 3)__FLT64_MIN_10_EXP__ (-307)ADC_AWDTR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX____SFRACT_EPSILON__ 0x1P-7HRADC_CHANNEL_TEMP 12ADC_ISR_EOSEQ ADC_ISR_EOS__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXADC_AWDTR3_LT_SHIFT 0__SQ_FBIT__ 31adc_is_power_offadc_set_left_aligned__UHQ_FBIT__ 16ADC_CALFACT(adc) MMIO32((adc) + 0xB4)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffADC_SMPTIME_079DOT5 ADC_SMPR_SMPx_079DOT5CYC__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)INT64_C(c) __INT64_C(c)ADC_CCR_PRESC_DIV16 (0x7)__GCC_IEC_559_COMPLEX 0ADC_TR1(adc) MMIO32((adc) + 0x20)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)ADC_CFGR1_EXTSEL_SHIFT 6__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__ADC_TR1_LT_SHIFT 0__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xADC_CCR_PRESC_DIV6 (0x3)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)ADC_SMPTIME_001DOT5 ADC_SMPR_SMPx_001DOT5CYCBIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffUADC_CFGR1_AWD1CH_SHIFT 26__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__ADC_CFGR1_AWD1SGL (1 << 22)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32ADC_IER_AWD1IE (1 << 7)TIM17_BASE (PERIPH_BASE_APB + 0x14800)BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9ADC_AWDTR3_LT_VAL(x) ((x) << ADC_TR3_LT_SHIFT)__thumb__ 1ADC_CHSELR_MAX_SQS 8LIBOPENCM3_MEMORYMAP_COMMON_H signed charADC_AWDTR2_LT_VAL(x) ((x) << ADC_TR2_LT_SHIFT)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15ADC_CFGR1_RES_12_BIT (0x0 << 3)__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1PTRDIFF_MIN__UINT_LEAST16_MAX__ 0xffffUINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77ADC_SMPR_SMPx_012DOT5CYC 0x3__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)ADC_CHANNEL_VBAT 14__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5ADC_CCR_PRESC_MASK (0xf)__ARM_ARCH_EXT_IDIV__ADC_SMPTIME_012DOT5 ADC_SMPR_SMPx_012DOT5CYC__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))ADC_CCR_PRESC_DIV32 (0x8)ADC_SMPR_SMPSEL_SHIFT 0x8__UINT16_MAX__ 0xffff__TQ_FBIT__ 127TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32INT_FAST16_MIN__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32adc_set_resolution_BoolSPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)UINT_LEAST8_MAXADC_AWDTR3_LT (0xFFF << ADC_TR3_LT_SHIFT)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)__USA_IBIT__ 16PTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)ADC_SMPR_SMPx_079DOT5CYC 0x6adc_enable_vrefint__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0UR__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2ADC_CFGR1_ALIGN (1 << 5)ADC_CCR_VREFEN (1 << 22)ADC_CCR_PRESC_DIV64 (0x9)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LADC_CCR_PRESC_DIV8 (0x4)__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xffADC_SMPR_SMP2_MASK 0x7__LDBL_MAX_EXP__ 1024ADC_IER_EOSIE (1 << 3)LIBOPENCM3_MEMORYMAP_H ADC_AW2CR_AWD2CHx_EN(x) (1 << x)ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)adc_read_regular__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LCOMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX __INT_LEAST8_MAX__USART3_BASE (PERIPH_BASE_APB + 0x4800)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FADC_IER_EOCIE (1 << 2)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8ADC_CFGR2_CKMODE_SHIFT (30)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0adc_disable_delayed_conversion_modeDBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8ADC_CR_ADVREGEN (1 << 28)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1ADC_CFGR1(adc) MMIO32((adc) + 0x0C)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_PCS 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)ADC_CFGR2_TOVS (1 << 9)__UINT_LEAST8_MAX__ 0xffADC_CCR_PRESC_SHIFT (18)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)ADC_AWDTR3_HT_SHIFT 16ADC_IER(adc) MMIO32((adc) + 0x04)ADC_SMPTIME_019DOT5 ADC_SMPR_SMPx_019DOT5CYCSYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)ADC_SMPR_SMPx_019DOT5CYC 0x4ADC_CR_ADSTART (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)ADC_CFGR2_OVSR_8x (0x2)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULadc_power_off__INT_LEAST8_MAX__ 0x7f__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)adc_calibrate_async__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)ADC_CFGR1_CONT (1 << 13)adc_disable_eoc_interrupt__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1ADC_CHSELR_SQx_MASK 0xf__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)ADC_AWDTR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intADC_CFGR2_OVSR_128x (0x6)ADC_IER_EOSEQIE ADC_IER_EOSIE__SOFTFP__ 1UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32ADC_CCR_TSEN (1 << 23)__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLADC_CFGR2_OVSR_SHIFT (2)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32adc_enable_dma__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1adc_enable_dma_circular_mode/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKadc_enable_temperature_sensor__FLT64_NORM_MAX__ 1.7976931348623157e+308F64__FINITE_MATH_ONLY__ 0LIBOPENCM3_ADC_COMMON_V2_SINGLE_H __LDBL_DENORM_MIN__ 4.9406564584124654e-324LADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__INT64_MAX__ 0x7fffffffffffffffLLADC_AWDTR2_LT (0xFFF << ADC_TR2_LT_SHIFT)adc_power_on_asyncADC_CFGR1_AUTOFF (1 << 15)__ULLFRACT_IBIT__ 0ADC_OR(adc) MMIO32((adc) + 0xD0)MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12ADC_SMPTIME_160DOT5 ADC_SMPR_SMPx_160DOT5CYCWCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKADC_IER_ADRDYIE (1 << 0)__ARM_ARCH 6adc_is_power_onADC_CCR_PRESC_DIV128 (0x10)ADC_CFGR1_DMAEN (1 << 0)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55ADC_CFGR2_OVSR_2x (0x0)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXINTPTR_MIN__LDBL_HAS_QUIET_NAN__ 1ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsADC_CCR_PRESC_DIV1 (0x1)ADC_CR(adc) MMIO32((adc) + 0x08)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8ADC_CFGR2_LFTRIG (1 << 29)__SIZEOF_WCHAR_T__ 4ADC_SMPR_SMPx_039DOT5CYC 0x5ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0ADC_AWDTR3_HT (0xFFF << ADC_TR3_HT_SHIFT)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPADC_ISR_EOS (1 << 3)adc_get_overrun_flagADC_IER_OVRIE (1 << 4)SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16ADC_AWDTR1_HT_SHIFT 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)ADC_CFGR1_SCANDIR (1 << 2)__INT_FAST32_TYPE__ intADC_AWDTR1_HT (0xFFF << ADC_TR1_HT_SHIFT)unsigned int__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKIOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKADC_CHSELR_MAX_CHANNELS 18ADC_ISR_AWD1 (1 << 7)__FLT_EVAL_METHOD__ 0ADC_SMPR_SMPSEL_SMP2 0x1__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charADC_CFGR1_AUTDLY (1 << 14)ADC_SMPTIME_039DOT5 ADC_SMPR_SMPx_039DOT5CYCADC_SMPR_SMP1_SHIFT 0x0__SIG_ATOMIC_TYPE__ intADC_IER_EOSMPIE (1 << 1)INTPTR_MIN (-INTPTR_MAX - 1)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINADC_CCR_PRESC_DIV2 (0x2)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__FLT32X_MIN_EXP__ (-1021)ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 1ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)__LFRACT_EPSILON__ 0x1P-31LRADC_TR1_LT_MASK 0xFFF__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1ADC_AWDTR1_LT_SHIFT 0ADC_SMPTIME_003DOT5 ADC_SMPR_SMPx_003DOT5CYC__FLT32_MIN_10_EXP__ (-37)ADC_CHSELR_SQx_SHIFT(seqnum) (4 * ((seqnum)-1))INFO_BASE (0x1fff7500U)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308Ladc_clear_overrun_flagDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1adc_set_right_aligned__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN 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0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intADC_CCR_PRESC_DIV256 (0x11)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)WCHAR_MINBEGIN_DECLS GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)adc_power_onADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15ADC_CCR_VBATEN (1 << 24)__FLT32X_MAX__ 1.7976931348623157e+308F32x__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1adc_power_off_asyncADC_ISR_EOSMP (1 << 1)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intADC_CCR_PRESC_DIV10 (0x5)__USQ_IBIT__ 0adc_is_calibratingstops__UINT_LEAST32_TYPE__ long unsigned intADC_CCR_PRESC_NODIV (0x0)ADC_CFGR1_OVRMOD (1 << 12)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intUINTPTR_MAX__GCC_ATOMIC_INT_LOCK_FREE 1adc_disable_temperature_sensorINTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)UINT_FAST64_MAX __UINT_FAST64_MAX____LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_ADCCLKADC_AWDTR3_HT_VAL(x) ((x) << ADC_TR3_HT_SHIFT)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intuint16_t__INT64_C(c) c ## LLADC_CFGR2_OVSR_4x (0x1)__LDBL_MIN_10_EXP__ (-307)ADC_CFGR2_OVSR_64x (0x5)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16ADC_SMPR_SMPSEL_MASK 0x7ffffadc_set_single_conversion_modeCORESIGHT_LAR_OFFSET 0xfb0ADC_SMPR_SMPx_160DOT5CYC 0x7INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)short int__UINT16_C(c) c__UDA_IBIT__ 32ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 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(0x7)ADC_CFGR1_CHSELRMOD (1 << 21)__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17ADC_CR_ADEN (1 << 0)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1ADC_DR(adc) MMIO32((adc) + 0x40)ADC_CFGR2_CKMODE_ADCCLK (0x0)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODADC_ISR(adc) MMIO32((adc) + 0x00)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H ADC_CFGR1_DMACFG (1 << 1)__GCC_CONSTRUCTIVE_SIZE 64ADC_SMPR_SMP2_SHIFT 0x4__LLFRACT_IBIT__ 0ADC_CCR_PRESC_DIV12 (0x6)uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKADC_CFGR2_OVSR_16x (0x3)ADC_CHSELR_SQx(seqnum,value) ((value) << ADC_CHSELR_SQx_SHIFT(seqnum))adc_calibrate__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8ADC_SMPR_SMP1_MASK 0x7__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15ADC_IER_CCRDYIE (1 << 13)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINADC_TR1_LT_VAL(x) (((x) & ADC_TR1_LT_MASK) << ADC_TR1_LT_SHIFT)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8adc_enable_delayed_conversion_mode__INT_LEAST16_TYPE__ short intadc_disable_dma__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308ADC_ISR_OVR (1 << 4)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT)__SIZE_MAX__ 0xffffffffUADC_SMPR_SMPx_001DOT5CYC 0x0__ARM_FEATURE_SATADC_AWDTR2_HT_VAL(x) ((x) << ADC_TR2_HT_SHIFT)__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1BIT25 (1<<25)ADC_CFGR1_RES_6_BIT (0x3 << 3)INT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__LLFRACT_EPSILON__ 0x1P-63LLRADC_CHSELR_SQx_EOS 0xf__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__WINT_MAXADC_CFGR2_OVSE (1 << 0)__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)adc_start_conversion_regularADC_AWD1TR(adc) MMIO32((adc) + 0x20)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53ADC_CFGR1_AWD1EN (1 << 23)__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)UINT64_MAX __UINT64_MAX__INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |   A 0AA A         A+aeabi!6S-M M       !!""##$$%%&&''(())**+++,, ,---.. .//00112233 34679;=SU?ACEGIKMOQW>o7k  VY    3CPa0u      " !8 "G #W $t %&' ( )*+ ,?-R.f / 0 1 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| -!!', G ea @`- q+ @\a-;( @da-c @|a-|] @aX-~  @a -W  @o -s N @o-" @s(- @s0- R @,uh-"x @u-$ @w-&0F0['[0 @w -*p\,,\.+ ^w/57 0 0 0 644 56044 ` ELF(44(KJ123456789:;<=>?@#"9KC``aZa#@BhCC`pG9@B`pG9@h@CApGK!YC#0hC "`hC`pGK!YC0hI @`hC`pGFK!YC0hI @`hC`pGFK!YC0hI @`hC`pGFK!YC#0hC`pGK!"YC0hC`pGK!YC@#0hC`pGK!@"YC0hC`pGK!YC #0hC`hJ@`pGK!"YC0hC`pGK!YC#0hC`pGK!YC#0hC`pGK!"YC0hC`pGK!YC#0hC`pGK!"YC0hC`pGK!YC#0hC`pGK!"YC0hC`pGK!YC#0hC`pGK!"YC0hC`pGK!YChapGK!YChBapGK!YC 0 hpGK!YC 0  `pGV #8 H>?0 HT=4.Q +I1c[4uz,!Hint<1dma&j .3F&" OEXRz] X!dma*j?9.7F]YFLdma0j.=Fk6 dma'j .4F)% 3jR dma#jB<.0F`\ [BjR. $dma jys.-F ?jR u_dmau'j.u4F"cdmac&j.c3F7cEj }>fj,& /P & dmaP)jP.P6Flh#2Qj  TjS6  dma6!jP.6.F:!;9 IB:!;9 IB:!; 9 IB.?:!;9!'@z$ > .?:!; 9!'@z:!; 9 IB:!; 9 I :!;9 I :!; 9 I 4:!; 9! IB :!; 9 I % Uy$ > .?: ;9 'I@z.?: ; 9 'I@z.?: ; 9 '@zPptQQP pt PQQPPQQPPQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQQ P px PQ Q P px PQQ P px PQQ P px PQQ P px PQQP px PQ QP px PQ QP px PQ Q P px PQQPPQQRR rq12$$rQ12$$RQ12$$Q QR RRQ Q         +?@** S V? I3ZU*0/bJD1X1JD8{#xR7BG5 i9n?L @HO1OJ?Ls7##,E[R^FodIhO/gI;.]nQQC =HXd+SDq35^^0`-,W35 ,D> ]6jcU.&wX ,Wy.2`)j))D\^} a'Y .%V+[&-iT*Gz/UZ=K9Zf  ~55 >Mo=-'{4 1D=<`Hs<3GY" o+@iNcR;Eqb0OV^:*UUPd](@I_Y B1C$4H&/E +Bj? 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"   =0   /! /0.  = /0.  = /0.  = //   // .  //   // .  /0   / =/ .  //   //   // .  //   // .  //   // .  //   // .  /.. /".. /" / ..!/. !DMA_CCR_HTIE (1 << 2)MMIO64(addr) (*(volatile uint64_t *)(addr))SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8DMA2_CCR(channel) DMA_CCR(DMA2, channel)DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64dma_set_peripheral_addressCORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1STM32G0 1DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)__FLT64_HAS_INFINITY__ 1DMA_ISR_TCIF_BIT DMA_TCIF__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17DMA_CCR_PSIZE_8BIT (0x0 << 8)WINT_MIN __WINT_MIN__INT_FAST64_MAXDMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITDMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKDMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64dma_set_read_from_peripheral__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed charDMA1_IFCR DMA_IFCR(DMA1)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)__UINT8_C(c) c__INT16_TYPE__ short intDMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)__FLT64_MAX__ 1.7976931348623157e+308F64peripheral_sizeUINT_FAST32_MAXDMA1_CMAR(channel) DMA_CMAR(DMA1, channel)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)INT_FAST64_MAX __INT_FAST64_MAX__DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intDMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38dma_set_read_from_memoryDMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)dma_enable_mem2mem_mode__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZDMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))dma_set_memory_sizeUINT32_MAX __UINT32_MAX__TIM3_BASE (PERIPH_BASE_APB + 0x0400)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32__FLT64_MIN_10_EXP__ (-307)DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__DMA_CCR_TCIE (1 << 1)__SFRACT_EPSILON__ 0x1P-7HR__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31DMA_CCR_PL_HIGH (0x2 << 12)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)DMA1_CCR(channel) DMA_CCR(DMA1, channel)prioDMA_CHANNEL2 2__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)DMA_CCR_PINC (1 << 6)__LACCUM_IBIT__ 32DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffff__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)INT64_C(c) __INT64_C(c)__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charDMA_CCR_PSIZE_16BIT (0x1 << 8)__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____TA_FBIT__ 63__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)TIM17_BASE (PERIPH_BASE_APB + 0x14800)BIT27 (1<<27)DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))TIM7_BASE (PERIPH_BASE_APB + 0x1400)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)__thumb__ 1LIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)DMA_CCR_PL_MASK (0x3 << 12)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKDMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))__GNUC_PATCHLEVEL__ 1PTRDIFF_MINdma_disable_peripheral_increment_mode__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX__DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINDMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5__ARM_ARCH_EXT_IDIV__DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))DMA_HTIF (1 << 2)__UINT16_MAX__ 0xffff__LDBL_MIN__ 2.2250738585072014e-308L__TQ_FBIT__ 127DMA_CHANNEL7 7TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32INT_FAST16_MINDMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)_BoolDMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16dma_enable_memory_increment_modePTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)DMA_CCR_PL_SHIFT 12__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LDMA2_IFCR DMA_IFCR(DMA2)__ARM_NEON__UINT8_MAX__ 0xffDMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H __DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__DA_FBIT__ 31flagsDMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)__GXX_ABI_VERSION 1017DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LDMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)__ULLACCUM_EPSILON__ 0x1P-32ULLKDMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))COMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX __INT_LEAST8_MAX__USART3_BASE (PERIPH_BASE_APB + 0x4800)__UACCUM_MIN__ 0.0UKdma_get_interrupt_flag__FLT_EPSILON__ 1.1920928955078125e-7FDMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)__ARM_ARCH_ISA_THUMBDMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charDMA_CMAR(dma_base,channel) MMIO32((dma_base) + 0x14 + (0x14 * ((channel) - 1)))__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)DMA_IFCR_CTEIF_BIT DMA_TEIF__FLT32_MIN__ 1.1754943508222875e-38F32__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1dma_enable_transfer_error_interruptUINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)__ARM_PCS 1bool _BoolDMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (DMA_FLAG_OFFSET(channel)))UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLDMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRDMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))DMA_CCR_MSIZE_MASK (0x3 << 10)__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7f__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDMA_CCR_EN (1 << 0)DAC_BASE (PERIPH_BASE_APB + 0x7400)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)DMA_CCR_PL_MEDIUM (0x1 << 12)DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intDMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))PERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0address__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXchannel__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICdma_set_prioritydma_clear_interrupt_flags__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0DMA_CCR(dma_base,channel) MMIO32((dma_base) + 0x08 + (0x14 * ((channel) - 1)))__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24dma_set_number_of_data__UDQ_IBIT__ 0__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXDMA_TCIF (1 << 1)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLinterrupts__ULLFRACT_IBIT__ 0DMA_ISR_TEIF_BIT DMA_TEIFDMA_FLAG_OFFSET(channel) (4*((channel) - 1))dma_enable_peripheral_increment_modeMMIO16(addr) (*(volatile uint16_t *)(addr))DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)__GNUC__ 12WCHAR_MAXDMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)DMA_IFCR_CIF_BIT 0xFDMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)TAMP_BASE (PERIPH_BASE_APB + 0xB000)DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xdma_set_peripheral_sizeINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXDMA_CHANNEL4 4__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLdma_disable_transfer_complete_interruptDMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8interrupt__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsDMA_CCR_MEM2MEM (1 << 14)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXDMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0dma_enable_transfer_complete_interrupt__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)SYS_TICK_BASE (SCS_BASE + 0x0010)DMA_IFCR_CGIF_BIT DMA_GIF__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)SPI2_BASE (PERIPH_BASE_APB + 0x3800)DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)DMA_ISR(dma_base) MMIO32((dma_base) + 0x00)DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)DMA_CCR_PL_LOW (0x0 << 12)__INT_FAST32_TYPE__ intunsigned int__GCC_ASM_FLAG_OUTPUTS__DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__FLT_EVAL_METHOD__ 0DMA_CCR_MINC (1 << 7)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DMA_IFCR(dma_base) MMIO32((dma_base) + 0x04)__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX../common/dma_common_l1f013.c__UQQ_FBIT__ 8INT16_Cflag__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__DMA_GIF (1 << 0)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)dma_disable_channel__SIG_ATOMIC_TYPE__ intUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINDMA_CCR_CIRC (1 << 5)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LR__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))DMA_CHANNEL3 3DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)DMA_TEIF (1 << 3)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__ARM_ARCH_PROFILE 77__SACCUM_IBIT__ 8DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LDBL_HAS_DENORM__ 1DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)PPBI_BASE (0xE0000000U)BIT15 (1<<15)DMA_ISR_GIF_BIT DMA_GIFBIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intDMA2 DMA2_BASEBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAXuint16_tDMA_CCR_PSIZE_32BIT (0x2 << 8)__UHQ_IBIT__ 0dma_disable_memory_increment_modeINT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intDMA_CNDTR(dma_base,channel) MMIO32((dma_base) + 0x0C + (0x14 * ((channel) - 1)))__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffDMA_CHANNEL5 5PTRDIFF_MAX __PTRDIFF_MAX__DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKDMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRDMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)WCHAR_MINdma_enable_circular_modeDMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)BEGIN_DECLS GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xDMA_ISR_HTIF_BIT DMA_HTIF__ARM_EABI__ 1DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMA_CCR_DIR (1 << 4)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31LIBOPENCM3_DMA_COMMON_F13_H __UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned intnumber__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)DMA1 DMA1_BASEDMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CDMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)INT64_MINdma_set_memory_address__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intDMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRDMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)DMA_IFCR_CTCIF_BIT DMA_TCIFLIBOPENCM3_DMA_H __LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16DMA2_ISR DMA_ISR(DMA2)dma_channel_resetDMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)CORESIGHT_LAR_OFFSET 0xfb0dma_enable_channelDMA_IFCR_CHTIF_BIT DMA_HTIFDMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)short intDMA_CCR_MSIZE_SHIFT 10__UINT16_C(c) c__UDA_IBIT__ 32DMA1_ISR DMA_ISR(DMA1)DMA_CCR_MSIZE_32BIT (0x2 << 10)UINT_LEAST32_MAXDMA2_CMAR(channel) DMA_CMAR(DMA2, channel)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)BIT5 (1<<5)__USFRACT_MIN__ 0.0UHRBIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)BIT8 (1<<8)DMA_CCR_MSIZE_8BIT (0x0 << 10)INT16_C(c) __INT16_C(c)DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)__INT16_MAX__ 0x7fffDMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)__INT_WIDTH__ 32DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)__QQ_FBIT__ 7DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)__ULLFRACT_EPSILON__ 0x1P-64ULLR__SIZEOF_WINT_T__ 4DMA_CPAR(dma_base,channel) MMIO32((dma_base) + 0x10 + (0x14 * ((channel) - 1)))__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1__TA_IBIT__ 64DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)DMA_CCR_PSIZE_SHIFT 8__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H __GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0mem_sizeuint32_tBIT12 (1<<12)DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKDMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)DMA_CHANNEL1 1dma_enable_half_transfer_interruptDMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKdma_get_number_of_data__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)DMA_CHANNEL6 6__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (DMA_FLAG_OFFSET(channel)))__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)__HQ_FBIT__ 15__bool_true_false_are_defined 1DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATDMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1DMA_CCR_TEIE (1 << 3)DMA_CCR_MSIZE_16BIT (0x1 << 10)DMA_CCR_PSIZE_MASK (0x3 << 8)INT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__LLFRACT_EPSILON__ 0x1P-63LLR__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)__ATOMIC_ACQ_REL 4DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32dma_disable_transfer_error_interruptI2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULLDMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)__DBL_MANT_DIG__ 53DMA_CCR_PL_VERY_HIGH (0x3 << 12)__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)INT_FAST16_MAXdma_disable_half_transfer_interrupt__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intDMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)IWDG_BASE (PERIPH_BASE_APB + 0x3000)DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)__ARM_FEATURE_CDE_COPROCDMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |                    A+aeabi!6S-M M          !!""##$$%%&()+-/AC13579;=?EBs;oDG      + Cd  Di !&"A#X$o%dma_common_l1f013.c$t$dwm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.dma_common_l1f013.h.40.d146a609b72d90beef1aca4a3724028bdma_channel_resetdma_clear_interrupt_flagsdma_get_interrupt_flagdma_enable_mem2mem_modedma_set_prioritydma_set_memory_sizedma_set_peripheral_sizedma_enable_memory_increment_modedma_disable_memory_increment_modedma_enable_peripheral_increment_modedma_disable_peripheral_increment_modedma_enable_circular_modedma_set_read_from_peripheraldma_set_read_from_memorydma_enable_transfer_error_interruptdma_disable_transfer_error_interruptdma_enable_half_transfer_interruptdma_disable_half_transfer_interruptdma_enable_transfer_complete_interruptdma_disable_transfer_complete_interruptdma_enable_channeldma_disable_channeldma_set_peripheral_addressdma_set_memory_addressdma_get_number_of_datadma_set_number_of_data> DDDA"C&B-D4D;DBDGDTDYDfDkDxDDDD;??D??DD9?? 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IB:!; 9 I H} I~ .?:!; 9 'I@z % Uy $ > .?: ;9 'I@z.?: ; 9 '@z2P p p}QQP p p} PQQPp p~ PQQP p p~ PQQPp p~ $PQ$QR$R SRPp p~ $PQ$QR$R SRPp p~ PQQRRS RPp p~ PQQP p p~ PQQPPQQP p~Q QP p PQQPPQQPPQQP PQ Q R RSRPPQQPPQQP PQ Q R RSRP PQ Q R RSRPPQQPPQQP PQ QPPQQRR SRPPQQ    $$     $$?@C*m # c<X 0\bS'd._@..*HBQ4{@`EA a6{<h 8= tFMQMG<9IF4<*XQ}R\D6aGM-?G8+ZZ P(P/ ;HFahQeAg>1\[]+S*U0S2 A% |[E4`PS#oV)IUz,/D/&&H'EB;\F_%{W ,)#|[OR(Dh-W,;AH ]X@   JN21 13 ;I:j++%1.d:9 F!0}EQ ~$3):>5L`PB_).T\8(SN#[=W:]W@ /Bk"*2\F-C. ?"sP)`S69-X]0" T[  3 .3VM:99E:_H>(5#K??+q,X5"6) %"%0EQ,7$Bau5!1v4SB(,<p> `-NC!My1E3!mYB+D)4gWL<SI]D;*A)Y'7s*2u;M%_`'(344?]1Fc97C;LL 0At]n< 2*?;Nd%G96\PO#L'Q_$SQ~a ,IW+LT !WJ")$6Bde-ff=g5Cjkn2oe$p!Lq%t3u"x]Dy0z\{X~%u 5O=*- F;X8C<[>B*hT; RSFq ^B(ES: &&(w.>`R]_+N0+ I1R562X>@6]/jN3,#^_H[AeB[ 0vJ-_QaT@;1UOWG  PhdP a' K&{` ^0]=Y!}#&='-!2]C #Dd0E%F#I $LQR.TSRT1UV"TWj2XmY%UZO[2 \B]Z^_)`Ca[byc+dDee*fDg-\h+il,jREk]lm-n1Go,p&F[,*!.3/4v255697$89'::; "?P@V!CH DLE9SF@GHd3IJJLJM7NIOPQ{T;UFVWI@XU[\G ]4 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1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)DMAMUX2_CxCR(dma_channel) DMAMUX_CxCR(DMAMUX2, (dma_channel))__INTMAX_MAX__ 0x7fffffffffffffffLLDMAMUX_CxCR(dmamux_base,dma_channel) MMIO32((dmamux_base) + 0x04 * ((dma_channel) - 1))__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17DMAMUX_CxCR_DMAREQ_ID_TIM2_TRIG 30__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITdmamux_enable_dma_request_syncsigned charINT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKDMAMUX_CxCR_DMAREQ_ID_TIM3_CH1 32__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 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(-125)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))UINT32_MAX __UINT32_MAX__TIM3_BASE (PERIPH_BASE_APB + 0x0400)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32DMAMUX_RG_CHANNEL2 2__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__dmamux_set_dma_channel_requestDMAMUX_RGxCR_SIG_ID_LPTIM2_OUT 21__SFRACT_EPSILON__ 0x1P-7HRDMAMUX_CxCR_DMAREQ_ID_SPI1_TX 17__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31dmamux_get_dma_channel_requestINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)DMAMUX_CxCR_DMAREQ_ID_MASK 0xff__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)DMAMUX_CxCR_DMAREQ_ID_TIM1_CH1 20__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN0 1__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffDMAMUX_CxCR_DMAREQ_ID_TIM3_TRIG 36DMAMUX_RGxCR_SIG_ID_EXTI_LINE1 1__UINT_FAST16_MAX__ 0xffffffffUDMAMUX_CxCR_SYNC_ID_DMAMUX_EVT1 17LPUART1_BASE (PERIPH_BASE_APB + 0x8000)INT64_C(c) __INT64_C(c)DMAMUX_RGCFR_COF(rg_channel) (1 << ((rg_channel) - 1))__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)DMAMUX_CxCR_DMAREQ_ID_USART4_TX 57__UINT_LEAST8_TYPE__ unsigned charDMAMUX_RGxCR_SIG_ID_MASK 0x1f__ACCUM_FBIT__ 15DMAMUX_CxCR_DMAREQ_ID_I2C2_RX 12__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1DMAMUX_CxCR_DMAREQ_ID_SPI2_TX 19__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32DMAMUX_CxCR_DMAREQ_ID_TIM2_UP 31DMAMUX_CxCR_SYNC_ID_LPTIM2_OUT 21DMAMUX_CxCR_SPOL_MASK 0x03__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charDMAMUX_CxCR_SYNC_ID_DMAMUX_EVT3 19__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRDMAMUX_RGxCR_SIG_ID_RESERVED 23GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)dmamux_reset_dma_channelBIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)USART2_BASE (PERIPH_BASE_APB + 0x4400)sig_idDMAMUX_CxCR_DMAREQ_ID_I2C1_TX 11__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__DMAMUX_RGxCR_SIG_ID_EXTI_LINE11 11__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMAMUX_CxCR_SYNC_ID_EXTI_LINE8 8TIM17_BASE (PERIPH_BASE_APB + 0x14800)DMAMUX_CxCR_DMAREQ_ID_TIM16_CH1 44BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)DMAMUX_CxCR_SYNC_ID_EXTI_LINE3 3DMAMUX_RGxCR_SIG_ID_EXTI_LINE13 13__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9__thumb__ 1LIBOPENCM3_MEMORYMAP_COMMON_H __VERSION__ "12.2.1 20221205"uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)DMAMUX_RGxCR_SIG_ID_EXTI_LINE15 15__GNUC_STDC_INLINE__ 1DMAMUX_CxCR_NBREQ_SHIFT 19__INT64_C(c) c ## LL__FRACT_FBIT__ 15DMAMUX_CxCR_DMAREQ_ID_TIM3_UP 37__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)DMAMUX_CxCR_DMAREQ_ID_TIM1_CH2 21__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5__ARM_ARCH_EXT_IDIV__DMAMUX_CxCR_SYNC_ID_TIM14_OC 22__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))__UINT16_MAX__ 0xffffgnbreqdmamuxTIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32INT_FAST16_MINdmamux_set_request_generator_trigger_pol__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16DMAMUX_CxCR_EGE (1 << 9)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)DMAMUX_RGxCR_SIG_ID_TIM14_OC 22__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2DMAMUX_RGxCR_GPOL_SHIFT 17INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H DMAMUX_RG_CHANNEL3 3DMAMUX_CxCR_DMAREQ_ID_TIM15_UP 43__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__DA_FBIT__ 31DMAMUX_CxCR_DMAREQ_ID_TIM7_UP 39__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffDMAMUX_CxCR_SYNC_ID_SHIFT 24__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308L__ULLACCUM_EPSILON__ 0x1P-32ULLKCOMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX __INT_LEAST8_MAX__USART3_BASE (PERIPH_BASE_APB + 0x4800)__UACCUM_MIN__ 0.0UKDMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN1 2__FLT_EPSILON__ 1.1920928955078125e-7FDMAMUX_CxCR_SPOL_NO_EVENT 0__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0DMAMUX_RGxCR_SIG_ID_EXTI_LINE2 2DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)DMAMUX_CxCR_SYNC_ID_EXTI_LINE10 10TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT32_HAS_QUIET_NAN__ 1DMAMUX_RGxCR_SIG_ID_EXTI_LINE7 7__LDBL_HAS_INFINITY__ 1DMAMUX_RGxCR(dmamux_base,rg_channel) MMIO32((dmamux_base) + 0x100 + 0x04 * ((rg_channel) - 1))__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_PCS 1DMAMUX_CxCR_DMAREQ_ID_UCPD1_TX 59bool _BoolDMAMUX_CxCR_DMAREQ_ID_USART4_RX 56UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__DMAMUX_CxCR_SYNC_ID_EXTI_LINE14 14SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2DMAMUX_CxCR_DMAREQ_ID_USART2_TX 53__ARM_FEATURE_FP16_FMLDMAMUX_CxCR_DMAREQ_ID_TIM2_CH1 26nbreqINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)DMAMUX_CxCR_SYNC_ID_EXTI_LINE4 4DMAMUX_CxCR_SYNC_ID_LPTIM1_OUT 20UINT64_CDMAMUX_CxCR_DMAREQ_ID_TIM2_CH3 28__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULDMAMUX_CxCR_DMAREQ_ID_TIM17_TRIG_COM 48DMAMUX_CxCR_DMAREQ_ID_RESERVED62 62__INT_LEAST8_MAX__ 0x7fDMAMUX_CxCR_SYNC_ID_EXTI_LINE9 9dmamux_clear_dma_request_sync_overrun__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDMAMUX_RGxCR_GPOL_RISING_EDGE 1DAC_BASE (PERIPH_BASE_APB + 0x7400)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024DMAMUX2_RGSR(dmamux_base) DMAMUX_RSGR(DMAMUX2)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KDMAMUX_RGxCR_SIG_ID_DMAMUX_EVT0 16__INT8_MAX__ 0x7fBIT14 (1<<14)DMAMUX_CxCR_DMAREQ_ID_SPI1_RX 16__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intPERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__DMAMUX_CxCR_DMAREQ_ID_USART3_TX 55INT_FAST32_MIN__FLT32X_MIN__ 2.2250738585072014e-308F32x__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8dmamux_get_request_generator_trigger_overrun_interruptBIT18 (1<<18)UINT_FAST16_MAXchannel__UINT_FAST8_TYPE__ unsigned intDMAMUX_CxCR_DMAREQ_ID_UCPD2_TX 61__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64DMAMUX_CxCR_DMAREQ_ID_SPI2_RX 18DMAMUX_RGxCR_SIG_ID_LPTIM1_OUT 20UINTPTR_MAXDMAMUX_RGxCR_GPOL_BOTH_EDGES 3DMAMUX_CxCR_DMAREQ_ID_TIM1_TRIG_COM 24__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLdmamux_disable_dma_request_event_generation__ULLFRACT_IBIT__ 0DMAMUX_CxCR_DMAREQ_ID_DAC_Channel1 8MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12DMAMUX_RGxCR_OIE (1 << 8)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__TQ_FBIT__ 127__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)DMAMUX_RGxCR_SIG_ID_EXTI_LINE12 12__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8dmamux_disable_dma_request_sync_overrun_interrupt__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)DMAMUX1_RGSR(dmamux_base) DMAMUX_RSGR(DMAMUX1)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long int../common/dmamux.c__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sections__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXSYSCFG_BASE (PERIPH_BASE_APB + 0x10000)DMAMUX_RGxCR_SIG_ID_EXTI_LINE3 3DMAMUX_CxCR_SE (1 << 16)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0DMAMUX1_CSR(dmamux_base) DMAMUX_CSR(DMAMUX1)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__DMAMUX_CxCR_DMAREQ_ID_AES_OUT 7DMAMUX_RGxCR_SIG_ID_EXTI_LINE8 8SYS_TICK_BASE (SCS_BASE + 0x0010)DMAMUX_CxCR_DMAREQ_ID_TIM3_CH2 33DMAMUX_CxCR_DMAREQ_ID_TIM1_CH4 23DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT2 18__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)dmamux_enable_request_generator_trigger_overrun_interruptdmamux_set_dma_request_sync_polSPI2_BASE (PERIPH_BASE_APB + 0x3800)DMAMUX_CxCR_DMAREQ_ID_TIM17_CH1 47DMAMUX_CxCR_DMAREQ_ID_TIM15_CH1 40__INT_FAST32_TYPE__ intDMAMUX_CxCR_DMAREQ_ID_TIM16_UP 46DMAMUX_CxCR_DMAREQ_ID_TIM3_CH4 35unsigned int__GCC_ASM_FLAG_OUTPUTS__DMAMUX_CxCR_SYNC_ID_EXTI_LINE12 12__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKDMAMUX_RGxCR_SIG_ID_EXTI_LINE6 6DMAMUX_CxCR_DMAREQ_ID_TIM3_CH3 34DMAMUX_CxCR_SYNC_ID_EXTI_LINE0 0__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned char__SIG_ATOMIC_TYPE__ intDMAMUX_RGxCR_GPOL_NO_EVENT 0UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINDMAMUX_CxCR_DMAREQ_ID_ADC 5PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)DMAMUX_CxCR_SPOL_FALLING_EDEG 2__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LRDMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN2 3DMAMUX2_CSR(dmamux_base) DMAMUX_CSR(DMAMUX2)UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1DMAMUX2_CFR(dmamux_base) DMAMUX_CFR(DMAMUX2)dmamux_get_dma_request_sync_overrun__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)DMAMUX1 DMAMUX_BASEDMAMUX_CxCR_DMAREQ_ID_AES_IN 6__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)DMAMUX_RGxCR_GPOL_MASK 0x03EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64DMAMUX_CxCR_DMAREQ_ID_TIM17_UP 49__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1DMAMUX_RGxCR_GNBREQ_MASK 0x1f__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT0 16SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__DMAMUX_CxCR_SYNC_ID_RESERVED23 23BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1DMAMUX_CxCR_DMAREQ_ID_UCPD1_RX 58__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)DMAMUX_RGCFR(dmamux_base) MMIO32((dmamux_base) + 0x144)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intDMAMUX_RGxCR_SIG_ID_EXTI_LINE10 10BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 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BCS*D&Gm>HaIL M N'Q-RDSl!VHW,Xg[D\X]J`9WaRb 0eZf=Kgt(*S+_,[Q-I.d\/)07/89T:;VE| ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32/common../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0exti_common_all.cstdint.hexti_common_all.hexti.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hexti.hexti_common_v2.hgpio.hgpio.hgpio_common_f24.hgpio_common_f234.hgpio_common_all.h,h ./ .(!x  .$! .- .>$ 1 ./$ 1 ./ % ! 2    $24w   y< z .@  u 2;!;!!;K#   " : C   C ?.H   q  <l  ,MMIO64(addr) (*(volatile uint64_t *)(addr))GPIOJ_BSRR GPIO_BSRR(GPIOJ)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)EXTI1 (1 << 1)GPIOK_PUPDR GPIO_PUPDR(GPIOK)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1__CHAR_UNSIGNED__ 1__UINTPTR_MAX__ 0xffffffffUSTM32G0 1GPIO_AF2 0x2__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffGPIOD_AFRH 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0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)EXTI_EXTICR_GPIOD 3__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)__UINT8_C(c) c__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64UINT_FAST32_MAXGPIOF_ODR GPIO_ODR(GPIOF)GPIO_AF6 0x6FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)GPIO5 (1 << 5)GPIOI_AFRH GPIO_AFRH(GPIOI)INT_FAST64_MAX __INT_FAST64_MAX__GPIOC_PUPDR GPIO_PUPDR(GPIOC)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64GPIOD_LCKR GPIO_LCKR(GPIOD)GPIOC_AFRL GPIO_AFRL(GPIOC)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intexti_select_sourceINT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38GPIO0 (1 << 0)GPIOG_BSRR GPIO_BSRR(GPIOG)__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZGPIOH GPIO_PORT_H_BASE__ARM_FEATURE_MVEGPIO_AF8 0x8__FLT32_MIN_EXP__ (-125)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))UINT32_MAX __UINT32_MAX__TIM3_BASE (PERIPH_BASE_APB + 0x0400)GPIO_MODE_AF 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0x8000)__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0UR__LDBL_HAS_QUIET_NAN__ 1WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15LIBOPENCM3_GPIO_COMMON_ALL_H __UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__EXTI_IMR1 MMIO32(EXTI_BASE + 0x80)__ARM_FEATURE_SAT__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO9 (1 << 9)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xEXTI0 (1 << 0)EXTI_RTSR1 MMIO32(EXTI_BASE + 0x00)GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIOJ_AFRL GPIO_AFRL(GPIOJ)GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__GPIO_AF1 0x1__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)shiftshort unsigned intRNG_BASE (PERIPH_BASE_AHB + 0x05000)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__EXTICR_SELECTION_FIELDSIZE EXTI_EXTICR_FIELDSIZEGPIO_OSPEED_HIGH 0x2__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32GPIO_AF9 0x9TIM17_BASE (PERIPH_BASE_APB + 0x14800)GPIOB_PUPDR GPIO_PUPDR(GPIOB)BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)UINT64_MAXGPIOH_ODR GPIO_ODR(GPIOH)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9__thumb__ 1__VERSION__ "12.2.1 20221205"uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1EXTI_EXTICR2 MMIO32(EXTI_BASE + 0x64)PTRDIFF_MINEXTI22 (1 << 22)exti_get_flag_statusUINTPTR_MAX __UINTPTR_MAX__INT32_MAXGPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINEXTI_TRIGGER_RISINGEXTI28 (1 << 28)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xEXTI23 (1 << 23)__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5GPIO2 (1 << 2)__ARM_ARCH_EXT_IDIV____FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))GPIO_AF7 0x7GPIO11 (1 << 11)EXTI24 (1 << 24)__FLT64_DECIMAL_DIG__ 17__UINT16_MAX__ 0xffff__TQ_FBIT__ 127TIM14_BASE (PERIPH_BASE_APB + 0x2000)EXTI11 (1 << 11)__USQ_FBIT__ 32INT_FAST16_MIN__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32EXTI_EXTICR_GPIOE 4EXTI25 (1 << 25)SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)GPIOH_AFRH GPIO_AFRH(GPIOH)CEC_BASE (PERIPH_BASE_APB + 0x7800)EXTI27 (1 << 27)UINT_LEAST8_MAXGPIOG_AFRH GPIO_AFRH(GPIOG)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8GPIO_OTYPER(port) MMIO32((port) + 0x04)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIOD_PUPDR GPIO_PUPDR(GPIOD)__USA_IBIT__ 16GPIOB_AFRH GPIO_AFRH(GPIOB)EXTI6 (1 << 6)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)GPIOG_AFRL GPIO_AFRL(GPIOG)exti_disable_request__FLT_MIN__ 1.1754943508222875e-38FGPIOG_ODR GPIO_ODR(GPIOG)__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LGPIOB_MODER GPIO_MODER(GPIOB)__USFRACT_MIN__ 0.0UHRBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H GPIOK_BSRR GPIO_BSRR(GPIOK)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)GPIO8 (1 << 8)GPIO_OSPEED_LOW 0x0GPIOB_AFRL GPIO_AFRL(GPIOB)GPIO_ALL 0xffffEXTI18 (1 << 18)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffGPIOI GPIO_PORT_I_BASE__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LGPIOJ_IDR GPIO_IDR(GPIOJ)GPIOC_ODR GPIO_ODR(GPIOC)GPIOA_LCKR GPIO_LCKR(GPIOA)COMP_BASE (PERIPH_BASE_APB + 0x10200)exti_enable_requestINT_LEAST8_MAX __INT_LEAST8_MAX__GPIOK_ODR GPIO_ODR(GPIOK)USART3_BASE (PERIPH_BASE_APB + 0x4800)EXTI19 (1 << 19)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FGPIO_MODE_MASK(n) (0x3 << (2 * (n)))GPIO_AF0 0x0EXTI_EXTICR_FIELDSIZE 8__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)__FLT32_HAS_QUIET_NAN__ 1GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIO_PUPD_PULLDOWN 0x2GPIO_MODE(n,mode) ((mode) << (2 * (n)))__ARM_PCS 1GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX__EXTI37 (1 << 5)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX__GPIOD_MODER GPIO_MODER(GPIOD)SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)EXTI_IMR EXTI_IMR1GPIOF_BSRR GPIO_BSRR(GPIOF)exti_set_triggerLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXGPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLLIBOPENCM3_EXTI_COMMON_V2_H INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRGPIOH_LCKR GPIO_LCKR(GPIOH)__USFRACT_FBIT__ 8SPI2_BASE (PERIPH_BASE_APB + 0x3800)GPIOK_IDR GPIO_IDR(GPIOK)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIO_PUPD_MASK(n) (0x3 << (2 * (n)))GPIOK_AFRH GPIO_AFRH(GPIOK)__INT_LEAST8_MAX__ 0x7fGPIO_OTYPE_OD 0x1__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)DAC_BASE (PERIPH_BASE_APB + 0x7400)GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)EXTI5 (1 << 5)extis__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIOF_AFRL GPIO_AFRL(GPIOF)PERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned intEXTI10 (1 << 10)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)GPIO_AF11 0xb__INT32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0lineUINTMAX_MAXGPIO13 (1 << 13)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__EXTI_EXTICR_GPIOA 0INT8_MAX __INT8_MAX__BIT28 (1<<28)trig__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1GPIOF_BRR GPIO_BRR(GPIOF)/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3../common/exti_common_all.cUINT_FAST8_MAX__FLT_MANT_DIG__ 24EXTI_EXTICR_GPIOF 5__UDQ_IBIT__ 0GPIOK_AFRL GPIO_AFRL(GPIOK)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAXEXTI_EXTICR1 MMIO32(EXTI_BASE + 0x60)EXTI_FPR1 MMIO32(EXTI_BASE + 0x10)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLGPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXEXTI30 (1 << 30)EXTI36 (1 << 4)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FPGPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1EXTI20 (1 << 20)CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))maskGPIOC GPIO_PORT_C_BASEGPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXGPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASEGPIOE_MODER GPIO_MODER(GPIOE)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16GPIO_AF5 0x5__UDQ_FBIT__ 64exti_reset_requestGPIO6 (1 << 6)LIBOPENCM3_EXTI_H GPIOD_ODR GPIO_ODR(GPIOD)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)EXTI_RTSR EXTI_RTSR1__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intEXTI31 (1 << 31)__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1EXTI4 (1 << 4)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)ADC1_BASE (PERIPH_BASE_APB + 0x12400)GPIO_OSPEED_25MHZ 0x1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKEXTI_SWIER1 MMIO32(EXTI_BASE + 0x08)__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)GPIO4 (1 << 4)EXTI_FTSR EXTI_FTSR1__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8EXTI12 (1 << 12)INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4bits__STDC__ 1EXTI26 (1 << 26)__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charEXTI13 (1 << 13)__SIG_ATOMIC_TYPE__ intUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LRGPIOI_PUPDR GPIO_PUPDR(GPIOI)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)GPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__DA_FBIT__ 31DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)GPIOE_AFRL GPIO_AFRL(GPIOE)GPIOD_OTYPER GPIO_OTYPER(GPIOD)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32GPIOC_MODER GPIO_MODER(GPIOC)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX____USQ_IBIT__ 0EXTI_EXTICR_GPIOB 1BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)EXTI35 (1 << 3)__DBL_MIN_EXP__ (-1021)GPIOA GPIO_PORT_A_BASE__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1GPIO1 (1 << 1)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)GPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)EXTI_EXTICR4 MMIO32(EXTI_BASE + 0x6c)GPIO_LCKK (1 << 16)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)GPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intGPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)GPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0LIBOPENCM3_MEMORYMAP_COMMON_H BIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15EXTI3 (1 << 3)GPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffGPIO_PUPDR(port) MMIO32((port) + 0x0c)PTRDIFF_MAX __PTRDIFF_MAX__EXTI16 (1 << 16)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)GPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)GPIOK_LCKR GPIO_LCKR(GPIOK)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)EXTI32 (1 << 0)EXTI_EMR1 MMIO32(EXTI_BASE + 0x84)CORESIGHT_LSR_SLK (1<<1)GPIOC_AFRH GPIO_AFRH(GPIOC)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIOB_LCKR GPIO_LCKR(GPIOB)__FLT32_MIN__ 1.1754943508222875e-38F32GPIOA_MODER GPIO_MODER(GPIOA)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1GPIOE GPIO_PORT_E_BASEDMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)GPIOE_OTYPER GPIO_OTYPER(GPIOE)__QQ_IBIT__ 0EXTI_EXTICR3 MMIO32(EXTI_BASE + 0x68)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__GNUC_MINOR__ 2GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))EXTI7 (1 << 7)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1GPIO_OSPEED_2MHZ 0x0GPIOA_BSRR GPIO_BSRR(GPIOA)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INT_LEAST8_MININTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)GPIOB GPIO_PORT_B_BASE__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULREXTI34 (1 << 2)__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)gpioportGPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16EXTI_TRIGGER_FALLINGGPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0LIBOPENCM3_GPIO_H GPIO_AF12 0xcshort int__UINT16_C(c) c__UDA_IBIT__ 32UINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)BIT2 (1<<2)EXTI9 (1 << 9)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)GPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)CORESIGHT_LSR_SLI (1<<0)BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)__ULACCUM_FBIT__ 32INT16_C(c) __INT16_C(c)EXTICR_SELECTION_REG(x) EXTI_EXTICR(x)GPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fffEXTI_EXTICR_GPIOC 2__INT_WIDTH__ 32GPIOJ GPIO_PORT_J_BASEGPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)EXTI_EXTICR_GPIOH 7GPIO_AFRL(port) MMIO32((port) + 0x20)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32GPIO10 (1 << 10)GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRGPIOH_IDR GPIO_IDR(GPIOH)GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__INT_LEAST32_MAX__ 0x7fffffffLEXTI_TRIGGER_BOTH__LDBL_DECIMAL_DIG__ 17EXTI_EXTICR(i) MMIO32(EXTI_BASE + 0x60 + (i)*4)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32EXTI21 (1 << 21)GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__UINT_FAST16_TYPE__ unsigned intGPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15GPIO_AF15 0xfUINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308GPIOD_BRR GPIO_BRR(GPIOD)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1GPIO15 (1 << 15)GPIOH_OTYPER GPIO_OTYPER(GPIOH)__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUEXTI15 (1 << 15)EXTI2 (1 << 2)EXTI33 (1 << 1)__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1EXTI29 (1 << 29)GPIO_OSPEED_100MHZ 0x3INT_LEAST64_MINPTRDIFF_MAX__LLFRACT_EPSILON__ 0x1P-63LLREXTI_EMR EXTI_EMR1__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53GPIO_BSRR(port) MMIO32((port) + 0x18)__ARM_ASM_SYNTAX_UNIFIED__EXTI14 (1 << 14)WINT_MAX__INT16_C(c) cEXTI_IMR2 MMIO32(EXTI_BASE + 0x90)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32EXTI17 (1 << 17)GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4EXTI8 (1 << 8)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)GPIOA_BRR GPIO_BRR(GPIOA)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__INT_MAX__ 0x7fffffff__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)EXTI_EXTICR_GPIOG 6INT_FAST16_MAXGPIOF GPIO_PORT_F_BASE__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)IWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCGPIOJ_PUPDR GPIO_PUPDR(GPIOJ)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | @     D A+aeabi!6S-M M 8 l!?A#%')+-/13579;=C@q9m   I  BE     @':Oexti_common_all.c$t$dwm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.exti_common_all.h.29.0c2e2fc3a4fa73c9d031cf0c9c76f7e0wm4.exti_common_v2.h.31.9e493934194aa272a6bdd3bd7756fa25wm4.exti.h.36.28824772b3b5c32226b642a9b9b8eba5wm4.gpio_common_all.h.37.fedbbcb9179f773c905aa3c3e4b7dbddwm4.gpio_common_f234.h.48.1db4d0a0536896711e20c0a147f92021wm4.gpio_common_f24.h.48.d7799bf98ecad7663b4b299525c33e1bwm4.gpio.h.42.6c8c835b288f416747d6ca42963eecafexti_set_triggerexti_enable_requestexti_disable_requestexti_reset_requestexti_get_flag_statusexti_select_source "&-4;BGT[`mt (,<@GRakouz '?Xk  (08  &, 28> !'"-#7@H$N%Ya&j'p(~)*+, #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ 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"C#H$,:%-&!'(I=)J*@+#,]-v/.0/20H1:2J345l)6bE789:;]08I?}(@n-B;CHDF?EW5F(Gk&' '1*D+...1) 2569.J;@A$B4CBDEF%GKHC$pD%$&&'I(J6+ -J& z ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32/commonexti_common_v2.cstdint.hexti.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hexti.hexti_common_all.hexti_common_v2.h$ !  !. !  !8 ! ! ! !MMIO64(addr) (*(volatile uint64_t *)(addr))SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1__UINTPTR_MAX__ 0xffffffffUSTM32G0 1__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 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0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)INT64_C(c) __INT64_C(c)FLASH_CR_FSTPG (1 << 18)FLASH_ACR_ICRST (1 << 11)flash_erase_page__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URFLASH_OPTR_RAM_PARITY_CHECK (1 << 22)WCHAR_MAX __WCHAR_MAX__flash_lock_progmemUINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17FLASH_OPTR_RDP_LEVEL_2 0xCC__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULLFLASH_OPTR_IRHEN (1 << 29)__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN____SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)FLASH_CR_OPTSTRT (1 << 17)flash_wait_for_last_operationTIM17_BASE (PERIPH_BASE_APB + 0x14800)BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9__thumb__ 1LIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1FLASH_CR_EOPIE (1 << 24)__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77FLASH_SR_PROGERR (1 << 3)__FLT64_MAX_10_EXP__ 308FLASH_OPTR_IWDG_STOP (1 << 17)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINFLASH_OPTR_RDP_LEVEL_1 0xBB__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38FLASH_OPTR_BORR_LEV_2V1 0__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)flash_clear_progerr_flag__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5LIBOPENCM3_FLASH_H __ARM_ARCH_EXT_IDIV__FLASH_SR_RDERR (1 << 14)__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))__UINT16_MAX__ 0xffff__TQ_FBIT__ 127FLASH_KEYR_KEY1 ((uint32_t)0x45670123)TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32INT_FAST16_MINFLASH_SR_OPTVERR (1 << 15)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)__LACCUM_EPSILON__ 0x1P-31LKUINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16flash_icache_enablePTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)FLASH_OPTR_NRST_MODE_MASK 0x03__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRTAMP_BASE (PERIPH_BASE_APB + 0xB000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H __DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)__DA_FBIT__ 31flash_icache_reset__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308L__ULLACCUM_EPSILON__ 0x1P-32ULLKCOMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX __INT_LEAST8_MAX__USART3_BASE (PERIPH_BASE_APB + 0x4800)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FFLASH_OPTR_NRST_MODE_SHIFT 27__ARM_ARCH_ISA_THUMBFLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)__ARM_FEATURE_MATMUL_INT8__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1FLASH_OPTR_NRST_MODE_BIDIR 3FLASH_OPTR_NRST_MODE_GPIO 2__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63BIT1 (1<<1)MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_PCS 1bool _BoolFLASH_OPTR_BORR_LEV_MASK 0x03UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffflash_lockBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)FLASH_PCROP1BER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLFLASH_OPTR_nRST_STDBY (1 << 14)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)FLASH_OPTR_BORF_LEV_2V2 1__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7fFLASH_SR_EOP (1 << 0)__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)FLASH_ACR_PRFTEN (1 << 8)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KFLASH_OPTR_NRST_MODE_RESET 1__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intflash_clear_eop_flagPERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0address__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLFLASH_OPTR_nRST_STOP (1 << 13)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__FLASH_ACR_ICEN (1 << 9)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0FLASH_SR_FASTERR (1 << 9)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64FLASH_OPTR_BORF_LEV_MASK 0x03UINTPTR_MAXFLASH_CR_OBL_LAUNCH (1 << 27)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ULLFRACT_IBIT__ 0FLASH_OPTR_WWDG_SW (1 << 19)MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKFLASH_CR_RDERRIE (1 << 26)__ARM_ARCH 6flash_clear_status_flags__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)flash_program_double_word__UINT_FAST64_MAX__ 0xffffffffffffffffULLflash_clear_operr_flag__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024FLASH_OPTR_RDP_SHIFT 0UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsFLASH_SR_BSY (1 << 16)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXflash_clear_wrperr_flagINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0FLASH_CR_PNB_MASK 0x3fFLASH_ECCR_ECCD (1 << 31)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)__INT_FAST32_TYPE__ intunsigned int__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8FLASH_CR_PNB_SHIFT 3ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKFLASH_CR_OPTLOCK (1 << 30)FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)__FLT_EVAL_METHOD__ 0FLASH_OPTR_RDP_LEVEL_0 0xAA__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charFLASH_CR_STRT (1 << 16)__SIG_ATOMIC_TYPE__ intUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINFLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LRpage__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)__ARM_FP16_FORMAT_ALTERNATIVEFLASH_SR_OPERR (1 << 1)__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64FLASH_OPTR_BORR_LEV_2V3 1__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__FLASH_ECCR_SYSF_ECC (1 << 20)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2FLASH_ACR_LATENCY_SHIFT 0BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234DESIG_UNIQUE_ID_BASE (0x1FFF7590)__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intFLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0INT_LEAST8_MINFLASH_PCROP1AER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28)BIT29 (1<<29)__INT_FAST16_TYPE__ intFLASH_OPTR_BORR_LEV_2V6 2FLASH_SR_PGAERR (1 << 5)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRFLASH_ACR_DBG_SWEN (1 << 18)__UINT_LEAST16_TYPE__ short unsigned intFLASH_PCROP1BSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34)__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128FLASH_SR_WRPERR (1 << 4)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffflash_unlock_progmemPTRDIFF_MAX __PTRDIFF_MAX__FLASH_ACR_LATENCY_0WS 0x00FLASH_PCROP1ASR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRFLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intFLASH_ECCR_ECCIE (1 << 24)FLASH_OPTR_IWDG_STDBY (1 << 18)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)FLASH_CR_ERRIE (1 << 25)WCHAR_MINFLASH_OPTR_BORF_LEV_2V8 3BEGIN_DECLS FLASH_SR_MISERR (1 << 8)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)FLASH_OPTR_RDP_MASK 0xff__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xFLASH_CR_SEC_PROT (1 << 28)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)__QQ_IBIT__ 0FLASH_OPTR_nBOOT_SEL (1 << 24)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINflash_unlock_option_bytes__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)FLASH_CR_PG (1 << 0)FLASH_SR_CFGBSY (1 << 18)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)FLASH_ACR_EMPTY (1 << 16)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CFLASH_ECCR_ADDR_ECC_MASK 0x3fffINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)FLASH_OPTR_BORF_LEV_SHIFT 9__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0short int__UINT16_C(c) cuint64_t__UDA_IBIT__ 32UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)FLASH_ACR_LATENCY_MASK 0x7USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)FLASH_OPTR_BORR_LEV_2V9 3INT16_C(c) __INT16_C(c)FLASH_CR_MER (1 << 2)__INT16_MAX__ 0x7fff__INT_WIDTH__ 32__QQ_FBIT__ 7FLASH_OPTR_nBOOT1 (1 << 25)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLR__SIZEOF_WINT_T__ 4__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17flash.c__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODFLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H __GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKFLASH_OPTR_nBOOT0 (1 << 26)flash_unlock__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINFLASH_OPTR_IDWG_SW (1 << 16)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 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D!H.symtab.strtab.shstrtab.text.data.bss.text.flash_prefetch_enable.text.flash_prefetch_disable.text.flash_set_ws.text.flash_unlock_option_bytes.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.groupG4 2"G@ 2#GL 2$GX 2%Gd 2&Gp 2'G| 2(G 2)!',Hex @ :!; 9 I.?:!; 9 '@z:!; 9 IB:!; 9!I1B% Uy$ >  4: ; 9 I .?: ; 9 'I  : ; 9 I 4: ; 9 IB .?: ; 9 'I@z1RB X Y W .1@zz Q QRPPPQQPPL3?@** L %1) %C) 08 U.oQN"Mo]%V,X$,OD4>_IKK13<7At 3b8o  9KB~HQHC8E18X(R_KUd@Z CH!+3.C5k)-TCqJJW6BZK;=.cU2UV;)(cO5./, b=Q T?l1*ZhHM!PA'NO)-i$}$ %=UnMX#XQF .*)&"9L<&@ +Q6fD Q:R;  { L0a 0hu7 6)#1/x,`65AlG.TA7&':GPZ K>-Y,NU4}^&!MITc9|0VPQ;a-> /3B*,?2;`8JY3*Q V  NRU S !1q.,C1(PI6/5AWD%O!c8G:09 R; 6`3'q 1$G$#@)^4= 21=&]:? rZEhCKUS@ JWg-JSP?BVJT5!I QL#@#'T. ,n6  QC B /DT=H)Hy5rP!RO/HV BEc27. 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"t.!!!!%MMIO64(addr) (*(volatile uint64_t *)(addr))GPIOJ_BSRR GPIO_BSRR(GPIOJ)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64GPIOK_PUPDR GPIO_PUPDR(GPIOK)CORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1STM32G0 1GPIO_AF2 0x2__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffGPIO_PUPD_MASK(n) (0x3 << (2 * (n)))__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITGPIOF_OTYPER GPIO_OTYPER(GPIOF)GPIO_OSPEED(n,speed) ((speed) << (2 * (n)))signed charINT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKGPIO_OSPEED_25MHZ 0x1__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intgpios__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)__UINT8_C(c) c__CHAR32_TYPE__ long unsigned int__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64UINT_FAST32_MAXGPIOF_ODR GPIO_ODR(GPIOF)GPIO_AF6 0x6FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)GPIO5 (1 << 5)GPIOI_AFRH GPIO_AFRH(GPIOI)INT_FAST64_MAX __INT_FAST64_MAX__gpio_clearGPIOC_PUPDR GPIO_PUPDR(GPIOC)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64GPIOC_AFRL GPIO_AFRL(GPIOC)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intINT32_MIN (-INT32_MAX - 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GPIO_PUPDR(GPIOJ)GPIO_AF10 0xa__INT_FAST16_WIDTH__ 32INTMAX_C__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffff__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)GPIOC_AFRH GPIO_AFRH(GPIOC)GPIOB GPIO_PORT_B_BASE__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15GPIO_ALL 0xffff__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__GPIOH_AFRH GPIO_AFRH(GPIOH)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO9 (1 << 9)__UFRACT_EPSILON__ 0x1P-16URGPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIOJ_AFRL GPIO_AFRL(GPIOJ)GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__GPIO_AF1 0x1__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX__gpio_getSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__GPIO_OSPEED_HIGH 0x2__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)GPIO_AF9 0x9TIM17_BASE (PERIPH_BASE_APB + 0x14800)GPIOB_PUPDR GPIO_PUPDR(GPIOB)BIT27 (1<<27)TIM7_BASE (PERIPH_BASE_APB + 0x1400)__LFRACT_MAX__ 0X7FFFFFFFP-31LRGPIOH_ODR GPIO_ODR(GPIOH)__UTA_FBIT__ 64__FLT_DECIMAL_DIG__ 9__thumb__ 1LIBOPENCM3_MEMORYMAP_COMMON_H __VERSION__ "12.2.1 20221205"INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1LIBOPENCM3_GPIO_COMMON_ALL_H __FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKGPIO4 (1 << 4)PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINGPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)GPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))__UINT_FAST32_TYPE__ unsigned intunsigned charGPIO10 (1 << 10)__SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5__ARM_ARCH_EXT_IDIV____FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))GPIO_AF7 0x7GPIO11 (1 << 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8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)__FLT32_HAS_QUIET_NAN__ 1GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIOJ_IDR GPIO_IDR(GPIOJ)GPIO_MODE(n,mode) ((mode) << (2 * (n)))__ARM_PCS 1GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX__GPIOD_MODER GPIO_MODER(GPIOD)SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)GPIOF_BSRR GPIO_BSRR(GPIOF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXGPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)UINT64_C__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIOK_AFRH GPIO_AFRH(GPIOK)INT64_C(c) __INT64_C(c)__INT_LEAST8_MAX__ 0x7fGPIO_OTYPE_OD 0x1__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)DAC_BASE (PERIPH_BASE_APB + 0x7400)GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIOF_AFRL GPIO_AFRL(GPIOF)PERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)../common/gpio_common_all.c__INT32_MAX__ 0x7fffffffL__INT64_C(c) c ## LLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24GPIOC GPIO_PORT_C_BASE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIOH_LCKR GPIO_LCKR(GPIOH)INT8_MAX __INT8_MAX__BIT28 (1<<28)UINT32_MAX __UINT32_MAX____GCC_ATOMIC_CHAR16_T_LOCK_FREE 1GPIOF_BRR GPIO_BRR(GPIOF)/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0GPIOK_AFRL GPIO_AFRL(GPIOK)gpioport__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLGPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16GPIOC_MODER GPIO_MODER(GPIOC)__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULLGPIO2 (1 << 2)GPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsGPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXGPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASE__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16GPIO_AF5 0x5__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)GPIOD_ODR GPIO_ODR(GPIOD)__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intGPIOE_MODER GPIO_MODER(GPIOE)__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIOA GPIO_PORT_A_BASE__SIZEOF_PTRDIFF_T__ 4GPIO13 (1 << 13)__STDC__ 1GPIOK_IDR GPIO_IDR(GPIOK)__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned chargpio_set__SIG_ATOMIC_TYPE__ intUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LRGPIOI_PUPDR GPIO_PUPDR(GPIOI)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)gpio_port_writeGPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)GPIOE_AFRL GPIO_AFRL(GPIOE)GPIOD_OTYPER GPIO_OTYPER(GPIOD)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1GPIO1 (1 << 1)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)GPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)GPIO_AF11 0xbGPIO_LCKK (1 << 16)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAXGPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)END_DECLS __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intGPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)INT_LEAST64_MAX__SACCUM_IBIT__ 8reg32__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15GPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffGPIOK_MODER GPIO_MODER(GPIOK)GPIO_PUPDR(port) MMIO32((port) + 0x0c)PTRDIFF_MAX __PTRDIFF_MAX__GPIO_PUPD_PULLDOWN 0x2__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)gpio_port_readGPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)GPIOK_LCKR GPIO_LCKR(GPIOK)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIOB_LCKR GPIO_LCKR(GPIOB)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1GPIOE GPIO_PORT_E_BASE__ARM_FPDMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)GPIOE_OTYPER GPIO_OTYPER(GPIOE)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1GPIO_OSPEED_2MHZ 0x0GPIOA_BSRR GPIO_BSRR(GPIOA)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)GPIO0 (1 << 0)gpio_toggleportGPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16GPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0LIBOPENCM3_GPIO_H GPIO_AF12 0xcshort int__UINT16_C(c) c__UDA_IBIT__ 32UINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)GPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)BIT5 (1<<5)__GNUC_PATCHLEVEL__ 1BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)GPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fff__INT_WIDTH__ 32GPIOJ GPIO_PORT_J_BASEGPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)GPIO_AFRL(port) MMIO32((port) + 0x20)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRGPIOH_IDR GPIO_IDR(GPIOH)GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__UINT_FAST16_TYPE__ unsigned intGPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15GPIO_AF15 0xfGPIO6 (1 << 6)__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308GPIOD_BRR GPIO_BRR(GPIOD)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1GPIO15 (1 << 15)GPIOH_OTYPER GPIO_OTYPER(GPIOH)__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SAT__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1GPIO_OSPEED_100MHZ 0x3INT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__LLFRACT_EPSILON__ 0x1P-63LLR__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53GPIO_BSRR(port) MMIO32((port) + 0x18)__ARM_ASM_SYNTAX_UNIFIED__WINT_MAX__INT16_C(c) cGPIOD_AFRH GPIO_AFRH(GPIOD)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4GPIO_OTYPER(port) MMIO32((port) + 0x04)__DBL_MIN_10_EXP__ (-307)dataGPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)GPIOA_BRR GPIO_BRR(GPIOA)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)INT_FAST16_MAXGPIOF GPIO_PORT_F_BASE__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)IWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |       A+aeabi!6S-M M   79!#%')+-/135;=n6j   :=   HQ\eqgpio_common_all.c$twm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.gpio_common_all.h.37.fedbbcb9179f773c905aa3c3e4b7dbddwm4.gpio_common_f234.h.48.1db4d0a0536896711e20c0a147f92021wm4.gpio_common_f24.h.48.d7799bf98ecad7663b4b299525c33e1bwm4.gpio.h.42.6c8c835b288f416747d6ca42963eecafgpio_setgpio_cleargpio_getgpio_togglegpio_port_readgpio_port_writegpio_port_config_lock "&-4;BINZ_kr $1;?DOSYd s}  ! 04 & 3 H Ul   ( 0 8@   % +1'-7@H N!Ybks"y#$% #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y   #)/5;AGMSY_ekqx  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BC]'D#G:H IL M!N8Q*R@SVDDW,X[J@\R]bF`NQab,efFg*%*@N+Y,K-1E.nV/0E,8B9KO:;)A ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32/commongpio_common_f0234.cstdint.hgpio.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hgpio.hgpio_common_f24.hgpio_common_f234.hgpio_common_all.hx.  y w 6!"   2  = ! !  " !x   .!! $/  %##w # ".1 <! . 6!r  %# #u $!"y(.1 <! . .  #J1 <! . 6!!MMIO64(addr) (*(volatile uint64_t *)(addr))GPIOJ_BSRR GPIO_BSRR(GPIOJ)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__INTMAX_C(c) c ## LL__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64GPIOK_PUPDR GPIO_PUPDR(GPIOK)CORESIGHT_LSR_SLK (1<<1)__CHAR_UNSIGNED__ 1STM32G0 1GPIO_AF2 0x2__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffGPIO_PUPD_MASK(n) (0x3 << (2 * (n)))__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffU__ARM_FEATURE_QBITGPIOF_OTYPER GPIO_OTYPER(GPIOF)GPIO_OSPEED(n,speed) ((speed) << (2 * (n)))INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKGPIO_OSPEED_25MHZ 0x1__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intgpios__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9DESIG_FLASH_SIZE_BASE (0x1FFF75E0)__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 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1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1LIBOPENCM3_GPIO_COMMON_ALL_H __FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKGPIO4 (1 << 4)PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINGPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)pull_up_downGPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))__UINT_FAST32_TYPE__ unsigned intunsigned charGPIO10 (1 << 10)__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5__ARM_ARCH_EXT_IDIV____FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))GPIO_AF7 0x7GPIO11 (1 << 11)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32__USES_INITFINI__ 1__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CEC_BASE (PERIPH_BASE_APB + 0x7800)UINT_LEAST8_MAXINT_LEAST8_MAXGPIOG_AFRH GPIO_AFRH(GPIOG)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIOD_PUPDR GPIO_PUPDR(GPIOD)__USA_IBIT__ 16GPIOB_AFRH GPIO_AFRH(GPIOB)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)moderGPIOG_AFRL GPIO_AFRL(GPIOG)__FLT_MIN__ 1.1754943508222875e-38FGPIOG_ODR GPIO_ODR(GPIOG)__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LGPIOB_MODER GPIO_MODER(GPIOB)__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H GPIOK_BSRR GPIO_BSRR(GPIOK)alt_func_numDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)GPIO8 (1 << 8)GPIO_OSPEED_LOW 0x0GPIOB_AFRL GPIO_AFRL(GPIOB)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffGPIOI GPIO_PORT_I_BASE__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308L__ULLACCUM_EPSILON__ 0x1P-32ULLKGPIOC_ODR GPIO_ODR(GPIOC)GPIOA_LCKR GPIO_LCKR(GPIOA)COMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX __INT_LEAST8_MAX__GPIOK_ODR GPIO_ODR(GPIOK)USART3_BASE (PERIPH_BASE_APB + 0x4800)GPIOD_LCKR GPIO_LCKR(GPIOD)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FGPIO_MODE_MASK(n) (0x3 << (2 * (n)))GPIO_AF0 0x0__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0__HQ_IBIT__ 0DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)__FLT32_HAS_QUIET_NAN__ 1GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIOJ_IDR GPIO_IDR(GPIOJ)otypeGPIO_MODE(n,mode) ((mode) << (2 * (n)))__ARM_PCS 1GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX__GPIOD_MODER GPIO_MODER(GPIOD)SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)speedGPIOF_BSRR GPIO_BSRR(GPIOF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXGPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8ospeedrCORESIGHT_LSR_SLI (1<<0)UINT64_C__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIOK_AFRH GPIO_AFRH(GPIOK)INT64_C(c) __INT64_C(c)../common/gpio_common_f0234.c__INT_LEAST8_MAX__ 0x7fGPIO_OTYPE_OD 0x1__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)DAC_BASE (PERIPH_BASE_APB + 0x7400)GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIOF_AFRL GPIO_AFRL(GPIOF)PERIPH_BASE_APB (PERIPH_BASE + 0x00000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)GPIO_AF11 0xb__INT32_MAX__ 0x7fffffffL__INT64_C(c) c ## LLUINTMAX_MAX__DBL_HAS_DENORM__ 1BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24GPIOC GPIO_PORT_C_BASE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIOH_LCKR GPIO_LCKR(GPIOH)INT8_MAX __INT8_MAX__BIT28 (1<<28)UINT32_MAX __UINT32_MAX____GCC_ATOMIC_CHAR16_T_LOCK_FREE 1GPIOF_BRR GPIO_BRR(GPIOF)/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0GPIOK_AFRL GPIO_AFRL(GPIOK)gpioport__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLGPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))__GNUC__ 12GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16GPIOC_MODER GPIO_MODER(GPIOC)__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULLGPIO2 (1 << 2)GPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))GPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXGPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASE__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_32BIT_STATE__UFRACT_FBIT__ 16GPIO_AF5 0x5__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)GPIOD_ODR GPIO_ODR(GPIOD)gpio_set_output_options__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intGPIOE_MODER GPIO_MODER(GPIOE)__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0__FLT32X_DIG__ 15INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIOA GPIO_PORT_A_BASE__SIZEOF_PTRDIFF_T__ 4GPIO13 (1 << 13)__STDC__ 1GPIOK_IDR GPIO_IDR(GPIOK)__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned char__SIG_ATOMIC_TYPE__ intgpio_set_afUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LRGPIOI_PUPDR GPIO_PUPDR(GPIOI)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)afrhINFO_BASE (0x1fff7500U)GPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVEafrl__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)GPIOE_AFRL GPIO_AFRL(GPIOE)GPIOD_OTYPER GPIO_OTYPER(GPIOD)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1GPIO1 (1 << 1)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)GPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)GPIO_LCKK (1 << 16)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAXGPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)END_DECLS __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intGPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intgpio_mode_setupGPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffGPIO_PUPDR(port) MMIO32((port) + 0x0c)PTRDIFF_MAX __PTRDIFF_MAX__INT8_CGPIO_PUPD_PULLDOWN 0x2__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)GPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)GPIOK_LCKR GPIO_LCKR(GPIOK)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIOB_LCKR GPIO_LCKR(GPIOB)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1GPIOE GPIO_PORT_E_BASE__ARM_FPDMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)GPIOE_OTYPER GPIO_OTYPER(GPIOE)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1GPIO_OSPEED_2MHZ 0x0GPIOA_BSRR GPIO_BSRR(GPIOA)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intuint16_tI2C2_BASE (PERIPH_BASE_APB + 0x5800)GPIO0 (1 << 0)GPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16GPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0LIBOPENCM3_GPIO_H GPIO_AF12 0xcINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)short int__UINT16_C(c) c__UDA_IBIT__ 32modeUINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)GPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)BIT5 (1<<5)__GNUC_PATCHLEVEL__ 1BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)BIT26 (1<<26)INT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__SIZEOF_FLOAT__ 4__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)GPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fff__INT_WIDTH__ 32GPIOJ GPIO_PORT_J_BASEGPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)GPIO_AFRL(port) MMIO32((port) + 0x20)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRGPIOH_IDR GPIO_IDR(GPIOH)GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__UINT_FAST16_TYPE__ unsigned intGPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15GPIO_AF15 0xfGPIO6 (1 << 6)__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308GPIOD_BRR GPIO_BRR(GPIOD)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1GPIO15 (1 << 15)GPIOH_OTYPER GPIO_OTYPER(GPIOH)__HQ_FBIT__ 15__bool_true_false_are_defined 1pupd__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SAT__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1GPIO_OSPEED_100MHZ 0x3INT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__LLFRACT_EPSILON__ 0x1P-63LLR__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53GPIO_BSRR(port) MMIO32((port) + 0x18)__ARM_ASM_SYNTAX_UNIFIED__WINT_MAX__INT16_C(c) cGPIOD_AFRH GPIO_AFRH(GPIOD)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4GPIO_OTYPER(port) MMIO32((port) + 0x04)__DBL_MIN_10_EXP__ (-307)GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)GPIOA_BRR GPIO_BRR(GPIOA)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)INT_FAST16_MAXGPIOF GPIO_PORT_F_BASE__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)IWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | @AA( <A  XA A+aeabi!6S-M M   35!#%')+-/17?p8l   69   J@Z<rXgpio_common_f0234.c$twm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.gpio_common_all.h.37.fedbbcb9179f773c905aa3c3e4b7dbddwm4.gpio_common_f234.h.48.1db4d0a0536896711e20c0a147f92021wm4.gpio_common_f24.h.48.d7799bf98ecad7663b4b299525c33e1bwm4.gpio.h.42.6c8c835b288f416747d6ca42963eecafgpio_mode_setupgpio_set_output_optionsgpio_set_af "&-4;BGTYfkx           $1; ? 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"J" ! /KKKp. ! /KKK =RCC_CCIPR_RNGDIV_2 1i2c_busyRCC_CR_HSEBYP (1 << 18)RCC_AHBSMENR_DMASMEN (1 << 0)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8RCC_CCIPR_I2C1SEL_MASK 0x3I2C_CR2_STOP (1 << 14)RCC_CCIPR_USART1SEL_PCLK 0PERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_SR1_WUF1 (1 << 0)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__INTMAX_C(c) c ## LL__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)CORESIGHT_LSR_SLK (1<<1)PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1size_tRCC_CSR_LSION (1 << 0)STM32G0 1RCC_CCIPR_RNGSEL_SYSCLK 2I2C_CR1_ALERTEN (1 << 22)__FLT64_HAS_INFINITY__ 1rcc_periph_reset_pulsePWR_CR2_PVDFT_2V5 0x03i2c_set_write_transfer_dir__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffPWR_SR2_REGLPF (1 << 9)RCC_AHBSMENR_RNGSMEN (1 << 18)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sections__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0LIBOPENCM3_I2C_COMMON_V2_H __FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAXRCC_IOPENR_OFFSET 0x34__ATOMIC_CONSUME 1__LFRACT_MIN__ (-0.5LR-0.5LR)__WCHAR_MAX__ 0xffffffffURCC_AHBRSTR_DMARST (1 << 0)___int_ptrdiff_t_h RCC_APBRSTR2_TIM15RST (1 << 16)_WCHAR_T_H RCC_BDCR MMIO32(RCC_BASE + 0x5c)RCC_APBSMENR1_PWRSMEN (1 << 28)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)RCC_CR_PLLRDY (1 << 25)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKi2c_set_7bit_address__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64h_time__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0rcc_periph_rst__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHKI2C_PECR(i2c_base) MMIO32((i2c_base) + 0x20)__FLT32_DECIMAL_DIG__ 9__GCC_ATOMIC_LLONG_LOCK_FREE 1__DECIMAL_DIG__ 17i2c_disable_txdmaUINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)WWDG_BASE (PERIPH_BASE_APB + 0x2c00)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64RCC_PLLCFGR_PLLP_MASK 0x1fPWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)RCC_CFGR_MCO_HSE 0x4PWR_CR3_EIWUL (1 << 15)LIBOPENCM3_I2C_H I2C_TIMINGR_SCLDEL_SHIFT 20FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0RCC_CFGR_PPRE_MASK 0x7INT_FAST64_MAX __INT_FAST64_MAX__I2C_ICR_OVRCF (1 << 10)I2C_CR2_PECBYTE (1 << 26)RCC_BDCR_LSEDRV_SHIFT 3I2C_CR2_HEAD10R (1 << 12)__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)RCC_CICR_LSECSSC (1 << 9)__GXX_ABI_VERSION 1017RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intRCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR1_OFFSET 0x4c__SIZE_T__ INT32_MIN (-INT32_MAX - 1)RCC_CCIPR_RNGSEL_NONE 0__FLT32_MAX_10_EXP__ 38RCC_AHBENR_CRCEN (1 << 12)I2C_ISR_ADDR (1 << 3)RCC_CFGR_SW_PLLRCLK 0x2RCC_APBENR1_DBGEN (1 << 27)__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZ__UINTPTR_MAX__ 0xffffffffURCC_CCIPR_ADCSEL_HSI16 2__need_wchar_t__FLT32_MIN_EXP__ (-125)RCC_CCIPR_I2S1SEL_HSI16 2ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))RCC_APBSMENR1_UCPD2SMEN (1 << 26)RCC_CFGR_MCOPRE_DIV1 0PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8)UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)__WCHAR_T __WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)slave__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_APBRSTR1_SPI2RST (1 << 14)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)I2C_TIMINGR(i2c_base) MMIO32((i2c_base) + 0x10)RCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRRCC_AHBRSTR_CRCRST (1 << 12)RCC_CFGR_HPRE_SHIFT 8_T_SIZE __INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RST_SYSCFGRCC_APBSMENR1_USART2SMEN (1 << 17)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)RCC_CCIPR_LPTIM1SEL_MASK 0x3__DEFINED_ptrdiff_t I2C_CR1_DNF_MASK 0xFINTPTR_MAX__UHQ_FBIT__ 16RCC_AHBSMENR_FLASHSMEN (1 << 8)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)PWR_SR2_VOSF (1 << 10)I2C_OAR1_OA1EN_ENABLE (0x1 << 15)UINT16_C(c) __UINT16_C(c)PWR_CR1_FPD_STOP (1 << 3)__LACCUM_IBIT__ 32_SIZE_T_DEFINED RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_SCR_CWUF2 (1 << 1)I2C_CR2_NBYTES_SHIFT 16__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_C__VERSION__ "12.2.1 20221205"LIBOPENCM3_RCC_COMMON_ALL_H __VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXPWR_SR2_PVDO (1 << 11)__UINT_FAST16_MAX__ 0xffffffffURCC_CCIPR_TIM15SEL_MASK 0x1LPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CCIPR_TIM1SEL_MASK 0x1i2c_set_data_hold_timeRCC_CCIPR_USART1SEL_SHIFT 0RCC_APBRSTR2_ADCRST (1 << 20)I2C_CR1_ADDRIE (1 << 3)__GCC_IEC_559_COMPLEX 0I2C_CR1_NACKIE (1 << 4)__UFRACT_MIN__ 0.0URi2c_send_startRCC_APBSMENR1_RTCAPBSMEN (1 << 10)I2C_ISR_TXIS (1 << 1)WCHAR_MAX __WCHAR_MAX__RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)PWR_CR3_EWUP2 (1 << 1)__UINT_LEAST8_TYPE__ unsigned charPWR_CR2_PVDRT_MASK 0x07RCC_APBRSTR2_TIM17RST (1 << 18)__ACCUM_FBIT__ 15RCC_APBRSTR1_TIM2RST (1 << 0)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)PWR_CR2_PVDRT_2V2 0x01__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_CCIPR_LPUART1SEL_HSI16 2RCC_APBSMENR1_LPTIM2SMEN (1 << 30)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__size_t__ RCC_APBENR2_SPI1EN (1 << 12)__FLT64_MAX_10_EXP__ 308RCC_APBENR2_OFFSET 0x40__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_APBSMENR1_LPUART1SMEN (1 << 20)I2C2_TXDR I2C_TXDR(I2C2)__GCC_ATOMIC_BOOL_LOCK_FREE 1PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_APBSMENR2_OFFSET 0x50__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHBENR_DMAEN (1 << 0)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)RCC_APBENR1_LPUART1EN (1 << 20)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)_T_WCHAR BIT7 (1<<7)BIT17 (1<<17)__LDBL_MIN_EXP__ (-1021)RCC_APBENR1_I2C1EN (1 << 21)_SIZE_T_DECLARED UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)I2C_CR1_TCIE (1 << 6)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffUI2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c)__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__RCC_CFGR_SW_HSISYS 0x0RCC_APBRSTR1_TIM7RST (1 << 5)PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)RCC_CCIPR_RNGDIV_1 0__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RST_CRC__FLT32X_MIN_EXP__ (-1021)RCC_AHBRSTR_OFFSET 0x28RCC_AHBRSTR_AESRST (1 << 16)RCC_CFGR_MCO_SHIFT 24RCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_ICSCR MMIO32(RCC_BASE + 0x04)BIT27 (1<<27)RCC_APBENR1_SPI2EN (1 << 14)I2C_OAR1_OA1MODE_10BIT 1RCC_CICR_PLLRDYC (1 << 5)RCC_CCIPR_USART2SEL_SHIFT 2I2C_TIEMOUTR_TEXTEN (1 << 31)RCC_CCIPR_LPTIM2SEL_SHIFT 20__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_APBENR1_UCPD1EN (1 << 25)__FLT_DECIMAL_DIG__ 9PWR_CR2_PVDRT_3V0 0x06__thumb__ 1I2C_OAR1_OA1EN_DISABLE (0x0 << 15)LIBOPENCM3_MEMORYMAP_COMMON_H signed charRCC_APBENR2_TIM17EN (1 << 18)i2c_set_speeduint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1I2C_TIMINGR_SCLH_SHIFT 8SPI2_BASE (PERIPH_BASE_APB + 0x3800)__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)PTRDIFF_MINI2C2_OAR1 I2C_OAR1(I2C2)__UINT_LEAST16_MAX__ 0xffffI2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT)PPBI_BASE (0xE0000000U)RCC_BDCR_RTCEN (1 << 15)I2C_CR1_TXIE (1 << 1)__LACCUM_FBIT__ 31RCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_PPRE_DIV8 0x6__FLT_DIG__ 6I2C_ISR_DIR_READ (0x1 << 16)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINI2C_CR1_RXDMAEN (1 << 15)RST_DMARCC_ICSCR_HSITRIM_MASK 0x1f_BSD_SIZE_T_DEFINED_ I2C_CR1_ANFOFF (1 << 12)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RCC_APBSMENR2_TIM15SMEN (1 << 16)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)RCC_APBENR1_WWDGEN (1 << 11)I2C_TIMINGR_PRESC_SHIFT 28__INT_FAST32_MAX__ 0x7fffffffRCC_CFGR_MCOPRE_DIV64 6PWR_CR1_LPMS_MASK 0x07__ARM_ARCH_EXT_IDIV____DEFINED_size_t RCC_CCIPR_CECSEL_MASK 0x1I2C_ICR_BERRCF (1 << 8)ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))PWR_CR3_EWUP4 (1 << 3)RCC_APBRSTR1_OFFSET 0x2cRCC_APBENR1_LPTIM2EN (1 << 30)i2c_peripheral_disableI2C_ISR_TCR (1 << 7)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)TIM14_BASE (PERIPH_BASE_APB + 0x2000)RCC_CCIPR_TIM15SEL_PLLQCLK 1__USQ_FBIT__ 32RCC_CCIPR_USART1SEL_SYSCLK 1INT_FAST16_MINRCC_CCIPR_RNGDIV_8 3RCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32RCC_APBRSTR2_OFFSET 0x30PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)_BoolRST_SPI1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1_SIZE_T_DEFINED_ __ARM_FEATURE_QBITRCC_APBSMENR2_TIM16SMEN (1 << 17)PWR_CR2_PVDRT_2V6 0x03UINT_LEAST8_MAXI2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04)RST_DMA1UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RCC_AHBENR_AESEN (1 << 16)PWR_CR1_DBP (1 << 8)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__TIM7_BASE (PERIPH_BASE_APB + 0x1400)__USA_IBIT__ 16RCC_CFGR_SW_LSE 0x4i2c_enable_stretchingPTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HRI2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12)__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)i2c_enable_rxdmaRCC_APBENR1_UCPD2EN (1 << 26)__FLT_MIN__ 1.1754943508222875e-38FRCC_CR_HSIDIV_DIV1 0__HA_FBIT__ 7i2c_speed_sm_100k__FDPIC__RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODRST_GPIOEi2c_send_stopRCC_CSR_LPWRRSTF (1 << 31)I2C_CR1_STOPIE (1 << 5)RCC_CSR_PINRSTF (1 << 26)INT_FAST64_MINRCC_CCIPR_TIM15SEL_TIMPCLK 0__USFRACT_IBIT__ 0RCC_CFGR_SWS_SHIFT 3__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7SPI1_BASE (PERIPH_BASE_APB + 0x13000)../common/i2c_common_v2.c__USFRACT_MIN__ 0.0UHRRCC_PLLCFGR_PLLP_SHIFT 17__ARM_NEONPWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfPWR_CR1_LPMS_STANDBY 3__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_CCIPR_LPTIM2SEL_PCLK 0RCC_CCIPR_USART2SEL_LSE 3RCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_CCIPR_USART1SEL_MASK 0x3i2c_reset__ARM_FP16_FORMAT_ALTERNATIVEUINT_FAST32_MAXi2c_enable_analog_filter__INT_LEAST16_MAX__ 0x7fff_T_WCHAR_ I2C_ICR(i2c_base) MMIO32((i2c_base) + 0x1C)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LI2C_ICR_TIMOUTCF (1 << 12)RCC_CSR MMIO32(RCC_BASE + 0x60)_REG_BIT(offset,bit) (((offset) << 5) + (bit))RST_GPIOFPWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)RST_RNGCOMP_BASE (PERIPH_BASE_APB + 0x10200)RCC_APBENR1_OFFSET 0x3cINT_LEAST8_MAX __INT_LEAST8_MAX__RCC_ICSCR_HSICAL_SHIFT 0PWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29__UINT32_C(c) c ## ULI2C2_RXDR I2C_RXDR(I2C2)I2C1_ISR I2C_ISR(I2C1)___int_wchar_t_h __UACCUM_MIN__ 0.0UKRCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR2_PVDRT_2V5 0x02_WCHAR_T_DEFINED_ i2c_set_own_10bit_slave_addressRCC_CCIPR_I2S1SEL_SYSCLK 0RST_ADCRCC_APBENR2_ADCEN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)RCC_ICSCR_HSITRIM_SHIFT 8__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0I2C_TIMINGR_SCLL_SHIFT 0__ATOMIC_ACQ_REL 4I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8RCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2I2C1_PECR I2C_PECR(I2C1)RCC_CSR_RMVF (1 << 23)__ELF__ 1SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT32_HAS_QUIET_NAN__ 1RCC_APBRSTR1_UCPD2RST (1 << 26)RCC_CCIPR_USART2SEL_PCLK 0_SIZET_ __LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308i2c_set_digital_filter__ARM_PCS 1i2c_peripheral_enableRCC_CIER_HSIRDYIE (1 << 3)bool _Bool__size_t I2C_ISR_OVR (1 << 10)I2C_CR2_RD_WRN (1 << 10)RCC_APBENR2_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xff_BSD_WCHAR_T_ BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__i2c_disable_rxdmaRCC_CFGR_MCO_PLLRCLK 0x5I2C_CR1_ERRIE (1 << 7)__FLT32X_IS_IEC_60559__ 2speedRST_AESi2c_disable_autoendI2C_CR2_START (1 << 13)RCC_CSR_OBLRSTF (1 << 25)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXI2C_ICR_PECCF (1 << 11)__INT_LEAST16_WIDTH__ 16I2C1_RXDR I2C_RXDR(I2C1)__DEC_EVAL_METHOD__ 2RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04RCC_BDCR_LSERDY (1 << 1)__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)i2c_set_scl_high_periodRCC_CCIPR_CECSEL_SHIFT 6__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APBENR1_USART4EN (1 << 19)RCC_CICR_CSSC (1 << 8)__need_NULLI2C_ISR_DIR_WRITE (0x0 << 16)_BSD_PTRDIFF_T_ __USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT32_MAX__ 0xffffffffULRCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_RNGDIV_SHIFT 28__INT_LEAST8_MAX__ 0x7fRCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_BDCR_LSEDRV_MASK 0x3DAC_BASE (PERIPH_BASE_APB + 0x7400)CEC_BASE (PERIPH_BASE_APB + 0x7800)I2C_ISR_ARLO (1 << 9)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024I2C2_CR2 I2C_CR2(I2C2)RCC_CCIPR_ADCSEL_PLLPCLK 1n_bytesRCC_APBRSTR2_TIM14RST (1 << 15)RCC_APBSMENR2_TIM14SMEN (1 << 15)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1i2c_enable_interrupt__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fRST_I2C2BIT14 (1<<14)I2C1_CR2 I2C_CR2(I2C1)prescaler__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV512 0xfRCC_CFGR_MCOPRE_DIV32 5RCC_CCIPR_LPTIM1SEL_PCLK 0PWR_SR2_FLASHRDY (1 << 8)RCC_CFGR_MCO_SYSCLK 0x1__SOFTFP__ 1PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN_T_SIZE_ __FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RRCC_CFGR_PPRE_SHIFT 12BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffLPWR_CR4_WP6 (1 << 5)RCC_PLLCFGR_PLLR_MASK 0x7RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICLIBOPENCM3_RCC_H RCC_PLLCFGR_PLLREN (1<<28)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intI2C1_OAR2 I2C_OAR2(I2C1)INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1PWR_CR2_PVDFT_2V2 0x01I2C_CR1_PECEN (1 << 23)__DBL_MAX_EXP__ 1024i2c_set_data_setup_time__ATOMIC_RELEASE 3__FLT32X_HAS_DENORM__ 1__FLT_MANT_DIG__ 24RCC_CCIPR_LPTIM2SEL_LSI 1__UDQ_IBIT__ 0I2C_ICR_ALERTCF (1 << 13)RCC_CFGR_SWS_HSISYS 0x0RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_APBSMENR1_TIM2SMEN (1 << 0)I2C_CR1_WUPEN (1 << 18)UINTPTR_MAX_T_PTRDIFF_ __LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLRCC_APBRSTR1_I2C1RST (1 << 21)I2C_ICR_STOPCF (1 << 5)__ULLFRACT_IBIT__ 0_ANSI_STDDEF_H _PTRDIFF_T_ MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8)RCC_APBSMENR1_TIM3SMEN (1 << 1)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)RCC_CIFR_HSIRDYF (1 << 3)__GNUC__ 12RST_LPTIM1RST_LPTIM2WCHAR_MAXRCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32RCC_PLLCFGR_PLLPEN (1 << 16)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKRCC_APBENR2_SYSCFGEN (1 << 0)__need_size_t__INT_MAX__ 0x7fffffffRCC_CFGR_SW_MASK 0x3_SIZE_T_ PWR_CR2_PVDFT_2V9 0x06RCC_PLLCFGR_PLLQ_SHIFT 25__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55PWR_SR1_WUFI (1 << 15)__ARM_FEATURE_CMSEINT16_MAXi2c_nack__wchar_t__ CRC_BASE (PERIPH_BASE_AHB + 0x03000)__LDBL_HAS_QUIET_NAN__ 1RCC_APBSMENR1_DAC1SMEN (1 << 29)I2C2_PECR I2C_PECR(I2C2)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28RCC_APBRSTR2_USART1RST (1 << 14)I2C_ISR_STOPF (1 << 5)I2C_CR2_SADD_10BIT_MASK 0x3FF__UINT_FAST64_MAX__ 0xffffffffffffffffULLINFO_BASE (0x1fff7500U)__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32i2c_send_dataRCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_PLLCFGR_PLLP_DIV(x) ((x)-1)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024I2C_ISR_NACKF (1 << 4)UINT16_MAXI2C2_TIMEOUTR I2C_TIMEOUTR(I2C2)__FLT64_MIN__ 2.2250738585072014e-308F64i2c_get_dataPWR_CR2_PVDFT_MASK 0x07i2c_received_dataRCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long intI2C1_ICR I2C_ICR(I2C1)__LFRACT_FBIT__ 31__CHAR_BIT__ 8interrupt__SIZEOF_WCHAR_T__ 4_PTRDIFF_T ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))LIBOPENCM3_PWR_H RCC_APBRSTR1_TIM3RST (1 << 1)i2c_set_10bit_addressRCC_CCIPR MMIO32(RCC_BASE + 0x54)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)__UFRACT_MAX__ 0XFFFFP-16URRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)RCC_CCIPR_CECSEL_HSI16 0INT64_MAXPWR_CR2_PVDRT_2V1 0x00i2c_speedsNULLRCC_CCIPR_TIM15SEL_SHIFT 24INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_APBENR1_USART3EN (1 << 18)RCC_CFGR_SWS_HSE 0x1__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RST_TIM15RST_TIM16RST_TIM17waitSYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CCIPR_I2S1SEL_MASK 0x3I2C_CR2_SADD_10BIT_SHIFT 0RCC_PLLCFGR_PLLSRC_HSI16 2__ARM_32BIT_STATE__UFRACT_FBIT__ 16addr__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_AHBSMENR_OFFSET 0x48__LDBL_MAX_10_EXP__ 308I2C_ISR(i2c_base) MMIO32((i2c_base) + 0x18)RCC_APBENR1_DAC1EN (1 << 29)i2c_set_own_7bit_slave_addressI2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)RCC_APBSMENR1_DBGSMEN (1 << 27)__ATOMIC_SEQ_CST 5RCC_CCIPR_CECSEL_LSE 1__GCC_ASM_FLAG_OUTPUTS__RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)RCC_CCIPR_RNGDIV_4 2ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)RCC_CIFR_HSERDYF (1 << 4)__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32_STDBOOL_H I2C_ISR_RXNE (1 << 2)_WCHAR_T_DECLARED i2c_set_10bit_addr_mode__FLT_EVAL_METHOD__ 0i2c_disable_analog_filter__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CR_PLLON (1 << 24)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXi2c_speed_fmp_1m_T_PTRDIFF __UQQ_FBIT__ 8PWR_CR4_WP5 (1 << 4)i2c_enable_autoendRST_UCPD1__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_APBSMENR1_TIM7SMEN (1 << 5)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__i2c_disable_interruptRTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charI2C_ISR_TIMEOUT (1 << 12)__SIG_ATOMIC_TYPE__ intRCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"RCC_CR_HSIRDY (1 << 10)INT8_MIN__ORDER_PDP_ENDIAN__ 3412RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_CCIPR_LPUART1SEL_MASK 0x3I2C_CR2_AUTOEND (1 << 25)RCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1_PTRDIFF_T_DECLARED __USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)RCC_APBRSTR1_DBGRST (1 << 27)I2C_TIMINGR_SDADEL_SHIFT 16__LDBL_MIN_10_EXP__ (-307)RCC_AHBSMENR_SRAMSMEN (1 << 9)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 1PWR_CR1_VOS_MASK 0x3RCC_CIER_LSIRDYIE (1 << 0)I2C2 I2C2_BASERCC_CCIPR_LPTIM2SEL_MASK 0x3__LFRACT_EPSILON__ 0x1P-31LRI2C2_ICR I2C_ICR(I2C2)RCC_CCIPR_USART2SEL_SYSCLK 1RCC_CCIPR_I2S1SEL_SHIFT 14RCC_PLLCFGR_PLLQ_MASK 0x7__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__PWR_CR2_PVDFT_2V0 0x00__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xi2c_transmit_int_status__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)I2C_TXDR(i2c_base) MMIO32((i2c_base) + 0x28)RCC_CR_HSIDIV_DIV16 4I2C_TIMEOUTR(i2c_base) MMIO32((i2c_base) + 0x14)__FLT32_MIN_10_EXP__ (-37)___int_size_t_h RCC_APBSMENR2_SYSCFGSMEN (1 << 0)MMIO64(addr) (*(volatile uint64_t *)(addr))_WCHAR_T RCC_APBENR1_TIM7EN (1 << 5)unsigned intRCC_PLLCFGR_PLLSRC_SHIFT 0__LDBL_NORM_MAX__ 1.7976931348623157e+308Li2c_is_start__DA_FBIT__ 31DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)_GCC_PTRDIFF_T /build/libopencm3/lib/stm32/g0__TA_IBIT__ 64USART3_BASE (PERIPH_BASE_APB + 0x4800)RCC_CCIPR_LPTIM1SEL_LSI 1_SIZE_T __SACCUM_IBIT__ 8__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1I2C_ICR_ADDRCF (1 << 3)WCHAR_MIN __WCHAR_MIN__RCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3__USQ_IBIT__ 0i2c_set_read_transfer_dirBIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)RCC_CR_HSIDIV_DIV128 7_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RCC_APBRSTR1_TIM6RST (1 << 4)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__SIZE_T __LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)RCC_APBSMENR2_TIM17SMEN (1 << 18)i2c_clear_stopRCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1RCC_APBSMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_I2C1SEL_PCLK 0PWR_CR1_LPMS_SHUTDOWN 4__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1i2c_transfer_completeBIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7PWR_CR2_PVDFT_2V4 0x02INT32_MAXRCC_BDCR_BDRST (1 << 16)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_CCIPR_I2C1SEL_HSI16 2_GCC_WCHAR_T __ARM_FEATURE_CRYPTOI2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00)I2C_OAR2_OA2EN (1 << 15)__INT_LEAST32_TYPE__ long intRCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9PWR_SCR_CWUF5 (1 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__FRACT_IBIT__ 0PWR_CR3_ULPEN (1 << 9)RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2I2C_CR1_DNF_SHIFT 8BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234I2C_ISR_ALERT (1 << 13)I2C2_OAR2 I2C_OAR2(I2C2)__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32I2C1 I2C1_BASE__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__WINT_MAX__ 0xffffffffUPWR_CR3_APC (1 << 10)INT_LEAST64_MAXuint16_t__DQ_FBIT__ 63I2C_CR1_GCEN (1 << 19)__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)__INT_FAST16_TYPE__ intPWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRST_SPI2__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intI2C_ISR_TXE (1 << 0)I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1)__FLT32X_DIG__ 15RCC_APBSMENR1_SPI2SMEN (1 << 14)RCC_CIFR_LSIRDYF (1 << 0)PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)__UTQ_FBIT__ 128PWR_CR2_PVDRT_2V9 0x05RCC_CCIPR_RNGSEL_HSI16 1__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffRCC_APBSMENR2_SPI1SMEN (1 << 12)RCC_IOPSMENR_OFFSET 0x44PTRDIFF_MAX __PTRDIFF_MAX__PWR_CR1_LPMS_STOP_0 0__ARM_ARCH 6I2C2_BASE (PERIPH_BASE_APB + 0x5800)I2C_OAR1_OA1MODE (1 << 10)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CR_HSIDIV_DIV2 1RCC_CCIPR_RNGSEL_PLLQCLK 3I2C_ICR_ARLOCF (1 << 9)dnf_setting__ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)I2C_OAR1_OA1_10BIT 1__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CCIPR_LPTIM2SEL_LSE 3RCC_BDCR_LSEDRV_HIGH 3GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT)_BSD_SIZE_T_ WCHAR_MINRCC_CCIPR_RNGSEL_MASK 0x3PWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3I2C_OAR1_OA1_7BIT 0_WCHAR_T_ RCC_CFGR_SWS_LSE 0x4BEGIN_DECLS periodI2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT)RST_TIM2RCC_CFGR_MCO_LSI 0x6RCC_CFGR_SW_LSI 0x3i2c_set_prescalerRST_LPUART1__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xI2C_CR1_TXDMAEN (1 << 14)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__FLT32_MIN__ 1.1754943508222875e-38F32INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1i2c_set_bytes_to_transferDMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)RCC_CIER MMIO32(RCC_BASE + 0x18)RST_CEC__QQ_IBIT__ 0I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08)PWR_CR2_PVDFT_2V8 0x05RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)__GNUC_MINOR__ 2__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINRCC_CIER_LSERDYIE (1 << 1)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)I2C_RXDR(i2c_base) MMIO32((i2c_base) + 0x24)RCC_PLLCFGR_PLLN_SHIFT 0x8I2C_CR1_SMBDEN (1 << 21)__ARM_FEATURE_FP16_SCALAR_ARITHMETICUINT_FAST32_MAX __UINT_FAST32_MAX____USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1clock_megahz__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_Cs_timeRCC_CCIPR_TIM1SEL_PLLQCLK 1INT64_MINRCC_BDCR_RTCSEL_NONE 0__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned int__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRI2C2_ISR I2C_ISR(I2C2)PWR_CR2_PVDRT_PVD_IN 0x07PWR_SCR_CWUF4 (1 << 3)__SIZEOF_SIZE_T__ 4PWR_CR1_VOS_RANGE_1 1__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLI2C1_TIMINGR I2C_TIMINGR(I2C1)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)MPU_BASE (SCS_BASE + 0x0D90)TIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_APBRSTR2_TIM1RST (1 << 11)I2C2_TIMINGR I2C_TIMINGR(I2C2)CORESIGHT_LAR_OFFSET 0xfb0UCPD1_BASE (PERIPH_BASE_APB + 0xA000)I2C_CR2_RELOAD (1 << 24)RCC_BDCR_LSEON (1 << 0)RCC_APBRSTR1_DAC1RST (1 << 29)short int_STDDEF_H __FLT32_IS_IEC_60559__ 2_SYS_SIZE_T_H __UINT16_C(c) c__UDA_IBIT__ 32i2c_speed_fm_400kI2C_CR1_NOSTRETCH (1 << 17)UINT_LEAST32_MAXRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8)BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1I2C2_CR1 I2C_CR1(I2C2)I2C_CR1_RXIE (1 << 2)__need_ptrdiff_t__DBL_DECIMAL_DIG__ 17SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)BIT8 (1<<8)RST_TIM7__ULACCUM_FBIT__ 32RCC_AHBRSTR_RNGRST (1 << 18)INT16_C(c) __INT16_C(c)_WCHAR_T_DEFINED RCC_CCIPR_I2S1SEL_PLLPLCK 1i2c_set_7bit_addr_mode__INT16_MAX__ 0x7fffRCC_CFGR_MCOPRE_DIV16 4I2C1_CR1 I2C_CR1(I2C1)__WCHAR_T__ __INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0RCC_CCIPR_LPUART1SEL_SHIFT 10PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)PWR_CR1_VOS_SHIFT 9__QQ_FBIT__ 7RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8)__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHBRSTR_FLASHRST (1 << 8)INT16_C__DEFINED_wchar_t I2C_ICR_NACKCF (1 << 4)__UTA_IBIT__ 64RCC_CCIPR_I2S1SEL_I2S_CKIN 2I2C_TIMINGR_PRESC_MASK (0xF << 28)__ULLFRACT_EPSILON__ 0x1P-64ULLRRST_DBGRCC_CCIPR_ADCSEL_MASK 0x3__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4RCC_APBRSTR2_SPI1RST (1 << 12)PWR_CR1_LPMS_SHIFT 0__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1PWR_CR1_VOS_RANGE_2 2RCC_CFGR_HPRE_DIV8 0xa__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)PWR_CR2_PVDRT_2V7 0x04__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1i2c_disable_stretchingRCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)RCC_APBENR1_TIM6EN (1 << 4)RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2I2C_OAR1_OA1MODE_7BIT 0I2C_ISR_BUSY (1 << 15)I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8)RCC_PLLCFGR_PLLQEN (1 << 24)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_CIER_PLLRDYIE (1 << 5)RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1I2C_CR2_NACK (1 << 15)RST_I2C1_GCC_SIZE_T RCC_APBSMENR2_USART1SMEN (1 << 14)I2C_ISR_TC (1 << 6)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAXRST_UCPD2__ARM_FP16_ARGSI2C_OAR2_OA2MSK_OA2_7 (0x6 << 8)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T_RCC_APBENR2_TIM1EN (1 << 11)__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tBIT12 (1<<12)RCC_CCIPR_LPTIM2SEL_HSI16 2RCC_CFGR_HPRE_DIV128 0xdPWR_CR4_WP1 (1 << 0)I2C_CR2_SADD_7BIT_SHIFT 1__SACCUM_EPSILON__ 0x1P-7HKRCC_CIFR_PLLRDYF (1 << 5)RST_DAC1RCC_CFGR_SW_SHIFT 0RCC_APBRSTR1_LPUART1RST (1 << 20)I2C_CR1_PE (1 << 0)__UINT_FAST16_TYPE__ unsigned intRCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)__UHA_IBIT__ 8__INT_WCHAR_T_H PWR_SR1_WUF4 (1 << 3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)RCC_APBSMENR1_USART4SMEN (1 << 19)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINI2C1_TXDR I2C_TXDR(I2C1)PWR_SCR_CWUF1 (1 << 0)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APBENR2_TIM16EN (1 << 17)__INT_LEAST16_TYPE__ short intI2C_ISR_BERR (1 << 8)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RST_TIM1UINTMAX_CRST_TIM3RCC_APBENR1_PWREN (1 << 28)RST_TIM6INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RST_FLASHI2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT)PWR_SR1_SBF (1 << 8)__HQ_FBIT__ 15__bool_true_false_are_defined 1I2C_CR2_ADD10 (1 << 11)RCC_CCIPR_ADCSEL_SHIFT 30BIT26 (1<<26)RCC_CFGR_SWS_PLLRCLK 0x2RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)I2C_OAR1_OA1 (1 << 10)__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)__LONG_MAX__ 0x7fffffffLRCC_CCIPR_USART2SEL_HSI16 2RCC_APBSMENR1_USART3SMEN (1 << 18)I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT)RCC_APBENR1_TIM2EN (1 << 0)I2C_CR1_SBC (1 << 16)RCC_AHBENR_OFFSET 0x38__PTRDIFF_TYPE__ intINT_LEAST64_MINPTRDIFF_MAXRCC_AHBSMENR_CRCSMEN (1 << 12)RNG_BASE (PERIPH_BASE_AHB + 0x05000)i2c_transfer7I2C_TIEMOUTR_TIMOUTEN (1 << 15)_STDDEF_H_ __ARM_ARCH_6M__ 1RCC_CR_HSIKERON (1 << 9)PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__i2c_enable_txdmaWINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RST_TIM14RCC_APBRSTR1_USART3RST (1 << 18)RST_USART1RST_USART2RST_USART3RST_USART4I2C1_OAR1 I2C_OAR1(I2C1)RCC_CCIPR_LPUART1SEL_PCLK 0__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)I2C_CR1_SMBHEN (1 << 20)PWR_CR4_VBRS (1 << 9)dataRCC_CFGR_MCO_HSI16 0x3prescRCC_CFGR_MCO_LSE 0x7RCC_CR_CSSON (1 << 19)RST_PWRRCC_CFGR_PPRE_DIV2 0x4RCC_PLLCFGR_PLLSRC_MASK 0x3i2c_speed_unknown__FLT32_NORM_MAX__ 3.4028234663852886e+38F32PWR_CR4_WP2 (1 << 1)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)RCC_APBRSTR1_LPTIM2RST (1 << 30)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)RCC_CR_HSION (1 << 8)INT_FAST16_MAX__INT_FAST64_WIDTH__ 64I2C_ISR_PECERR (1 << 11)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long inti2c_set_scl_low_periodIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_CICR_LSERDYC (1 << 1)PWR_SR2_REGLPS (1 << 8)RCC_CCIPR_ADCSEL_SYSCLK 0UINT32_CRCC_CR_HSIDIV_DIV64 6GCC: (15:12.2.rel1-1) 12.2.1 20221205 | ,B                           A ^AA+aeabi!6S-M M       !!"" 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"! ".!!/  2 .E ! !pllnRCC_CICR_PLLRDYC (1 << 5)pllppllqpllr__DECIMAL_DIG__ 17RCC_CCIPR_LPTIM1SEL_MASK 0x3__UHA_FBIT__ 8RCC_CCIPR_USART1SEL_PCLK 0PERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_SR1_WUF1 (1 << 0)RCC_APBSMENR2_TIM14SMEN (1 << 15)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1FLASH_OPTR_nRSTS_HDW (1 << 15)PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1RCC_CSR_LSION (1 << 0)STM32G0 1FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)RCC_CCIPR_RNGSEL_SYSCLK 2RCC_CICR_LSECSSC (1 << 9)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffPWR_SR2_REGLPF (1 << 9)RCC_AHBSMENR_RNGSMEN (1 << 18)__INTMAX_C(c) c ## LLTIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLLMMIO8(addr) (*(volatile uint8_t *)(addr))RCC_APBSMENR1_USART2SMEN (1 << 17)__TQ_IBIT__ 0rcc_periph_clken__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUFLASH_OPTR_BOREN (1 << 8)RCC_DBG__ARM_FEATURE_QBITLIBOPENCM3_RCC_COMMON_ALL_H RCC_APBRSTR2_TIM15RST (1 << 16)SCC_CECRCC_BDCR MMIO32(RCC_BASE + 0x5c)__FLT_MANT_DIG__ 24RCC_APBSMENR1_PWRSMEN (1 << 28)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64FLASH_OPTR_nRST_STOP (1 << 13)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9RCC_AHBRSTR_CRCRST (1 << 12)DESIG_FLASH_SIZE_BASE (0x1FFF75E0)__LDBL_MIN_EXP__ (-1021)FLASH_CR_MER (1 << 2)__LDBL_MANT_DIG__ 53rcc_css_int_clearWWDG_BASE (PERIPH_BASE_APB + 0x2c00)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__WINT_TYPE__ unsigned intRCC_APBSMENR1_RTCAPBSMEN (1 << 10)apb_frequency__FLT64_MAX__ 1.7976931348623157e+308F64RCC_PLLCFGR_PLLP_MASK 0x1fUINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4PWR_CR3_EIWUL (1 << 15)RCC_CIER_LSIRDYIE (1 << 0)RCC_CR_HSIRDY (1 << 10)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0INT_FAST64_MAX __INT_FAST64_MAX__RCC_PLLCFGR_PLLM_SHIFT 0x4__STDC_HOSTED__ 1rcc_osc_offRCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_RNGSEL_HSI16 1FLASH_CR_FSTPG (1 << 18)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long intpwr_set_vos_scaleRCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR1_OFFSET 0x4cRCC_CCIPR_LPUART1SEL_MASK 0x3INT32_MIN (-INT32_MAX - 1)RCC_CCIPR_CECSEL_HSI16 0__FLT32_MAX_10_EXP__ 38FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)RCC_CFGR_HPRE_DIV8 0xaRCC_CFGR_SW_PLLRCLK 0x2SCC_DBGRCC_APBENR1_DBGEN (1 << 27)__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZ__UINTPTR_MAX__ 0xffffffffURCC_APBSMENR1_DAC1SMEN (1 << 29)__FLT32_MIN_EXP__ (-125)RCC_CSR_LPWRRSTF (1 << 31)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))RCC_CFGR_MCOPRE_DIV1 0PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_APBRSTR1_SPI2RST (1 << 14)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)RCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRRCC_CFGR_HPRE_SHIFT 8RCC_IOPSMENR_OFFSET 0x44__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXFLASH_CR_ERRIE (1 << 25)__SQ_FBIT__ 31UINT32_C__UTA_FBIT__ 64PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)FLASH_CR_PER (1 << 1)__UHQ_FBIT__ 16RCC_AHBSMENR_FLASHSMEN (1 << 8)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB + 0x00000)INT8_C(c) __INT8_C(c)__UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)PWR_SR2_VOSF (1 << 10)UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)__LACCUM_IBIT__ 32PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_SCR_CWUF2 (1 << 1)flash_waitstates__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_CFLASH_OPTR_BORF_LEV_2V5 2__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXPWR_SR2_PVDO (1 << 11)__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CCIPR_TIM1SEL_MASK 0x1RCC_CCIPR_USART1SEL_SHIFT 0SCC_SPI1SCC_SPI2__UFRACT_MIN__ 0.0UR__LDBL_HAS_QUIET_NAN__ 1FLASH_OPTR_RAM_PARITY_CHECK (1 << 22)RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)RCC_APBRSTR2_ADCRST (1 << 20)__UINT_LEAST8_TYPE__ unsigned charRCC_PWRRCC_APBRSTR2_TIM17RST (1 << 18)__ACCUM_FBIT__ 15RCC_APBRSTR1_TIM2RST (1 << 0)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)rcc_set_rng_clk_div__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17FLASH_OPTR_RDP_LEVEL_2 0xCC__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_APBSMENR1_LPTIM2SMEN (1 << 30)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intrcc_wait_for_sysclk_status__UDA_FBIT__ 32PWR_SCR_CWUF4 (1 << 3)RCC_APBENR2_SPI1EN (1 << 12)RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZRCC_APBENR2_OFFSET 0x40__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_APBSMENR2_OFFSET 0x50__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHBENR_DMAEN (1 << 0)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_PLLCFGR_PLLREN (1<<28)GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)rcc_ahb_frequencyshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)PWR_CR4_WP1 (1 << 0)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)RCC_APBENR1_I2C1EN (1 << 21)RCC_CCIPR_I2S1SEL_HSI16 2UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_SPI2LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CCIPR_LPTIM2SEL_MASK 0x3__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_CFGR_SW_HSISYS 0x0cm3_assert(expr) do { if (CM3_LIKELY(expr)) { (void)0; } else { cm3_assert_failed(); } } while (0)RCC_APBRSTR1_TIM7RST (1 << 5)PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)RCC_CCIPR_RNGDIV_1 0pllq_div__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32rcc_get_clksel_freqFLASH_OPTR_nBOOT_SEL (1 << 24)RCC_CCIPR_CECSEL_MASK 0x1RCC_PLLCFGR_PLLQ_MASK 0x7RCC_APBSMENR2_TIM15SMEN (1 << 16)RCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)rcc_clock_scaleBIT27 (1<<27)SCC_PWRRCC_LPUART1RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APBRSTR1_LPTIM2RST (1 << 30)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)RCC_CCIPR_USART2SEL_SHIFT 2rcc_set_mcopreRCC_CCIPR_LPTIM2SEL_SHIFT 20__FLT_MIN_10_EXP__ (-37)usartRCC_APBENR1_UCPD1EN (1 << 25)rcc_clock_configPWR_CR2_PVDRT_3V0 0x06LIBOPENCM3_MEMORYMAP_COMMON_H RCC_LSI__VERSION__ "12.2.1 20221205"RCC_CFGR_MCO_HSI16 0x3uint8_tINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1SPI2_BASE (PERIPH_BASE_APB + 0x3800)FLASH_CR_OBL_LAUNCH (1 << 27)__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__FLT_HAS_QUIET_NAN__ 1RCC_TIM2__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)FLASH_CR_PNB_MASK 0x3fPTRDIFF_MIN__UINT_LEAST16_MAX__ 0xffffRCC_TIM6__FLT32_HAS_QUIET_NAN__ 1UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77__LACCUM_FBIT__ 31RCC_CFGR_PPRE_DIV16 0x7FLASH_SR_PGSERR (1 << 7)RCC_CFGR_PPRE_DIV8 0x6__FLT64_MAX_10_EXP__ 308FLASH_OPTR_IWDG_STOP (1 << 17)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_ICSCR_HSITRIM_MASK 0x1fRCC_APBENR1_TIM2EN (1 << 0)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38pll_mulFLASH_OPTR_BORR_LEV_2V1 0__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0FLASH_OPTR_BORR_LEV_MASK 0x03INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)SCC_DMA1RCC_APBENR1_WWDGEN (1 << 11)RCC_APBRSTR1_DAC1RST (1 << 29)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5LIBOPENCM3_FLASH_H FLASH_SR_PROGERR (1 << 3)__ARM_ARCH_EXT_IDIV__RCC_CIER_PLLRDYIE (1 << 5)FLASH_SR_RDERR (1 << 14)BIT8 (1<<8)ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))__DQ_IBIT__ 0RCC_APBRSTR1_OFFSET 0x2cRCC_APBENR1_LPTIM2EN (1 << 30)PWR_CR2_PVDFT_2V0 0x00__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)RCC_RNGTIM14_BASE (PERIPH_BASE_APB + 0x2000)ahb_frequencypllp_divRCC_CCIPR_USART1SEL_SYSCLK 1INT_FAST16_MINRCC_CCIPR_RNGDIV_8 3FLASH_SR_OPTVERR (1 << 15)RCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32RCC_APBRSTR2_OFFSET 0x30PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)_BoolhsidivSPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1rcc_get_usart_clk_freqpllr_divUINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)__SIZEOF_LONG_DOUBLE__ 8RCC_AHBENR_AESEN (1 << 16)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__TIM7_BASE (PERIPH_BASE_APB + 0x1400)__USA_IBIT__ 16RCC_CFGR_SW_LSE 0x4PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)RCC_APBENR1_TIM6EN (1 << 4)__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)RCC_CFGR_SWS_PLLRCLK 0x2RCC_APBENR1_UCPD2EN (1 << 26)FLASH_OPTR_NRST_MODE_MASK 0x03__FLT_MIN__ 1.1754943508222875e-38FRCC_CR_HSIDIV_DIV1 0__HA_FBIT__ 7RCC_APBRSTR2_TIM1RST (1 << 11)__FDPIC__RCC_GPIOARCC_GPIOBRCC_GPIOCRCC_GPIODRCC_GPIOERCC_GPIOFRCC_IOPENR_OFFSET 0x34RCC_CSR_PINRSTF (1 << 26)RCC_CFGR_MCO_PLLRCLK 0x5INT_FAST64_MINRCC_CCIPR_TIM15SEL_TIMPCLK 0__USFRACT_IBIT__ 0RCC_CFGR_SWS_SHIFT 3PWR_CR2_PVDRT_MASK 0x07__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7RCC_APBENR2_TIM16EN (1 << 17)__USFRACT_MIN__ 0.0UHRRCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONPWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xffRCC_CLOCK_CONFIG_HSI_PLL_64MHZ__LDBL_MAX_EXP__ 1024SCC_LPTIM1SCC_LPTIM2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfSCC_RNG__FLT32X_HAS_DENORM__ 1BIT7 (1<<7)__DBL_HAS_DENORM__ 1sourceRCC_CCIPR_LPTIM2SEL_PCLK 0RCC_CCIPR_USART2SEL_LSE 3RCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_CCIPR_USART1SEL_MASK 0x3FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)__DA_FBIT__ 31BIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3RCC_ICSCR_HSICAL_SHIFT 0__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_CSR MMIO32(RCC_BASE + 0x60)RCC_CIFR_HSIRDYF (1 << 3)RCC_CCIPR_LPTIM2SEL_LSI 1COMP_BASE (PERIPH_BASE_APB + 0x10200)RCC_APBENR1_OFFSET 0x3cINT_LEAST8_MAX __INT_LEAST8_MAX__RCC_APBENR1_PWREN (1 << 28)rcc_osc_onPWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29__UINT32_C(c) c ## ULRCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)RCC_CFGR_MCOPRE_DIV4 2__UACCUM_MIN__ 0.0UKRCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR2_PVDRT_2V5 0x02RCC_PLLCFGR_PLLSRC_SHIFT 0FLASH_SR_SIZERR (1 << 6)RCC_CCIPR_I2S1SEL_SYSCLK 0FLASH_OPTR_NRST_MODE_SHIFT 27__PTRDIFF_TYPE__ intRCC_APBENR2_ADCEN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)FLASH_ACR_ICEN (1 << 9)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8LIBOPENCM3_PWR_H PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0RCC_PLLCFGR_PLLPEN (1 << 16)rcc_set_pll_sourceRCC_CCIPR_LPUART1SEL_LSE 3rcc_clock_setupRCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2SCC_DAC1FLASH_OPTR_NRST_MODE_BIDIR 3FLASH_OPTR_NRST_MODE_GPIO 2__ELF__ 1SCS_BASE (PPBI_BASE + 0xE000)rcc_get_i2c_clk_freqPWR_CR1_VOS_SHIFT 9rcc_enable_pllprcc_enable_pllqINT8_MAXRCC_CLOCK_CONFIG_HSI_4MHZRCC_CCIPR_USART2SEL_PCLK 0RCC_CSR_OBLRSTF (1 << 25)FLASH_ACR_LATENCY_MASK 0x7__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__RCC_LSEFLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)__FLT32X_MAX_10_EXP__ 308RCC_APBENR2_TIM1EN (1 << 11)__ARM_PCS 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_CCIPR_RNGSEL_MASK 0x3RCC_CRCRCC_APBENR2_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffrcc_is_osc_readyBIT13 (1<<13)flash_prefetch_enableBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCC_TIM1INT16_MAX __INT16_MAX__SCC_TIM3RCC_APBSMENR2_TIM16SMEN (1 << 17)SCC_TIM6SCC_TIM7__FLT32X_IS_IEC_60559__ 2hsisys_divPWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)RCC_CIER MMIO32(RCC_BASE + 0x18)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__UFRACT_MAX__ 0XFFFFP-16URrcc_css_int_flag__INT_LEAST16_WIDTH__ 16RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)RCC_CR_HSIDIV_DIV64 6CORESIGHT_LAR_OFFSET 0xfb0__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04FLASH_OPTR_nRST_STDBY (1 << 14)RCC_BDCR_LSERDY (1 << 1)FLASH_OPTR_BORR_LEV_SHIFT 11FLASH_ECCR_ECCC (1 << 30)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APBSMENR1_USART3SMEN (1 << 18)RCC_APBENR2_TIM17EN (1 << 18)RCC_CCIPR_CECSEL_SHIFT 6RCC_DAC1__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRCC_APBENR1_USART4EN (1 << 19)PWR_CR2_PVDFT_2V9 0x06PWR_CR1_VOS_MASK 0x3RCC_AHBRSTR_OFFSET 0x28__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_TIM15SEL_PLLQCLK 1RCC_DMARCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_RNGDIV_SHIFT 28__INT_LEAST8_MAX__ 0x7fFLASH_SR_EOP (1 << 0)RCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIVRCC_HSE__ARM_FEATURE_COMPLEXPWR_CR2_PVDFT_2V8 0x05DAC_BASE (PERIPH_BASE_APB + 0x7400)RCC_HSICEC_BASE (PERIPH_BASE_APB + 0x7800)FLASH_ACR_EMPTY (1 << 16)rcc_clockRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_BDCR_LSEON (1 << 0)RCC_CCIPR_ADCSEL_PLLPCLK 1BIT21 (1<<21)RCC_TIM1SCC_CRCRCC_TIM3flash_prefetch_disable__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_PLLCFGR_PLLSRC_HSE 3FLASH_ACR_PRFTEN (1 << 8)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)__ACCUM_MAX__ 0X7FFFFFFFP-15KFLASH_OPTR_NRST_MODE_RESET 1__INT8_MAX__ 0x7fBIT14 (1<<14)RCC_ICSCR_HSITRIM_SHIFT 8__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV512 0xfPWR_SR2_FLASHRDY (1 << 8)RCC_CFGR_MCO_SYSCLK 0x1__SOFTFP__ 1PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)UINT_LEAST16_MAX __UINT_LEAST16_MAX__pll_divINT_FAST32_MINRCC_CFGR_MCOPRE_DIV16 4__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)shift__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RRCC_CFGR_PPRE_SHIFT 12BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffLPWR_CR4_WP6 (1 << 5)RCC_PLLCFGR_PLLR_MASK 0x7RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLFLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c)__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCC_DMALIBOPENCM3_RCC_H PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2cm3_assert_failedSCC_GPIOF__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAXrng_divclock__UDQ_IBIT__ 0RCC_CFGR_SWS_HSISYS 0x0FLASH_SR_FASTERR (1 << 9)RCC_CR_HSERDY (1 << 17)SCC_FLASH__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_CECSEL_LSE 1__FINITE_MATH_ONLY__ 0PWR_CR1_LPMS_STOP_0 0__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLFLASH_OPTR_RDP_SHIFT 0RCC_APBRSTR1_I2C1RST (1 << 21)__ULLFRACT_IBIT__ 0rcc_wait_for_osc_readyFLASH_OPTR_WWDG_SW (1 << 19)MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)RCC_LPTIM1RCC_LPTIM2RCC_APBSMENR1_TIM3SMEN (1 << 1)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)PWR_CR2_PVDRT_2V2 0x01__GNUC__ 12PWR_CR2_PVDFT_2V2 0x01WCHAR_MAXGPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)RCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16FLASH_CR_OPTLOCK (1 << 30)RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)RCC_ADCRCC_APBENR2_SYSCFGEN (1 << 0)FLASH_CR_RDERRIE (1 << 26)__ARM_ARCH 6RCC_CFGR_SW_MASK 0x3RCC_PLLCFGR_PLLQ_SHIFT 25__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55rcc_css_enable__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXrcc_apb1_frequencySCC_GPIOASCC_GPIOBSCC_GPIOCSCC_GPIODSCC_GPIOE__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_CFGR_MCOPRE_DIV64 6TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28RCC_APBRSTR2_USART1RST (1 << 14)enable__UINT_FAST64_MAX__ 0xffffffffffffffffULLINFO_BASE (0x1fff7500U)__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)RCC_CICR_LSERDYC (1 << 1)__FLT32X_MIN__ 2.2250738585072014e-308F32xclkselINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024PWR_SR1_WUFI (1 << 15)UINT16_MAXBIT20 (1<<20)TIM16_BASE (PERIPH_BASE_APB + 0x14400)__FLT64_MIN__ 2.2250738585072014e-308F64rcc_enable_pllrGNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsPWR_CR2_PVDFT_MASK 0x07PWR_CR1_LPMS_STANDBY 3rcc_get_timer_clk_freqRCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4FLASH_OPTR_BORF_LEV_2V0 0ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))maskFLASH_SR_BSY (1 << 16)RCC_CCIPR MMIO32(RCC_BASE + 0x54)timerRCC_AESpwr_vos_scaleRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)INT64_MAXPWR_CR2_PVDRT_2V1 0x00UINTMAX_CPWR_CR3_EWUP2 (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_APBENR1_USART3EN (1 << 18)RCC_CFGR_SWS_HSE 0x1SCC_ADC__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RCC_TIM14RCC_TIM15RCC_TIM16RCC_TIM17SYS_TICK_BASE (SCS_BASE + 0x0010)rcc_oscRCC_CCIPR_I2C1SEL_HSI16 2RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHBRSTR_DMARST (1 << 0)__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_AHBSMENR_OFFSET 0x48__LDBL_MAX_10_EXP__ 308RCC_APBENR1_DAC1EN (1 << 29)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)RCC_APBSMENR1_DBGSMEN (1 << 27)unsigned int__GCC_ASM_FLAG_OUTPUTS__RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)RCC_BDCR_RTCEN (1 << 15)__FLT_MIN_EXP__ (-125)__DEC_EVAL_METHOD__ 2FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)FLASH_CR_PNB_SHIFT 3RCC_CCIPR_RNGDIV_4 2ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UINTMAX_TYPE__ long long unsigned intPWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)rcc_system_clock_sourceRCC_CCIPR_RNGDIV_2 1SCB_BASE (SCS_BASE + 0x0D00)__FLT_EVAL_METHOD__ 0FLASH_OPTR_RDP_LEVEL_0 0xAARCC_CLOCK_CONFIG_HSI_16MHZ__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CR_PLLON (1 << 24)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXSCC_AES__UQQ_FBIT__ 8PWR_CR4_WP5 (1 << 4)__HQ_FBIT__ 15RCC_APBENR1_SPI2EN (1 << 14)__ARM_FP16_ARGSRCC_UCPD1RCC_UCPD2FLASH_SR_CFGBSY (1 << 18)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_APBSMENR1_TIM7SMEN (1 << 5)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____FLT_DECIMAL_DIG__ 9RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charPWR_CR2_PVDFT_2V5 0x03rcc_css_disable__SIG_ATOMIC_TYPE__ intRCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX__RCC_CFGR_MCOPRE_DIV32 5INT8_MINRCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_APBRSTR1_DBGRST (1 << 27)__FLT32X_MIN_EXP__ (-1021)RCC_AHBSMENR_SRAMSMEN (1 << 9)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)FLASH_OPTR_BORF_LEV_SHIFT 9__GCC_ATOMIC_CHAR_LOCK_FREE 1RCC_CCIPR_LPTIM1SEL_SHIFT 18cm3_assert_not_reached() cm3_assert_failed()__LFRACT_EPSILON__ 0x1P-31LRRCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_CIFR_HSERDYF (1 << 4)RCC_CCIPR_USART2SEL_SYSCLK 1RCC_CCIPR_I2S1SEL_SHIFT 14RCC_ICSCR_HSICAL_MASK 0xff__ARM_SIZEOF_MINIMAL_ENUM 1__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_APBRSTR1_TIM3RST (1 << 1)__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CR_HSIDIV_DIV16 4__FLT32_MIN_10_EXP__ (-37)RCC_APBSMENR2_SYSCFGSMEN (1 << 0)MMIO64(addr) (*(volatile uint64_t *)(addr))RCC_APBENR1_TIM7EN (1 << 5)__ARM_FP16_FORMAT_ALTERNATIVEFLASH_SR_OPERR (1 << 1)__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)FLASH_CR_LOCK (1 << 31)RCC_AHBRSTR_RNGRST (1 << 18)DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8RCC_SPI1/build/libopencm3/lib/stm32/g0__TA_IBIT__ 64__ARM_FEATURE_SIMD32FLASH_OPTR_BORR_LEV_2V3 1USART3_BASE (PERIPH_BASE_APB + 0x4800)RCC_CCIPR_LPTIM1SEL_LSI 1__SACCUM_IBIT__ 8__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1RCC_PLLCFGR_PLLP_SHIFT 17__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3RCC_CCIPR_I2S1SEL_MASK 0x3FLASH_ECCR_SYSF_ECC (1 << 20)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)RCC_CR_HSIDIV_DIV128 7_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ULACCUM_MIN__ 0.0ULK__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)FLASH_OPTR_IRHEN (1 << 29)LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)RCC_APBSMENR2_TIM17SMEN (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1RCC_APBSMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_I2C1SEL_PCLK 0PWR_CR1_LPMS_SHUTDOWN 4__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7PWR_CR2_PVDFT_2V4 0x02INT32_MAXrcc_set_sysclk_sourceRCC_BDCR_BDRST (1 << 16)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_AHBENR_CRCEN (1 << 12)__ARM_FEATURE_CRYPTOFLASH_ACR_ICRST (1 << 11)__INT_LEAST32_TYPE__ long intRCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9PWR_SCR_CWUF5 (1 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2FLASH_ACR_LATENCY_SHIFT 0BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RCC_AHBRSTR_FLASHRST (1 << 8)__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63PWR_CR3_APC (1 << 10)INT_LEAST64_MAXuint16_treg32__UHQ_IBIT__ 0PWR_CR2_PVDRT_2V6 0x03INT_LEAST8_MININTMAX_C(c) __INTMAX_C(c)BIT29 (1<<29)__INT_FAST16_TYPE__ intFLASH_OPTR_BORR_LEV_2V6 2__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_ADCSEL_SYSCLK 0__UINT_LEAST16_TYPE__ short unsigned intFLASH_PCROP1BSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34)__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intFLASH_CR_OPTSTRT (1 << 17)__FLT32X_DIG__ 15RCC_APBSMENR1_SPI2SMEN (1 << 14)RCC_CIFR_LSIRDYF (1 << 0)PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)FLASH_OPTR_BORF_LEV_MASK 0x03__UTQ_FBIT__ 128PWR_CR2_PVDRT_2V9 0x05FLASH_SR_WRPERR (1 << 4)__LLACCUM_EPSILON__ 0x1P-31LLK__ULLACCUM_IBIT__ 32RCC_CR_HSEBYP (1 << 18)__INT_FAST16_MAX__ 0x7fffffffRCC_APBSMENR2_SPI1SMEN (1 << 12)FLASH_CR_STRT (1 << 16)PTRDIFF_MAX __PTRDIFF_MAX__PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)FLASH_ACR_LATENCY_0WS 0x00FLASH_PCROP1ASR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24)RCC_CR_PLLRDY (1 << 25)I2C2_BASE (PERIPH_BASE_APB + 0x5800)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CLOCK_CONFIG_LSI_32KHZRCC_CR_HSIDIV_DIV2 1RCC_CCIPR_RNGSEL_PLLQCLK 3rcc_set_hsisys_divFLASH_OPTR_RDP_LEVEL_1 0xBBUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)RCC_DMA1FLASH_CR_EOPIE (1 << 24)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intFLASH_ECCR_ECCIE (1 << 24)FLASH_OPTR_IWDG_STDBY (1 << 18)RCC_CCIPR_LPTIM2SEL_LSE 3RCC_BDCR_LSEDRV_HIGH 3GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)RCC_APBRSTR1_UCPD2RST (1 << 26)WCHAR_MINPWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3FLASH_OPTR_BORF_LEV_2V8 3pllsrcRCC_CFGR_SWS_LSE 0x4BEGIN_DECLS FLASH_SR_MISERR (1 << 8)rcc.cRNG_BASE (PERIPH_BASE_AHB + 0x05000)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)FLASH_OPTR_RDP_MASK 0xffRCC_CFGR_SW_LSI 0x3RCC_CFGR_PPRE_MASK 0x7CORESIGHT_LSR_SLK (1<<1)RCC_CLOCK_CONFIG_HSI_PLL_32MHZ__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xPWR_CR3_EWUP4 (1 << 3)FLASH_CR_SEC_PROT (1 << 28)__ARM_EABI__ 1INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1INT64_MIN (-INT64_MAX - 1)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)__QQ_IBIT__ 0FLASH_OPTR_BORF_LEV_2V2 1SCC_TIM14SCC_TIM15SCC_TIM16SCC_TIM17RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31PWR_CR1_LPMS_MASK 0x07__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intUINTPTR_MAX__GCC_ATOMIC_INT_LOCK_FREE 1PWR_CR3_ULPEN (1 << 9)RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)periphINTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)FLASH_CR_PG (1 << 0)RCC_CCIPR_LPTIM1SEL_PCLK 0RCC_PLL__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_USART2FLASH_ACR_DBG_SWEN (1 << 18)__FLT64_HAS_QUIET_NAN__ 1FLASH_ACR_LATENCY_1WS 0x01LIBOPENCM3_CM3_ASSERT_H __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCC_USART1SCC_USART2SCC_USART3SCC_USART4INT64_MINRCC_BDCR_RTCSEL_NONE 0__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned int__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APBSMENR1_LPUART1SMEN (1 << 20)PWR_CR2_PVDRT_PVD_IN 0x07__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4PWR_CR1_VOS_RANGE_1 1__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LL__LDBL_MIN_10_EXP__ (-307)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)FLASH_ECCR_ECCD (1 << 31)SCC_UCPD1SCC_UCPD2__LDBL_MIN__ 2.2250738585072014e-308LTIM15_BASE (PERIPH_BASE_APB + 0x14000)FLASH_PCROP1BER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16_REG_BIT(offset,bit) (((offset) << 5) + (bit))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1RCC_CCIPR_TIM15SEL_SHIFT 24INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)SCC_LPUART1short intRCC_APBRSTR1_TIM6RST (1 << 4)rcc_get_spi_clk_freq__FLT32_IS_IEC_60559__ 2__UINT16_C(c) cFLASH_SR_PGAERR (1 << 5)__UDA_IBIT__ 32FLASH_PCROP1AER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28)UINT_LEAST32_MAXrcc_set_peripheral_clk_selRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)CORESIGHT_LSR_SLI (1<<0)RCC_BDCR_LSEDRV_MASK 0x3BIT5 (1<<5)sysclock_sourceUSART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXflash_set_ws__USES_INITFINI__ 1voltage_scaleSCC_I2C1SCC_I2C2RCC_APBENR1_LPUART1EN (1 << 20)RCC_TIM7__DBL_DECIMAL_DIG__ 17SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)RCC_SYSCFGFLASH_OPTR_BORR_LEV_2V9 3INT16_C(c) __INT16_C(c)RCC_CCIPR_I2S1SEL_PLLPLCK 1RCC_APBSMENR1_UCPD2SMEN (1 << 26)__INT16_MAX__ 0x7fffrcc_periph_clock_enable__INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)SCC_SYSCFG__QQ_FBIT__ 7FLASH_OPTR_nBOOT1 (1 << 25)RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)__ULLFRACT_EPSILON__ 0x1P-64ULLRPOWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_CCIPR_I2C1SEL_MASK 0x3INT16_CPWR_CR1_FPD_STOP (1 << 3)RCC_AHBSMENR_DMASMEN (1 << 0)__UTA_IBIT__ 64RCC_CCIPR_I2S1SEL_I2S_CKIN 2RCC_CICR_CSSC (1 << 8)signed char__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4RCC_APBRSTR2_SPI1RST (1 << 12)PWR_CR1_LPMS_SHIFT 0__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1RCC_USART1__USACCUM_FBIT__ 8mcoprePWR_CR2_PVDRT_2V7 0x04__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32rcc_set_hpreBIT1 (1<<1)RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)RCC_I2C1RCC_I2C2RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2RCC_CCIPR_TIM1SEL_PLLQCLK 1SCC_TIM2GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_APBSMENR1_USART4SMEN (1 << 19)RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1RCC_APBSMENR2_USART1SMEN (1 << 14)FLASH_KEYR_KEY1 ((uint32_t)0x45670123)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30)RCC_AHBRSTR_AESRST (1 << 16)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tFLASH_ACR_LATENCY_2WS 0x02BIT12 (1<<12)RCC_CCIPR_LPTIM2SEL_HSI16 2RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CIFR_PLLRDYF (1 << 5)FLASH_OPTR_nBOOT0 (1 << 26)RCC_CFGR_SW_SHIFT 0RCC_APBRSTR1_LPUART1RST (1 << 20)__UINT_FAST16_TYPE__ unsigned intRCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)PWR_SR1_WUF4 (1 << 3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKFLASH_ECCR_ADDR_ECC_MASK 0x3fff__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)rcc_set_ppre__WINT_MIN__ 0UINT_LEAST16_MINFLASH_OPTR_IDWG_SW (1 << 16)PWR_SCR_CWUF1 (1 << 0)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_CEC__INT_LEAST16_TYPE__ short intRCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)RCC_APBRSTR2_TIM14RST (1 << 15)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RCC_CCIPR_TIM15SEL_MASK 0x1__thumb__ 1RCC_CCIPR_RNGSEL_NONE 0INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RCC_APBSMENR1_TIM2SMEN (1 << 0)RCC_FLASHFLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)PWR_SR1_SBF (1 << 8)rcc_set_main_pll__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_SHIFT 30RCC_CLOCK_CONFIG_ENDBIT26 (1<<26)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)PWR_CR1_VOS_RANGE_2 2__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)__LONG_MAX__ 0x7fffffffLrcc_get_div_from_hpreRCC_CCIPR_USART2SEL_HSI16 2RCC_CCIPR_ADCSEL_HSI16 2RCC_AHBENR_OFFSET 0x38INT_LEAST64_MINPTRDIFF_MAXRCC_AHBSMENR_CRCSMEN (1 << 12)hprePWR_CR1_DBP (1 << 8)RCC_PLLCFGR_PLLN_SHIFT 0x8__USQ_FBIT__ 32RCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__RCC_CFGR_MCO_LSI 0x6WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32pll_sourceRCC_USART3RCC_USART4RCC_APBRSTR1_USART3RST (1 << 18)__ATOMIC_ACQ_REL 4RCC_CCIPR_LPUART1SEL_PCLK 0__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)PWR_CR4_VBRS (1 << 9)__ULLFRACT_FBIT__ 64__INT16_TYPE__ short intRCC_CR_CSSON (1 << 19)RCC_CFGR_PPRE_DIV2 0x4RCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32PWR_CR4_WP2 (1 << 1)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULLFLASH_ECCR_ADDR_ECC_SHIFT 0__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)RCC_CR_HSION (1 << 8)INT_FAST16_MAXRCC_CSR_RMVF (1 << 23)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_PLLCFGR_PLLQEN (1 << 24)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCPWR_SCALE1PWR_SR2_REGLPS (1 << 8)PWR_SCALE2pprepllmGCC: (15:12.2.rel1-1) 12.2.1 20221205 | PDPAXALAA    $A (A $A  $ $ $    A B<B  B A+aeabi!6S-M M    P< D @ @  !:+9!! !5:###$$ $%%%&&&'''((()))***+++,,,...//p/11,13335557779:;;<<==>@ACEG_aIKMOQSUWY[]c?f+_   be   Pfx<=PXL#4$J b(!}#$$$%$&$'()*+ ,5GTj./<13 5 7x;rcc.c$trcc_get_clksel_freq$dCSWTCH.13CSWTCH.15CSWTCH.17wm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.pwr.h.29.ddfee424ee321ef744c4f2c8fdc8b82ewm4.rcc.h.38.6d5bd27c58b50474703b74eac4d276eawm4.flash.h.36.4f6d705bc81e2f76c8a1781a03348953wm4.assert.h.49.015b362b73716e3cc7cc0fcda59cfa2ercc_get_div_from_hprecm3_assert_failedrcc_apb1_frequencyrcc_ahb_frequencyrcc_osc_on__gnu_thumb1_case_uqircc_osc_offrcc_is_osc_readyrcc_wait_for_osc_readyrcc_css_enablercc_css_disablercc_css_int_clearrcc_css_int_flagrcc_set_sysclk_sourcercc_system_clock_sourcercc_wait_for_sysclk_statusrcc_set_pll_sourcercc_set_main_pllrcc_enable_pllprcc_enable_pllqrcc_enable_pllrrcc_set_pprercc_set_hprercc_set_hsisys_divrcc_set_mcoprercc_clock_setuprcc_periph_clock_enablepwr_set_vos_scaleflash_set_wsflash_prefetch_enableflash_prefetch_disablercc_set_rng_clk_divrcc_set_peripheral_clk_selrcc_get_usart_clk_freqrcc_get_timer_clk_freqrcc_get_i2c_clk_freqrcc_get_spi_clk_freqrcc_clock_config& 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VY04\.symtab.strtab.shstrtab.text.data.bss.rel.text.rcc_get_clksel_freq.rel.text.rcc_osc_on.rel.text.rcc_osc_off.rel.text.rcc_is_osc_ready.rel.text.rcc_wait_for_osc_ready.text.rcc_css_enable.text.rcc_css_disable.text.rcc_css_int_clear.text.rcc_css_int_flag.rel.text.rcc_set_sysclk_source.rel.text.rcc_system_clock_source.rel.text.rcc_wait_for_sysclk_status.text.rcc_set_pll_source.text.rcc_set_main_pll.text.rcc_enable_pllp.text.rcc_enable_pllq.text.rcc_enable_pllr.text.rcc_set_ppre.text.rcc_set_hpre.text.rcc_set_hsisys_div.text.rcc_set_mcopre.rel.text.rcc_clock_setup.text.rcc_set_rng_clk_div.rel.text.rcc_set_peripheral_clk_sel.rel.text.rcc_get_usart_clk_freq.rel.text.rcc_get_timer_clk_freq.rel.text.rcc_get_i2c_clk_freq.rel.text.rcc_get_spi_clk_freq.rodata.CSWTCH.15.rodata.CSWTCH.13.rodata.rcc_clock_config.data.rcc_apb1_frequency.data.rcc_ahb_frequency.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.group.4 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,!5-FX.o/30X1!2Vl3\#4150'6r7w8C%9-+:,;<= >J?$I@g:A) B,JCD-E?FFTG*L^MLNzO/P=Q,ST(Y&Ze_[o\ []Q^h_*2`UcidMxe{kw7lmg+n5tBuCz {p|+} ~|O_!_T#T88y!a'xeB:@3z(U(( GT8{Y 4j9r:85'=sGa&TaZ;r da +:oA8Q+,pT- x#_ 9WF,JzH@2!)/[N irP?9]tmINW|:SzqZHN "!H$P` -^KrAd=y u 6}hQ,'bBm&Tbd$YUg!UI nvjr3TG/c M!qdR%N,2/U"lOt/xA5w F5GO;+ uIk)`K;@fo2]Mp?u>xTV>c  q^t?R1*>v/N6fwaC4~%K"`->u z_?h'"[pkpnU)=qA`xPdT.YKwQ,rkWmm p"HNO<y42^ >`R.Q/wp))0"\EBZ3.fvXPtaUe_>G c(;j\i;<[` j2[he #s#p KG'.{wn9*}u ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/commonrcc_common_all.cstdint.hrcc.hrcc.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hpwr.hpwr.hrcc_common_all.h.!/!/<! . /! .</<" . / /   !E  "Js      &0y    Js      &"y    .11 " 0 /"0RCC_CCIPR_RNGDIV_2 1RCC_CICR_PLLRDYC (1 << 5)RCC_CR_HSEBYP (1 << 18)RCC_AHBSMENR_DMASMEN (1 << 0)__DECIMAL_DIG__ 17RCC_CCIPR_LPTIM1SEL_MASK 0x3__UHA_FBIT__ 8PERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_SR1_WUF1 (1 << 0)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)RCC_APBSMENR2_TIM14SMEN (1 << 15)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1RCC_CSR_LSION (1 << 0)STM32G0 1RCC_CCIPR_RNGSEL_SYSCLK 2RCC_CICR_LSECSSC (1 << 9)__FLT64_HAS_INFINITY__ 1rcc_periph_reset_pulse__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffPWR_SR2_REGLPF (1 << 9)RCC_AHBSMENR_RNGSMEN (1 << 18)__INTMAX_C(c) c ## LLTIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0rcc_periph_clken__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_DBG__ARM_FEATURE_QBITLIBOPENCM3_RCC_COMMON_ALL_H RCC_APBRSTR2_TIM15RST (1 << 16)SCC_CECRCC_BDCR MMIO32(RCC_BASE + 0x5c)RCC_APBSMENR1_PWRSMEN (1 << 28)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0rcc_periph_rst__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9RCC_AHBRSTR_CRCRST (1 << 12)DESIG_FLASH_SIZE_BASE (0x1FFF75E0)__LDBL_MIN_EXP__ (-1021)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)WWDG_BASE (PERIPH_BASE_APB + 0x2c00)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__CHAR32_TYPE__ long unsigned int__WINT_TYPE__ unsigned intRCC_APBSMENR1_RTCAPBSMEN (1 << 10)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_PLLCFGR_PLLP_MASK 0x1fUINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4PWR_CR3_EIWUL (1 << 15)RCC_CIER_LSIRDYIE (1 << 0)RCC_CR_HSIRDY (1 << 10)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0RCC_CFGR_PPRE_MASK 0x7INT_FAST64_MAX __INT_FAST64_MAX__RCC_PLLCFGR_PLLM_SHIFT 0x4rcc_set_mco__INT_FAST8_TYPE__ int__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intrcc_peripheral_enable_clockRCC_CCIPR_RNGSEL_HSI16 1RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long intRCC_CFGR_SW_LSE 0x4RCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR1_OFFSET 0x4cINT32_MIN (-INT32_MAX - 1)RCC_CCIPR_CECSEL_HSI16 0__FLT32_MAX_10_EXP__ 38RCC_CFGR_HPRE_DIV8 0xaRCC_CFGR_SW_PLLRCLK 0x2SCC_DBGRCC_APBENR1_DBGEN (1 << 27)__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZ__UINTPTR_MAX__ 0xffffffffURCC_APBSMENR1_DAC1SMEN (1 << 29)__FLT32_MIN_EXP__ (-125)RCC_CSR_LPWRRSTF (1 << 31)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))RCC_CFGR_MCOPRE_DIV1 0PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901Lrcc_peripheral_disable_clockRCC_APBRSTR1_SPI2RST (1 << 14)RCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRRCC_CFGR_HPRE_SHIFT 8RCC_IOPSMENR_OFFSET 0x44__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__THUMB_INTERWORK__ 1__SQ_FBIT__ 31RCC_APBENR2_TIM16EN (1 << 17)RST_SYSCFGRCC_APBSMENR1_USART2SMEN (1 << 17)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)__UHQ_FBIT__ 16RCC_AHBSMENR_FLASHSMEN (1 << 8)__FLT64_MIN_EXP__ (-1021)clear_resetDMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)PWR_SR2_VOSF (1 << 10)UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)__LACCUM_IBIT__ 32PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_SCR_CWUF2 (1 << 1)RCC_APBENR1_PWREN (1 << 28)__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXPWR_SR2_PVDO (1 << 11)RCC_APBSMENR1_WWDGSMEN (1 << 11)__UINT_FAST16_MAX__ 0xffffffffURCC_CCIPR_TIM15SEL_MASK 0x1LPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CCIPR_TIM1SEL_MASK 0x1BIT21 (1<<21)RCC_CCIPR_USART1SEL_SHIFT 0SCC_SPI1SCC_SPI2__UFRACT_MIN__ 0.0UR__LDBL_HAS_QUIET_NAN__ 1RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)RCC_APBRSTR2_ADCRST (1 << 20)INT8_C(c) __INT8_C(c)RCC_PWRRCC_APBRSTR2_TIM17RST (1 << 18)__ACCUM_FBIT__ 15RCC_APBRSTR1_TIM2RST (1 << 0)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)PWR_CR2_PVDRT_2V2 0x01__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_APBSMENR1_LPTIM2SMEN (1 << 30)NVIC_BASE (SCS_BASE + 0x0100)UINTPTR_MAXBIT13 (1<<13)__UDA_FBIT__ 32PWR_SCR_CWUF4 (1 << 3)RCC_APBENR2_SPI1EN (1 << 12)__FLT64_MAX_10_EXP__ 308RCC_APBENR2_OFFSET 0x40__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_APBSMENR2_OFFSET 0x50__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHBENR_DMAEN (1 << 0)__UINTMAX_TYPE__ long long unsigned int__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_PLLCFGR_PLLREN (1<<28)GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)PWR_CR4_WP1 (1 << 0)BIT7 (1<<7)UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)RCC_APBENR1_I2C1EN (1 << 21)RCC_CCIPR_I2S1SEL_HSI16 2UINT8_MAX __UINT8_MAX__SCC_LPUART1SIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_SPI2LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CCIPR_LPTIM2SEL_MASK 0x3__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_CFGR_SW_HSISYS 0x0RCC_APBRSTR1_TIM7RST (1 << 5)PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)RCC_CCIPR_RNGDIV_1 0__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RST_CRCRCC_CCIPR_CECSEL_MASK 0x1RCC_APBENR1_UCPD2EN (1 << 26)RCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST8_MAX__ 0x7fffffffBIT27 (1<<27)SCC_PWRRCC_LPUART1RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APBRSTR1_LPTIM2RST (1 << 30)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)RCC_CCIPR_USART2SEL_SHIFT 2RCC_CCIPR_LPTIM2SEL_SHIFT 20__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_APBENR1_UCPD1EN (1 << 25)__FLT_DECIMAL_DIG__ 9PWR_CR2_PVDRT_3V0 0x06__thumb__ 1RCC_LSILIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1SPI2_BASE (PERIPH_BASE_APB + 0x3800)__INT64_C(c) c ## LL__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__FLT_HAS_QUIET_NAN__ 1RCC_TIM2__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)PTRDIFF_MIN__UINT_LEAST16_MAX__ 0xffffRCC_TIM6__FLT32_HAS_QUIET_NAN__ 1UINTPTR_MAX __UINTPTR_MAX__RCC_BDCR_RTCEN (1 << 15)__LACCUM_FBIT__ 31RCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_PPRE_DIV8 0x6__FLT_DIG__ 6MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRST_DMARCC_ICSCR_HSITRIM_MASK 0x1fRCC_APBENR1_TIM2EN (1 << 0)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RCC_APBSMENR2_TIM15SMEN (1 << 16)__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)SCC_DMA1RCC_APBENR1_WWDGEN (1 << 11)RCC_APBRSTR1_DAC1RST (1 << 29)__INT_FAST32_MAX__ 0x7fffffffRCC_CFGR_MCOPRE_DIV64 6__ARM_ARCH_EXT_IDIV__RCC_CIER_PLLRDYIE (1 << 5)ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))__DQ_IBIT__ 0RCC_APBRSTR1_OFFSET 0x2cRCC_APBENR1_LPTIM2EN (1 << 30)PWR_CR2_PVDFT_2V0 0x00__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)RCC_RNGTIM14_BASE (PERIPH_BASE_APB + 0x2000)RCC_CCIPR_TIM15SEL_PLLQCLK 1__USQ_FBIT__ 32RCC_CCIPR_USART1SEL_SYSCLK 1INT_FAST16_MINRCC_CCIPR_RNGDIV_8 3WCHAR_MAXRCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32RCC_APBRSTR2_OFFSET 0x30PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)RST_SPI1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)PWR_CR2_PVDRT_2V6 0x03UINT_LEAST8_MAXRST_DMA1UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RCC_AHBENR_AESEN (1 << 16)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__TIM7_BASE (PERIPH_BASE_APB + 0x1400)__USA_IBIT__ 16PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)RCC_APBENR1_TIM6EN (1 << 4)__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)RCC_CFGR_SWS_PLLRCLK 0x2__FLT_MIN__ 1.1754943508222875e-38FRCC_CR_HSIDIV_DIV1 0__HA_FBIT__ 7RCC_APBRSTR2_TIM1RST (1 << 11)__FDPIC__RST_GPIOARCC_GPIOARCC_GPIOBRCC_GPIOCRST_GPIOERCC_GPIOERCC_GPIOFRCC_IOPENR_OFFSET 0x34RCC_CSR_PINRSTF (1 << 26)RCC_CFGR_MCO_PLLRCLK 0x5INT_FAST64_MINRCC_CCIPR_TIM15SEL_TIMPCLK 0__USFRACT_IBIT__ 0RCC_CFGR_SWS_SHIFT 3PWR_CR2_PVDRT_MASK 0x07__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7SPI1_BASE (PERIPH_BASE_APB + 0x13000)__USFRACT_MIN__ 0.0UHRRCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONPWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024SCC_LPTIM1SCC_LPTIM2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfSCC_RNG__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_CCIPR_LPTIM2SEL_PCLK 0RCC_CCIPR_USART2SEL_LSE 3RCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_CCIPR_USART1SEL_MASK 0x3__DA_FBIT__ 31BIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3RST_GPIOC__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_CSR MMIO32(RCC_BASE + 0x60)_REG_BIT(offset,bit) (((offset) << 5) + (bit))RST_GPIOFRST_RNGCOMP_BASE (PERIPH_BASE_APB + 0x10200)RCC_APBENR1_OFFSET 0x3cINT_LEAST8_MAX __INT_LEAST8_MAX__RCC_ICSCR_HSICAL_SHIFT 0PWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29__UINT32_C(c) c ## ULRCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)RCC_CFGR_MCOPRE_DIV4 2__UACCUM_MIN__ 0.0UKRCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR2_PVDRT_2V5 0x02RCC_PLLCFGR_PLLSRC_SHIFT 0RCC_CCIPR_I2S1SEL_SYSCLK 0RST_ADCRCC_APBENR2_ADCEN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0RCC_PLLCFGR_PLLPEN (1 << 16)__ATOMIC_ACQ_REL 4__USACCUM_FBIT__ 8RST_GPIOB__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2SCC_DAC1RCC_BDCR_LSCOSEL (1 << 25)__ELF__ 1SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)PWR_CR1_VOS_SHIFT 9INT8_MAXRCC_CCIPR_USART2SEL_PCLK 0RCC_CSR_OBLRSTF (1 << 25)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308RCC_APBENR2_TIM1EN (1 << 11)__ARM_PCS 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_CCIPR_ADCSEL_SYSCLK 0RCC_CRCRCC_APBENR2_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCC_TIM1SCC_TIM2SCC_TIM3RCC_CCIPR_USART1SEL_PCLK 0SCC_TIM6SCC_TIM7__FLT32X_IS_IEC_60559__ 2PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)RST_AESEXTI_BASE (PERIPH_BASE_AHB + 0x01800)RST_GPIODLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)RCC_CR_HSIDIV_DIV64 6RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04RCC_BDCR_LSERDY (1 << 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APBSMENR1_USART3SMEN (1 << 18)RCC_APBENR2_TIM17EN (1 << 18)RCC_CCIPR_CECSEL_SHIFT 6RCC_DAC1__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRCC_APBENR1_USART4EN (1 << 19)PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)PWR_CR1_VOS_MASK 0x3RCC_AHBRSTR_OFFSET 0x28__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_LPUART1SEL_LSE 3RCC_DMARCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_RNGDIV_SHIFT 28__INT_LEAST8_MAX__ 0x7fRCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIVRCC_HSE__ARM_FEATURE_COMPLEXPWR_CR2_PVDFT_2V8 0x05DAC_BASE (PERIPH_BASE_APB + 0x7400)RCC_HSICEC_BASE (PERIPH_BASE_APB + 0x7800)RST_TIM14RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RST_TIM16RCC_CCIPR_ADCSEL_PLLPCLK 1RST_TIM17RCC_TIM1SCC_CRCRCC_TIM3__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fRST_I2C2BIT14 (1<<14)RCC_ICSCR_HSITRIM_SHIFT 8__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV512 0xfPWR_SR2_FLASHRDY (1 << 8)RCC_CFGR_MCO_SYSCLK 0x1__SOFTFP__ 1PWR_CR2_PVDFT_2V2 0x01UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RRCC_CFGR_PPRE_SHIFT 12BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffLPWR_CR4_WP6 (1 << 5)RCC_PLLCFGR_PLLR_MASK 0x7RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_SW_MASK 0x3__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCC_DMALIBOPENCM3_RCC_H PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32rcc_osc_bypass_enable__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intRCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1SCC_GPIOF__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_CCIPR_LPTIM2SEL_LSI 1__UDQ_IBIT__ 0RCC_CFGR_SWS_HSISYS 0x0RCC_CR_HSERDY (1 << 17)SCC_FLASH__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_APBSMENR1_TIM2SMEN (1 << 0)RCC_CCIPR_CECSEL_LSE 1RCC_APBSMENR2_TIM16SMEN (1 << 17)PWR_CR1_LPMS_STOP_0 0__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)RCC_LPTIM1RCC_LPTIM2RCC_APBSMENR1_TIM3SMEN (1 << 1)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)RCC_CIFR_HSIRDYF (1 << 3)__GNUC__ 12RST_LPTIM1RST_LPTIM2mcosrcRCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1CRC_BASE (PERIPH_BASE_AHB + 0x03000)RCC_ADCRCC_APBENR2_SYSCFGEN (1 << 0)__ARM_ARCH 6RCC_LSEPWR_CR2_PVDFT_2V9 0x06RCC_PLLCFGR_PLLQ_SHIFT 25__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55PWR_CR3_EWUP4 (1 << 3)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXSCC_GPIOASCC_GPIOBSCC_GPIOCSCC_GPIODSCC_GPIOE__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28RCC_APBRSTR2_USART1RST (1 << 14)__UINT_FAST64_MAX__ 0xffffffffffffffffULLINFO_BASE (0x1fff7500U)__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024PWR_SR1_WUFI (1 << 15)UINT16_MAXBIT20 (1<<20)__FLT64_MIN__ 2.2250738585072014e-308F64GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsPWR_CR2_PVDFT_MASK 0x07PWR_CR1_LPMS_STANDBY 3RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))LIBOPENCM3_PWR_H RCC_AHBSMENR_SRAMSMEN (1 << 9)RCC_CCIPR MMIO32(RCC_BASE + 0x54)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)RCC_AES__UFRACT_MAX__ 0XFFFFP-16URRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)RCC_SYSCFGPWR_CR2_PVDRT_2V1 0x00PWR_CR3_EWUP2 (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_APBENR1_USART3EN (1 << 18)RCC_CFGR_SWS_HSE 0x1SCC_ADC__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RCC_TIM14RCC_TIM15RCC_TIM16RCC_TIM17SYS_TICK_BASE (SCS_BASE + 0x0010)rcc_oscRCC_CCIPR_I2C1SEL_HSI16 2RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHBRSTR_DMARST (1 << 0)__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_AHBSMENR_OFFSET 0x48__LDBL_MAX_10_EXP__ 308RCC_APBENR1_DAC1EN (1 << 29)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)reset__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)RCC_APBSMENR1_DBGSMEN (1 << 27)__ATOMIC_SEQ_CST 5__GCC_ASM_FLAG_OUTPUTS__RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)../common/rcc_common_all.c__FLT_MIN_EXP__ (-125)__DEC_EVAL_METHOD__ 2RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)RCC_CCIPR_RNGDIV_4 2ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32_STDBOOL_H PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)RCC_APBRSTR1_I2C1RST (1 << 21)SCB_BASE (SCS_BASE + 0x0D00)__FLT_EVAL_METHOD__ 0unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CR_PLLON (1 << 24)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXSCC_AES__UQQ_FBIT__ 8PWR_CR4_WP5 (1 << 4)INT16_CRCC_APBENR1_SPI2EN (1 << 14)RST_UCPD1RCC_UCPD1RCC_UCPD2INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_APBSMENR1_TIM7SMEN (1 << 5)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__rcc_periph_clock_disable__UINT8_TYPE__ unsigned charPWR_CR2_PVDFT_2V5 0x03__UINT_LEAST8_TYPE__ unsigned charRCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"RCC_CFGR_MCOPRE_DIV32 5INT8_MIN__ORDER_PDP_ENDIAN__ 3412RCC_CCIPR_LPUART1SEL_MASK 0x3RCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)RCC_APBRSTR1_DBGRST (1 << 27)__FLT32X_MIN_EXP__ (-1021)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 1RCC_CCIPR_LPTIM1SEL_SHIFT 18__LFRACT_EPSILON__ 0x1P-31LRRCC_CIFR_HSERDYF (1 << 4)RCC_CCIPR_USART2SEL_SYSCLK 1RCC_CCIPR_I2S1SEL_SHIFT 14RCC_PLLCFGR_PLLQ_MASK 0x7__ARM_SIZEOF_MINIMAL_ENUM 1__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_APBRSTR1_TIM3RST (1 << 1)__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CR_HSIDIV_DIV16 4__FLT32_MIN_10_EXP__ (-37)RCC_APBSMENR2_SYSCFGSMEN (1 << 0)MMIO64(addr) (*(volatile uint64_t *)(addr))RCC_APBENR1_TIM7EN (1 << 5)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)RCC_GPIODRCC_AHBRSTR_RNGRST (1 << 18)DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8RCC_SPI1/build/libopencm3/lib/stm32/g0INT_LEAST64_MAX __INT_LEAST64_MAX____ARM_FEATURE_SIMD32USART3_BASE (PERIPH_BASE_APB + 0x4800)RCC_CCIPR_LPTIM1SEL_LSI 1__SACCUM_IBIT__ 8__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1RCC_PLLCFGR_PLLP_SHIFT 17WCHAR_MIN __WCHAR_MIN__RCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3__USQ_IBIT__ 0BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)RCC_CR_HSIDIV_DIV128 7_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ULACCUM_MIN__ 0.0ULK__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)RCC_APBSMENR2_TIM17SMEN (1 << 18)_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1rcc_peripheral_clear_resetPWR_CR1_LPMS_SHUTDOWN 4__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7PWR_CR2_PVDFT_2V4 0x02INT32_MAXRCC_BDCR_BDRST (1 << 16)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_AHBENR_CRCEN (1 << 12)RCC_CIER MMIO32(RCC_BASE + 0x18)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9PWR_SCR_CWUF5 (1 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RCC_AHBRSTR_FLASHRST (1 << 8)__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63PWR_CR3_APC (1 << 10)INT_LEAST64_MAXuint16_t__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ int__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRST_SPI2__UINT_LEAST16_TYPE__ short unsigned intrcc_periph_reset_hold__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15RCC_APBSMENR1_SPI2SMEN (1 << 14)RCC_CIFR_LSIRDYF (1 << 0)PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)__UTQ_FBIT__ 128PWR_CR2_PVDRT_2V9 0x05__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffRCC_APBSMENR2_SPI1SMEN (1 << 12)PTRDIFF_MAX __PTRDIFF_MAX__rcc_periph_reset_releaseRCC_CR_PLLRDY (1 << 25)I2C2_BASE (PERIPH_BASE_APB + 0x5800)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CR_HSIDIV_DIV2 1RCC_CCIPR_RNGSEL_PLLQCLK 3UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)RCC_DMA1__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_CCIPR_LPTIM2SEL_LSE 3RCC_BDCR_LSEDRV_HIGH 3GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)RCC_APBRSTR1_UCPD2RST (1 << 26)WCHAR_MINRCC_CCIPR_RNGSEL_MASK 0x3PWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3RCC_CFGR_SWS_LSE 0x4BEGIN_DECLS PWR_CR2_PVDRT_PVD_IN 0x07RST_TIM2div_valRCC_CFGR_SW_LSI 0x3RST_LPUART1CORESIGHT_LSR_SLK (1<<1)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xRCC_APBRSTR2_TIM14RST (1 << 15)__FLT32_MIN__ 1.1754943508222875e-38F32INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1rcc_osc_bypass_disableDMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)RST_CEC__QQ_IBIT__ 0_RCC_BITSCC_TIM14SCC_TIM15SCC_TIM16SCC_TIM17RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31PWR_CR1_LPMS_MASK 0x07__GNUC_MINOR__ 2__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1_RCC_BIT(i) (1 << ((i) & 0x1f))PWR_CR3_ULPEN (1 << 9)RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)rcc_peripheral_resetRCC_CCIPR_LPTIM1SEL_PCLK 0RCC_PLL__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__FLT64_HAS_QUIET_NAN__ 1__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCC_USART1SCC_USART2SCC_USART3SCC_USART4INT64_MINRCC_BDCR_RTCSEL_NONE 0__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned int__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APBSMENR1_LPUART1SMEN (1 << 20)__SIZEOF_SIZE_T__ 4PWR_CR1_VOS_RANGE_1 1__UINT64_TYPE__ long long unsigned int__LDBL_MIN_10_EXP__ (-307)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)SCC_UCPD1SCC_UCPD2__LDBL_MIN__ 2.2250738585072014e-308LTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0RCC_CCIPR_TIM15SEL_SHIFT 24RCC_BDCR_LSEON (1 << 0)short intRCC_APBRSTR1_TIM6RST (1 << 4)__FLT32_IS_IEC_60559__ 2__UINT16_C(c) c__UDA_IBIT__ 32UINT_LEAST32_MAXRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)CORESIGHT_LSR_SLI (1<<0)RCC_BDCR_LSEDRV_MASK 0x3BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1SCC_I2C1SCC_I2C2RCC_APBENR1_LPUART1EN (1 << 20)RCC_TIM7__DBL_DECIMAL_DIG__ 17SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)BIT8 (1<<8)RST_TIM7clkenINT16_C(c) __INT16_C(c)RCC_CCIPR_I2S1SEL_PLLPLCK 1RCC_APBSMENR1_UCPD2SMEN (1 << 26)__INT16_MAX__ 0x7fffrcc_periph_clock_enable_RCC_REG__INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)SCC_SYSCFG__QQ_FBIT__ 7RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_CCIPR_I2C1SEL_MASK 0x3PWR_CR1_FPD_STOP (1 << 3)__UTA_IBIT__ 64RCC_CCIPR_I2S1SEL_I2S_CKIN 2RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRRST_DBG__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4RCC_APBRSTR2_SPI1RST (1 << 12)PWR_CR1_LPMS_SHIFT 0__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INTPTR_WIDTH__ 32__FLT32_HAS_DENORM__ 1RCC_USART1RCC_APBSMENR1_USART4SMEN (1 << 19)__FLT32X_HAS_DENORM__ 1PWR_CR2_PVDRT_2V7 0x04__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__TA_IBIT__ 64RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)RCC_I2C1RCC_I2C2RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2RCC_CCIPR_TIM1SEL_PLLQCLK 1RCC_PLLCFGR_PLLQEN (1 << 24)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_CCIPR_I2C1SEL_PCLK 0RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1RST_I2C1RCC_APBSMENR2_USART1SMEN (1 << 14)__ULLFRACT_MIN__ 0.0ULLRRST_UCPD2__PTRDIFF_WIDTH__ 32__ARM_FP16_ARGSRCC_AHBRSTR_AESRST (1 << 16)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tBIT12 (1<<12)RCC_CCIPR_LPTIM2SEL_HSI16 2RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CIFR_PLLRDYF (1 << 5)RST_DAC1RCC_CFGR_SW_SHIFT 0RCC_APBRSTR1_LPUART1RST (1 << 20)__UINT_FAST16_TYPE__ unsigned intRCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)PWR_SR1_WUF4 (1 << 3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINPWR_SCR_CWUF1 (1 << 0)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_CEC__INT_LEAST16_TYPE__ short intRTC_BASE (PERIPH_BASE_APB + 0x2800)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RST_TIM1UINTMAX_CRST_TIM3RCC_CCIPR_RNGSEL_NONE 0RST_TIM6INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RST_FLASHRCC_FLASHPWR_SR1_SBF (1 << 8)__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_SHIFT 30BIT26 (1<<26)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)PWR_CR1_VOS_RANGE_2 2__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)__LONG_MAX__ 0x7fffffffLrcc_get_div_from_hpreRCC_CCIPR_USART2SEL_HSI16 2RCC_CCIPR_I2S1SEL_MASK 0x3RCC_CCIPR_ADCSEL_HSI16 2RCC_AHBENR_OFFSET 0x38__PTRDIFF_TYPE__ intINT_LEAST64_MINPTRDIFF_MAXRCC_AHBSMENR_CRCSMEN (1 << 12)RNG_BASE (PERIPH_BASE_AHB + 0x05000)PWR_CR1_DBP (1 << 8)RCC_PLLCFGR_PLLN_SHIFT 0x8__ARM_ARCH_6M__ 1RCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__RCC_CFGR_MCO_LSI 0x6WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_USART2RCC_USART3RCC_USART4RST_TIM15RCC_APBRSTR1_USART3RST (1 << 18)RST_USART1RST_USART2RST_USART3RST_USART4RCC_CCIPR_LPUART1SEL_PCLK 0__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)PWR_CR4_VBRS (1 << 9)RCC_CFGR_MCO_HSI16 0x3__INT16_TYPE__ short intRCC_CR_CSSON (1 << 19)RST_PWRRCC_CFGR_PPRE_DIV2 0x4RCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32PWR_CR4_WP2 (1 << 1)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__INT_MAX__ 0x7fffffff__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)RCC_CR_HSION (1 << 8)INT_FAST16_MAXRCC_CSR_RMVF (1 << 23)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_CICR_LSERDYC (1 << 1)PWR_SR2_REGLPS (1 << 8)UINT32_CRCC_CFGR_MCOPRE_DIV16 4GCC: (15:12.2.rel1-1) 12.2.1 20221205 |       AA  ( , A+aeabi!6S-M M        !#%9;')+-/1357=?p8l <?  1Ib y(,rcc_common_all.c$t$dwm4.0.617b8dbbc34198d75911611823c9a3a2wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.991cbfb03a4e91ff777157049f1f9499wm4.memorymap.h.23.d106c532242e9726d4013db9fd1d7638wm4.pwr.h.29.ddfee424ee321ef744c4f2c8fdc8b82ewm4.rcc.h.38.6d5bd27c58b50474703b74eac4d276earcc_peripheral_enable_clockrcc_peripheral_disable_clockrcc_peripheral_resetrcc_peripheral_clear_resetrcc_periph_clock_enablercc_periph_clock_disablercc_periph_reset_pulsercc_periph_reset_holdrcc_periph_reset_releasercc_set_mcorcc_osc_bypass_enablercc_osc_bypass_disablercc_get_div_from_hpre O P& ,,,)"+&*-,4,;,B,G,T,Y,f,k,},,,,,,,,,,,,,,,,,,,,,#,*,1,8,?,F,M,T,[,b,i,p,w,~,,,,,,,,,,,,,,,,,,,, ,,,,&,-,4,;,B,I,P,W,^,e,l,s,z,,,,,,,,,,,,,,,,,,,,,,,%,,,3,:,A,H,O,V,],d,k,r,y,,,,,,,,,,,,,,,,,,,,, ,,,!,(,0,<#K,W'['a,f ,,,'',,,''",'6,@'D'J,O ^,h'l'r,,,,,, #(?Vm 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"  <0 #    1  >  0!     1!     1  !H8H  8   1  !! = !/" = =" =  =! = !/ !/! = !/! = !/# 0" /! = !/! /! /2  !!!!! /! /! /! /! /! /! /! /! /! /! /! /! /! /! /! /! /! /!2  ! ! !RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_CICR_PLLRDYC (1 << 5)RCC_CR_HSEBYP (1 << 18)RCC_AHBSMENR_DMASMEN (1 << 0)SCB_BASE (SCS_BASE + 0x0D00)RCC_CCIPR_LPTIM1SEL_MASK 0x3__FLT64_EPSILON__ 2.2204460492503131e-16F64SPI_I2SCFGR_DATLEN_LSB 1RCC_CCIPR_USART1SEL_PCLK 0PERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_SR1_WUF1 (1 << 0)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__INTMAX_C(c) c ## LL__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1RCC_CSR_LSION (1 << 0)STM32G0 1__SFRACT_FBIT__ 7RCC_AHBSMENR_RNGSMEN (1 << 18)RCC_CCIPR_RNGSEL_SYSCLK 2SPI_CR2_DS_14BIT (0xD << 8)__FLT64_HAS_INFINITY__ 1rcc_periph_reset_pulse__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffPWR_SR2_REGLPF (1 << 9)SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0PWR_CR4_WP2 (1 << 1)__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXSPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUSPI2_DR SPI_DR(SPI2_BASE)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_QBITLIBOPENCM3_RCC_COMMON_ALL_H SPI_CR2_DS_12BIT (0xB << 8)RCC_APBRSTR2_TIM15RST (1 << 16)RCC_BDCR MMIO32(RCC_BASE + 0x5c)RCC_APBSMENR1_PWRSMEN (1 << 28)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8spi_enable_rx_dma__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)__USACCUM_MAX__ 0XFFFFP-8UHKspi_xfer__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0rcc_periph_rst__SIZE_TYPE__ unsigned intSPI_CR1_BR_FPCLK_DIV_8 0x2PWR_CR3_EIWUL (1 << 15)spi_set_bidirectional_mode__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9RCC_AHBRSTR_CRCRST (1 << 12)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53SPI_SR_CRCERR (1 << 4)INT64_MIN (-INT64_MAX - 1)WWDG_BASE (PERIPH_BASE_APB + 0x2c00)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__INT16_TYPE__ short intRCC_APBRSTR2_TIM17RST (1 << 18)__FLT64_MAX__ 1.7976931348623157e+308F64SPI_CR1_RXONLY (1 << 10)RCC_PLLCFGR_PLLP_MASK 0x1fUINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3RCC_CIER_LSIRDYIE (1 << 0)RCC_CR_HSIRDY (1 << 10)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0SPI_I2SPR_ODD (1 << 8)INT_FAST64_MAX __INT_FAST64_MAX__RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_BDCR_LSEDRV_SHIFT 3__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RCC_CICR_LSECSSC (1 << 9)RCC_CCIPR_RNGSEL_HSI16 1RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intRCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR1_OFFSET 0x4cINT32_MIN (-INT32_MAX - 1)spi_set_clock_phase_1__FLT32_MAX_10_EXP__ 38RCC_AHBENR_CRCEN (1 << 12)RCC_CFGR_HPRE_DIV8 0xaRCC_CFGR_SW_PLLRCLK 0x2RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZSPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)__UINTPTR_MAX__ 0xffffffffURCC_APBSMENR1_DAC1SMEN (1 << 29)__FLT32_MIN_EXP__ (-125)SPI_CR2_LDMA_TX (1 << 14)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))RCC_CFGR_MCOPRE_DIV1 0PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)SPI_I2SCFGR_I2SCFG_LSB 8SPI_CR1_BR_FPCLK_DIV_128 0x6UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_APBRSTR1_SPI2RST (1 << 14)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)SPI_CR2_DS_15BIT (0xE << 8)RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRSPI_CR2_DS_4BIT (0x3 << 8)RCC_CFGR_HPRE_SHIFT 8RCC_IOPSMENR_OFFSET 0x44__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RCC_CCIPR_TIM15SEL_PLLQCLK 1RST_SYSCFGRCC_APBSMENR1_USART2SMEN (1 << 17)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)SPI_I2SPR_MCKOE (1 << 9)SPI3_CR1 SPI_CR1(SPI3_BASE)RCC_APBSMENR2_TIM15SMEN (1 << 16)__UHQ_FBIT__ 16RCC_AHBSMENR_FLASHSMEN (1 << 8)__FLT64_MIN_EXP__ (-1021)spi_writeINT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)LIBOPENCM3_RCC_H __UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)PWR_SR2_VOSF (1 << 10)UINT16_C(c) __UINT16_C(c)PWR_CR1_FPD_STOP (1 << 3)__LACCUM_IBIT__ 32PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_SCR_CWUF2 (1 << 1)RCC_CCIPR_LPTIM2SEL_HSI16 2__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_C__VERSION__ "12.2.1 20221205"RCC_CFGR_MCO_PLLRCLK 0x5__VFP_FP__ 1SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffPWR_SR2_PVDO (1 << 11)RCC_APBSMENR1_WWDGSMEN (1 << 11)__UINT_FAST16_MAX__ 0xffffffffURCC_CCIPR_TIM15SEL_MASK 0x1LPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11INT64_C(c) __INT64_C(c)RCC_CCIPR_TIM1SEL_MASK 0x1SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2RCC_APBRSTR2_ADCRST (1 << 20)SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URRCC_APBSMENR1_RTCAPBSMEN (1 << 10)SPI4 SPI4_BASEspi_disableWCHAR_MAX __WCHAR_MAX__RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)__UINT_LEAST8_TYPE__ unsigned charSPI_DR(spi_base) MMIO32((spi_base) + 0x0c)spi_set_bidirectional_transmit_only_mode__ACCUM_FBIT__ 15RCC_APBRSTR1_TIM2RST (1 << 0)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)PWR_CR2_PVDRT_2V2 0x01__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xSPI_I2SCFGR_PCMSYNC (1 << 7)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32PWR_SCR_CWUF4 (1 << 3)RCC_APBENR2_OFFSET 0x40__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 1PWR_CR2_PVDFT_2V4 0x02RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_CFGR_PPRE_MASK 0x7__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHBENR_DMAEN (1 << 0)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)RCC_APBENR1_LPUART1EN (1 << 20)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)PWR_CR4_WP1 (1 << 0)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)RCC_APBENR1_I2C1EN (1 << 21)__ELF__ 1UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CCIPR_LPTIM2SEL_MASK 0x3USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_CFGR_SW_HSISYS 0x0RCC_APBRSTR1_TIM7RST (1 << 5)PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)SPI_CR1_MSBFIRST (0 << 7)RCC_CCIPR_RNGDIV_1 0__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RST_CRCRCC_AHBRSTR_OFFSET 0x28SPI_I2SCFGR_DATLEN_32BIT 0x2spi_disable_software_slave_managementRCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)__LONG_LONG_MAX__ 0x7fffffffffffffffLLSPI_CR2_RXNEIE (1 << 6)__INT_FAST8_MAX__ 0x7fffffffBIT27 (1<<27)RCC_APBENR1_SPI2EN (1 << 14)TIM7_BASE (PERIPH_BASE_APB + 0x1400)RCC_CCIPR_LPUART1SEL_HSI16 2DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)RCC_CCIPR_USART2SEL_SHIFT 2SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)SPI_CR2_DS_8BIT (0x7 << 8)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_APBENR1_UCPD1EN (1 << 25)__FLT_DECIMAL_DIG__ 9PWR_CR2_PVDRT_3V0 0x06LIBOPENCM3_MEMORYMAP_COMMON_H spi_disable_rx_dmaRCC_CFGR_MCO_SYSCLK 0x1signed charSPI_SR_BSY (1 << 7)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)PTRDIFF_MIN__UINT_LEAST16_MAX__ 0xffffRCC_CFGR_MCO_SHIFT 24PPBI_BASE (0xE0000000U)RCC_BDCR_RTCEN (1 << 15)RCC_CCIPR_CECSEL_MASK 0x1RCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_PPRE_DIV8 0x6__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRST_DMASPI_CR1_LSBFIRST (1 << 7)RCC_APBENR1_TIM2EN (1 << 0)RCC_CCIPR_RNGDIV_2 1__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38spi_set_full_duplex_modeSPI_CR2_DS_13BIT (0xC << 8)__FRACT_MAX__ 0X7FFFP-15RRCC_AHBSMENR_CRCSMEN (1 << 12)INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)UINTMAX_CSPI1_DR SPI_DR(SPI1_BASE)RCC_APBRSTR1_DAC1RST (1 << 29)__INT_FAST32_MAX__ 0x7fffffffLIBOPENCM3_SPI_H PWR_CR1_LPMS_MASK 0x07__ARM_ARCH_EXT_IDIV__SPI_SR_TXE (1 << 1)ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))PWR_CR3_EWUP4 (1 << 3)SPI_I2SCFGR_DATLEN_24BIT 0x1RCC_APBENR1_LPTIM2EN (1 << 30)__UACCUM_MIN__ 0.0UK__UINT16_MAX__ 0xffffRCC_APBSMENR2_USART1SMEN (1 << 14)__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)__SHRT_MAX__ 0x7fffTIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32spi_peripheralINT_FAST16_MINRCC_CCIPR_RNGDIV_8 3RCC_CR_HSIKERON (1 << 9)SPI_SR_UDR (1 << 3)RCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32RCC_APBRSTR2_OFFSET 0x30PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xfCEC_BASE (PERIPH_BASE_APB + 0x7800)PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)PWR_CR2_PVDRT_2V6 0x03UINT_LEAST8_MAXRST_DMA1UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RCC_AHBENR_AESEN (1 << 16)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_APBRSTR1_LPTIM2RST (1 << 30)RCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)__USA_IBIT__ 16RCC_CFGR_SW_LSE 0x4PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)SPI_CR1_BIDIOE (1 << 14)RCC_CFGR_SWS_PLLRCLK 0x2RCC_APBENR1_UCPD2EN (1 << 26)__FLT_MIN__ 1.1754943508222875e-38FRCC_CR_HSIDIV_DIV1 0__HA_FBIT__ 7RCC_APBRSTR2_TIM1RST (1 << 11)__FDPIC__RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODRST_GPIOERST_GPIOFRCC_CSR_LPWRRSTF (1 << 31)RCC_IOPENR_OFFSET 0x34SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c)SPI_I2SCFGR_I2SE (1 << 10)INT_FAST64_MINRCC_CCIPR_TIM15SEL_TIMPCLK 0__USFRACT_IBIT__ 0RCC_CFGR_SWS_SHIFT 3PWR_CR2_PVDRT_MASK 0x07__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7__USFRACT_MIN__ 0.0UHRSPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)RCC_PLLCFGR_PLLP_SHIFT 17__ARM_NEONSPI_CR1_CRCL (1 << 11)PWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xffSPI_I2SCFGR_DATLEN_16BIT 0x0__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H SPI_CR2_DS_MASK (0xF << 8)LIBOPENCM3_SPI_COMMON_ALL_H SPI_CR2_FRF_TI_MODE (1 << 4)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)RCC_CCIPR_USART2SEL_LSE 3RCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_CCIPR_USART1SEL_MASK 0x3SPI_CR2_SSOE (1 << 2)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3RCC_ICSCR_HSICAL_SHIFT 0__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_CSR MMIO32(RCC_BASE + 0x60)_REG_BIT(offset,bit) (((offset) << 5) + (bit))SPI_CR2_DS_10BIT (0x9 << 8)RST_RNGCOMP_BASE (PERIPH_BASE_APB + 0x10200)__LDBL_MAX_10_EXP__ 308INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_APBENR1_PWREN (1 << 28)PWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29__UINT32_C(c) c ## ULRCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)RCC_APBENR2_SPI1EN (1 << 12)spi_set_receive_only_modespi_set_next_tx_from_crc__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR2_PVDRT_2V5 0x02RCC_PLLCFGR_PLLSRC_SHIFT 0RCC_CCIPR_I2S1SEL_SYSCLK 0RST_ADCRCC_APBENR2_ADCEN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)SPI_CR1_BIDIMODE (1 << 15)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0RCC_PLLCFGR_PLLPEN (1 << 16)__ATOMIC_ACQ_REL 4spi_enable_software_slave_management__USACCUM_FBIT__ 8RCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2RCC_CSR_RMVF (1 << 23)RCC_APBRSTR1_OFFSET 0x2c__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)SPI_CR1_BR_FPCLK_DIV_256 0x7__FLT32_HAS_QUIET_NAN__ 1RCC_APBRSTR1_UCPD2RST (1 << 26)RCC_CCIPR_USART2SEL_PCLK 0RCC_CSR_OBLRSTF (1 << 25)SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308RCC_APBENR2_TIM1EN (1 << 11)spi_set_nss_high__ARM_PCS 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_CCIPR_ADCSEL_SYSCLK 0SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)spi_set_baudrate_prescaler__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)INT16_MAX __INT16_MAX__spi_disable_error_interruptRCC_APBSMENR2_TIM16SMEN (1 << 17)SPI2_CR2 SPI_CR2(SPI2_BASE)__FLT32X_IS_IEC_60559__ 2PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)RST_AESRCC_CFGR_PPRE_SHIFT 12LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXspi_clean_disable__INT_LEAST16_WIDTH__ 16RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)__DEC_EVAL_METHOD__ 2RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04RCC_BDCR_LSERDY (1 << 1)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APBSMENR1_USART3SMEN (1 << 18)RCC_APBENR2_TIM17EN (1 << 18)spi_set_unidirectional_mode__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APBENR1_USART4EN (1 << 19)PWR_CR2_PVDFT_2V9 0x06PWR_CR1_VOS_MASK 0x3SPI_CR2_LDMA_RX (1 << 13)PWR_CR3_APC (1 << 10)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULRCC_CCIPR_LPUART1SEL_LSE 3RCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_RNGDIV_SHIFT 28__INT_LEAST8_MAX__ 0x7fRCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)SPI_CR2_DS_6BIT (0x5 << 8)PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RST_TIM14RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_CCIPR_ADCSEL_PLLPCLK 1spi_set_standard_modeRCC_PLLCFGR_PLLQ_MASK 0x7__UINT_LEAST32_MAX__ 0xffffffffULRCC_APBRSTR2_TIM14RST (1 << 15)RCC_APBSMENR2_TIM14SMEN (1 << 15)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fRST_I2C2BIT14 (1<<14)RCC_ICSCR_HSITRIM_SHIFT 8__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcPWR_SR2_FLASHRDY (1 << 8)__SOFTFP__ 1PWR_CR2_PVDFT_2V2 0x01UINT_LEAST16_MAX __UINT_LEAST16_MAX__SPI_CR2_FRF (1 << 4)INT_FAST32_MINSPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_ICSCR_HSITRIM_MASK 0x1f__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)UINT_FAST16_MAXspi_disable_tx_buffer_empty_interruptRCC_APBRSTR1_LPUART1RST (1 << 20)__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RSPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffLPWR_CR4_WP6 (1 << 5)SPI_CR2_RXDMAEN (1 << 0)RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICSPI_CR1_BR_FPCLK_DIV_4 0x1RCC_PLLCFGR_PLLREN (1<<28)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT_LEAST64_TYPE__ long long unsigned intRCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_CCIPR_LPTIM2SEL_LSI 1__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_I2S1SEL_PLLPLCK 1UINTPTR_MAXPWR_CR1_LPMS_STOP_0 0SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLRCC_APBRSTR1_I2C1RST (1 << 21)SPI_CR2_DS_11BIT (0xA << 8)__ULLFRACT_IBIT__ 0RCC_APBENR1_OFFSET 0x3cMMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)RCC_APBENR1_DBGEN (1 << 27)RCC_APBSMENR1_TIM3SMEN (1 << 1)SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)RCC_CIFR_HSIRDYF (1 << 3)__GNUC__ 12RST_LPTIM1RST_LPTIM2SPI1_DR8 SPI_DR8(SPI1_BASE)WCHAR_MAXSPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)RCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1spi_enable_tx_dma__ULACCUM_MIN__ 0.0ULKRCC_APBENR2_SYSCFGEN (1 << 0)__ARM_ARCH 6RCC_CFGR_SW_MASK 0x3RCC_CCIPR_CECSEL_SHIFT 6SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXCRC_BASE (PERIPH_BASE_AHB + 0x03000)__LDBL_HAS_QUIET_NAN__ 1SPI2_DR8 SPI_DR8(SPI2_BASE)RCC_APBSMENR2_OFFSET 0x50__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_CFGR_MCOPRE_DIV64 6TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28RCC_APBRSTR2_USART1RST (1 << 14)PWR_SR1_WUFI (1 << 15)__UINT_FAST64_MAX__ 0xffffffffffffffffULLINFO_BASE (0x1fff7500U)__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT16_MAXRCC_AHBRSTR_FLASHRST (1 << 8)SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20)__FLT64_MIN__ 2.2250738585072014e-308F64GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsPWR_CR2_PVDFT_MASK 0x07PWR_CR1_LPMS_STANDBY 3RCC_CCIPR_LPTIM2SEL_PCLK 0RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SPI_CR1_SPE (1 << 6)ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))SPI_CR1_SSM (1 << 9)LIBOPENCM3_PWR_H RCC_CSR_PINRSTF (1 << 26)RCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_CCIPR MMIO32(RCC_BASE + 0x54)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)__UFRACT_MAX__ 0XFFFFP-16URRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)RCC_CCIPR_CECSEL_HSI16 0INT64_MAXPWR_CR2_PVDRT_2V1 0x00PWR_CR3_EWUP2 (1 << 1)__UHA_FBIT__ 8spi_enable_ss_output__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_LPUART1SEL_PCLK 0RCC_APBENR1_USART3EN (1 << 18)RCC_CFGR_SWS_HSE 0x1__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RST_TIM15RST_TIM16RST_TIM17SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CCIPR_I2S1SEL_MASK 0x3SPI_CR1_CRCL_16BIT (1 << 11)RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHBRSTR_DMARST (1 << 0)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_APBSMENR2_SYSCFGSMEN (1 << 0)RCC_AHBSMENR_OFFSET 0x48SPI2_BASE (PERIPH_BASE_APB + 0x3800)spi_set_bidirectional_receive_only_modeRCC_APBENR1_DAC1EN (1 << 29)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)spi_set_next_tx_from_bufferRCC_APBSMENR1_DBGSMEN (1 << 27)__ATOMIC_SEQ_CST 5SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)__GCC_ASM_FLAG_OUTPUTS__SPI_CR1_MSTR (1 << 2)RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)RCC_CCIPR_RNGDIV_4 2ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6_STDBOOL_H PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)SPI2_CR1 SPI_CR1(SPI2_BASE)PWR_SCR_CWUF1 (1 << 0)__FLT_EVAL_METHOD__ 0RCC_APBSMENR1_LPTIM2SMEN (1 << 30)unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CR_PLLON (1 << 24)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXRCC_CCIPR_RNGSEL_MASK 0x3__UQQ_FBIT__ 8PWR_CR4_WP5 (1 << 4)INT16_CRST_UCPD1__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4spi_enable_crc__STDC__ 1RCC_CCIPR_USART2SEL_HSI16 2RCC_APBSMENR1_TIM7SMEN (1 << 5)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charPWR_CR2_PVDFT_2V5 0x03SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0SPI_CR1_CRCEN (1 << 13)__SIG_ATOMIC_TYPE__ intRCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"RCC_CFGR_MCOPRE_DIV32 5INT8_MIN__ORDER_PDP_ENDIAN__ 3412RCC_CCIPR_LPUART1SEL_MASK 0x3SPI2_I2SPR SPI_I2SPR(SPI2_BASE)RCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1spi_send__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)RCC_APBRSTR1_DBGRST (1 << 27)__FLT32X_MIN_EXP__ (-1021)RCC_AHBSMENR_SRAMSMEN (1 << 9)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1SPI_CR1(spi_base) MMIO32((spi_base) + 0x00)RCC_CR_CSSON (1 << 19)RCC_PLLCFGR_PLLR_MASK 0x7__LFRACT_EPSILON__ 0x1P-31LRRCC_CIFR_HSERDYF (1 << 4)RCC_CCIPR_USART2SEL_SYSCLK 1RCC_CCIPR_I2S1SEL_SHIFT 14SPI_SR_OVR (1 << 6)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_APBRSTR1_TIM3RST (1 << 1)__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CR_HSIDIV_DIV16 4__FLT32_MIN_10_EXP__ (-37)SPI2 SPI2_BASEMMIO64(addr) (*(volatile uint64_t *)(addr))RCC_APBENR1_TIM7EN (1 << 5)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)INTPTR_MINSPI_I2SCFGR_I2SSTD_LSB 4DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)/build/libopencm3/lib/stm32/g0__TA_IBIT__ 64SPI_CR2_TXDMAEN (1 << 1)USART3_BASE (PERIPH_BASE_APB + 0x4800)SPI_CR2_DS_16BIT (0xF << 8)SPI_CR2_DS_7BIT (0x6 << 8)__SACCUM_IBIT__ 8__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1__LDBL_HAS_DENORM__ 1WCHAR_MIN __WCHAR_MIN__RCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3__USQ_IBIT__ 0BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)RCC_CR_HSIDIV_DIV128 7_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)spi_disable_crcLPTIM2_BASE (PERIPH_BASE_APB + 0x9400)RCC_APBSMENR2_TIM17SMEN (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1SPI2_CRCPR SPI_CRCPR(SPI2_BASE)PWR_CR1_LPMS_SHUTDOWN 4__FLT32_DIG__ 6SPI_CR1_CPHA (1 << 0)INT_LEAST16_MAXSPI1_SR SPI_SR(SPI1_BASE)TIM6_BASE (PERIPH_BASE_APB + 0x1000)RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7RCC_APBSMENR1_TIM2SMEN (1 << 0)INT32_MAXRCC_BDCR_BDRST (1 << 16)__UINT64_C(c) c ## ULLRCC_CFGR_HPRE_MASK 0xfRCC_CCIPR_I2C1SEL_HSI16 2RCC_CIER MMIO32(RCC_BASE + 0x18)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9PWR_SCR_CWUF5 (1 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__FRACT_IBIT__ 0PWR_CR3_ULPEN (1 << 9)RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SPI_CR1_BR_FPCLK_DIV_2 0x0__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)../common/spi_common_all.c__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)INT_LEAST64_MAXuint16_treg32__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intSPI3_I2SPR SPI_I2SPR(SPI3_BASE)SPI1 SPI1_BASEINT64_CRST_SPI1RST_SPI2__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15RCC_APBSMENR1_SPI2SMEN (1 << 14)SPI_I2SCFGR_CHLEN (1 << 0)SPI3_DR8 SPI_DR8(SPI3_BASE)SPI3_CRCPR SPI_CRCPR(SPI3_BASE)__UTQ_FBIT__ 128PWR_CR2_PVDRT_2V9 0x05spi_send_lsb_firstSPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffSPI6 SPI6_BASEPTRDIFF_MAX __PTRDIFF_MAX__PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)SPI_CR2_DS_5BIT (0x4 << 8)RCC_CR_PLLRDY (1 << 25)RCC_CCIPR_USART1SEL_SYSCLK 1__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CR_HSIDIV_DIV2 1RCC_CCIPR_RNGSEL_PLLQCLK 3UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intSPI_CR2_FRXTH (1 << 12)RCC_CCIPR_LPTIM2SEL_LSE 3RCC_BDCR_LSEDRV_HIGH 3GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)SPI_SR_MODF (1 << 5)WCHAR_MINPWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3RCC_CFGR_SWS_LSE 0x4BEGIN_DECLS PWR_CR2_PVDRT_PVD_IN 0x07RST_TIM2RCC_CFGR_MCO_LSI 0x6RCC_CFGR_SW_LSI 0x3RST_LPUART1SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)spi_set_slave_mode__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xspi_set_nss_lowSPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)__FLT32_MIN__ 1.1754943508222875e-38F32INT16_MINspi_disable_tx_dma__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)RST_CEC__QQ_IBIT__ 0SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)PWR_CR2_PVDFT_2V8 0x05RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__GNUC_MINOR__ 2SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)RCC_CCIPR_I2S1SEL_I2S_CKIN 2SPI_CR1_CRCNEXT (1 << 12)RCC_CCIPR_LPTIM1SEL_PCLK 0__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHKspi_enable_error_interrupt__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSPI2_SR SPI_SR(SPI2_BASE)RCC_CIER_PLLRDYIE (1 << 5)RCC_CCIPR_TIM1SEL_PLLQCLK 1RCC_BDCR_RTCSEL_NONE 0INT64_MINSPI_CR2_ERRIE (1 << 5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intINT_FAST64_MIN (-INT_FAST64_MAX - 1)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APBSMENR1_LPUART1SMEN (1 << 20)RCC_CCIPR_LPTIM1SEL_SHIFT 18__SIZEOF_SIZE_T__ 4PWR_CR1_VOS_RANGE_1 1__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)__LDBL_MIN_10_EXP__ (-307)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)__LDBL_MIN__ 2.2250738585072014e-308LTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16SPI3_DR SPI_DR(SPI3_BASE)CORESIGHT_LAR_OFFSET 0xfb0RCC_CCIPR_TIM15SEL_SHIFT 24RCC_BDCR_LSEON (1 << 0)SPI_CR1_BR_FPCLK_DIV_16 0x3short intRCC_APBRSTR1_TIM6RST (1 << 4)__FLT32_IS_IEC_60559__ 2__UINT16_C(c) cSPI_SR_RXNE (1 << 0)__UDA_IBIT__ 32modeUINT_LEAST32_MAXRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)__ATOMIC_RELAXED 0RCC_PLLCFGR_PLLQ_SHIFT 25__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)SPI1_CR2 SPI_CR2(SPI1_BASE)BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14)SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__DBL_DECIMAL_DIG__ 17SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)BIT8 (1<<8)RST_TIM7RCC_APBSMENR2_SPI1SMEN (1 << 12)SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)INT16_C(c) __INT16_C(c)spi_set_clock_polarity_0spi_set_clock_polarity_1RCC_APBSMENR1_UCPD2SMEN (1 << 26)__INT16_MAX__ 0x7fffRCC_CFGR_MCOPRE_DIV16 4SPI_CR1_BR_FPCLK_DIV_64 0x5__INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0spi_resetPWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)PWR_CR1_VOS_SHIFT 9__QQ_FBIT__ 7RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32RCC_CCIPR_I2C1SEL_MASK 0x3baudrate__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32SPI_SR_FRE (1 << 8)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRRST_DBGSPI_CR2(spi_base) MMIO32((spi_base) + 0x04)PWR_CR2_PVDFT_2V0 0x00__SIZEOF_WINT_T__ 4RCC_APBRSTR2_SPI1RST (1 << 12)SPI_CR1_SSI (1 << 8)__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INTPTR_WIDTH__ 32__FLT32_HAS_DENORM__ 1SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1RCC_APBSMENR1_USART4SMEN (1 << 19)__FLT32X_HAS_DENORM__ 1PWR_CR2_PVDRT_2V7 0x04__ULLACCUM_MIN__ 0.0ULLKSPI5 SPI5_BASE__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)RCC_APBENR1_TIM6EN (1 << 4)RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)SPI_I2SCFGR_I2SSTD_PCM 0x3SPI_I2SCFGR_I2SMOD (1 << 11)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_CCIPR_I2C1SEL_PCLK 0RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1__DBL_HAS_QUIET_NAN__ 1RST_I2C1spi_enable_tx_buffer_empty_interruptSPI_CR1_CPOL (1 << 1)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__ULLFRACT_MIN__ 0.0ULLRRST_UCPD2__ARM_FP16_ARGSRCC_AHBRSTR_AESRST (1 << 16)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tBIT12 (1<<12)SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)spi_disable_rx_buffer_not_empty_interruptRCC_CFGR_HPRE_DIV2 0x8RCC_CIFR_PLLRDYF (1 << 5)RST_DAC1spi_readSPI1_CR1 SPI_CR1(SPI1_BASE)SPI3_SR SPI_SR(SPI3_BASE)__UINT_FAST16_TYPE__ unsigned intRCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)SPI1_I2SPR SPI_I2SPR(SPI1_BASE)__WINT_MIN__ 0UINT_LEAST16_MINRCC_CCIPR_CECSEL_LSE 1SPI_I2SCFGR_CKPOL (1 << 3)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APBENR2_TIM16EN (1 << 17)__INT_LEAST16_TYPE__ short int__FLT_HAS_DENORM__ 1SPI1_CRCPR SPI_CRCPR(SPI1_BASE)RCC_CFGR_SWS_HSISYS 0x0__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RST_TIM1__thumb__ 1RST_TIM3RCC_CCIPR_RNGSEL_NONE 0RST_TIM6INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RST_FLASHspi_send_msb_firstPWR_SR1_SBF (1 << 8)__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_SHIFT 30BIT26 (1<<26)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)PWR_CR1_VOS_RANGE_2 2__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)__LONG_MAX__ 0x7fffffffL__STRICT_ANSI__ 1SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)spi_set_master_modeRCC_APBENR1_WWDGEN (1 << 11)RCC_AHBRSTR_RNGRST (1 << 18)RCC_CCIPR_ADCSEL_HSI16 2RCC_AHBENR_OFFSET 0x38__PTRDIFF_TYPE__ intINT_LEAST64_MINPTRDIFF_MAXRCC_APBENR2_TIM15EN (1 << 16)RNG_BASE (PERIPH_BASE_AHB + 0x05000)PWR_CR1_DBP (1 << 8)RCC_PLLCFGR_PLLN_SHIFT 0x8__ARM_ARCH_6M__ 1SPI3 SPI3_BASERCC_CCIPR_LPTIM1SEL_LSI 1__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__PWR_CR1_LPMS_SHIFT 0WINT_MAX__INT16_C(c) cspi_enablePWR_SR1_WUF4 (1 << 3)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__PTRDIFF_WIDTH__ 32spi_disable_ss_outputSPI_SR_CHSIDE (1 << 2)RCC_APBRSTR1_USART3RST (1 << 18)RST_USART1RST_USART2RST_USART3RST_USART4SPI_CR2_TXEIE (1 << 7)spi_enable_rx_buffer_not_empty_interrupt__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SPI_CR2_DS_9BIT (0x8 << 8)PWR_CR4_VBRS (1 << 9)dataRCC_CFGR_MCO_HSI16 0x3SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)RCC_CFGR_SW_SHIFT 0RCC_CCIPR_USART1SEL_SHIFT 0SPI3_CR2 SPI_CR2(SPI3_BASE)RST_PWRRCC_CFGR_PPRE_DIV2 0x4RCC_PLLCFGR_PLLSRC_MASK 0x3spi_set_clock_phase_0__FLT32_NORM_MAX__ 3.4028234663852886e+38F32__SACCUM_EPSILON__ 0x1P-7HKSPI_CR1_CRCL_8BIT (0 << 11)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__INT_MAX__ 0x7fffffff__DBL_MANT_DIG__ 53SPI_CR1_BR_FPCLK_DIV_32 0x4__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)RCC_CR_HSION (1 << 8)INT_FAST16_MAXPWR_SR2_REGLPS (1 << 8)SPI_SR(spi_base) MMIO32((spi_base) + 0x08)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_PLLCFGR_PLLQEN (1 << 24)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_CICR_LSERDYC (1 << 1)SPI_CR2_NSSP (1 << 3)RCC_CCIPR_I2S1SEL_HSI16 2UINT32_CRCC_CR_HSIDIV_DIV64 6GCC: (15:12.2.rel1-1) 12.2.1 20221205 | ,B .C              A+aeabi!6S-M M         !!"" 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../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32/commonspi_common_v2.cstdint.hspi.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hspi.hspi_common_all.hspi_common_v2.hrcc.hrcc.hpwr.hpwr.hrcc_common_all.h$  p#z.C " "/"      0!     0  ! !/! = "!3; "! = !/RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_CICR_PLLRDYC (1 << 5)MMIO64(addr) (*(volatile uint64_t *)(addr))RCC_AHBSMENR_DMASMEN (1 << 0)SCB_BASE (SCS_BASE + 0x0D00)RCC_CCIPR_LPTIM1SEL_MASK 0x3__UHA_FBIT__ 8SPI_I2SCFGR_DATLEN_LSB 1RCC_CCIPR_USART1SEL_PCLK 0PWR_SR1_WUF1 (1 << 0)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)RCC_APBSMENR2_TIM14SMEN (1 << 15)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1RCC_CSR_LSION (1 << 0)STM32G0 1PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)RCC_CCIPR_RNGSEL_SYSCLK 2SPI_CR2_DS_14BIT (0xD << 8)__FLT64_HAS_INFINITY__ 1spi_init_master__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffPWR_SR2_REGLPF (1 << 9)RCC_AHBSMENR_RNGSMEN (1 << 18)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0PWR_CR4_WP2 (1 << 1)__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUSPI2_DR SPI_DR(SPI2_BASE)RCC_AHBRSTR_DMARST (1 << 0)__ARM_FEATURE_QBITLIBOPENCM3_RCC_COMMON_ALL_H SPI_CR2_DS_12BIT (0xB << 8)RCC_APBRSTR2_TIM15RST (1 << 16)RCC_BDCR MMIO32(RCC_BASE + 0x5c)RCC_CFGR_SW_LSI 0x3INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8SPI_CR1_MSTR (1 << 2)__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intSPI_CR1_BR_FPCLK_DIV_8 0x2PWR_CR3_EIWUL (1 << 15)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9RCC_AHBRSTR_CRCRST (1 << 12)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53SPI_SR_CRCERR (1 << 4)INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64SPI_CR1_RXONLY (1 << 10)RCC_PLLCFGR_PLLP_MASK 0x1fUINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3RCC_CIER_LSIRDYIE (1 << 0)RCC_CR_HSIRDY (1 << 10)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0SPI_I2SPR_ODD (1 << 8)INT_FAST64_MAX __INT_FAST64_MAX__RCC_PLLCFGR_PLLM_SHIFT 0x4__UINT_LEAST16_MAX__ 0xffffSPI1_DR SPI_DR(SPI1_BASE)__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intRCC_CICR_LSECSSC (1 << 9)RCC_CCIPR_RNGSEL_HSI16 1RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intRCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR1_OFFSET 0x4cINT32_MIN (-INT32_MAX - 1)RCC_CCIPR_CECSEL_HSI16 0__FLT32_MAX_10_EXP__ 38RCC_AHBENR_CRCEN (1 << 12)RCC_CFGR_HPRE_DIV8 0xaRCC_CFGR_SW_PLLRCLK 0x2RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZSPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)__UINTPTR_MAX__ 0xffffffffURCC_APBSMENR1_DAC1SMEN (1 << 29)__FLT32_MIN_EXP__ (-125)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))RCC_CFGR_MCOPRE_DIV1 0PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)SPI_I2SCFGR_I2SCFG_LSB 8SPI_CR1_BR_FPCLK_DIV_128 0x6UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_APBRSTR1_SPI2RST (1 << 14)SPI_CR2_DS_15BIT (0xE << 8)cpha__SFRACT_EPSILON__ 0x1P-7HRSPI_CR2_DS_4BIT (0x3 << 8)RCC_CFGR_HPRE_SHIFT 8RCC_IOPSMENR_OFFSET 0x44__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RCC_CCIPR_TIM15SEL_PLLQCLK 1RCC_APBSMENR1_USART2SMEN (1 << 17)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)SPI_I2SPR_MCKOE (1 << 9)SPI3_CR1 SPI_CR1(SPI3_BASE)spi_fifo_reception_threshold_16bitRCC_AHBSMENR_FLASHSMEN (1 << 8)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)PWR_SR2_VOSF (1 << 10)UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)__LACCUM_IBIT__ 32PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_SCR_CWUF2 (1 << 1)RCC_CCIPR_LPTIM2SEL_HSI16 2__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_C__VERSION__ "12.2.1 20221205"RCC_CFGR_MCO_PLLRCLK 0x5__VFP_FP__ 1SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffPWR_SR2_PVDO (1 << 11)RCC_APBSMENR1_WWDGSMEN (1 << 11)__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11INT64_C(c) __INT64_C(c)SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2RCC_APBRSTR2_ADCRST (1 << 20)SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URRCC_APBSMENR1_RTCAPBSMEN (1 << 10)SPI4 SPI4_BASERCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)__UINT_LEAST8_TYPE__ unsigned charSPI_DR(spi_base) MMIO32((spi_base) + 0x0c)RCC_APBRSTR2_TIM17RST (1 << 18)__ACCUM_FBIT__ 15RCC_APBRSTR1_TIM2RST (1 << 0)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)PWR_CR2_PVDRT_2V2 0x01__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xSPI_I2SCFGR_PCMSYNC (1 << 7)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32PWR_SCR_CWUF4 (1 << 3)RCC_APBENR2_OFFSET 0x40__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charspi_read8PWR_CR2_PVDFT_2V4 0x02RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_CFGR_PPRE_MASK 0x7__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHBENR_DMAEN (1 << 0)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_PLLCFGR_PLLREN (1<<28)GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)RCC_APBENR1_LPUART1EN (1 << 20)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)PWR_CR4_WP1 (1 << 0)BIT7 (1<<7)BIT17 (1<<17)SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)RCC_APBENR1_I2C1EN (1 << 21)RCC_CCIPR_I2S1SEL_HSI16 2UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CCIPR_LPTIM2SEL_MASK 0x3USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__RCC_CFGR_SW_HSISYS 0x0RCC_APBRSTR1_TIM7RST (1 << 5)PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)SPI_CR1_MSBFIRST (0 << 7)RCC_CCIPR_RNGDIV_1 0__SIZEOF_DOUBLE__ 8__ARM_FEATURE_CMSE__FLT32X_MIN_EXP__ (-1021)RCC_AHBRSTR_OFFSET 0x28SPI_I2SCFGR_DATLEN_32BIT 0x2RCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)SPI_CR2_RXNEIE (1 << 6)BIT27 (1<<27)RCC_APBENR1_SPI2EN (1 << 14)TIM7_BASE (PERIPH_BASE_APB + 0x1400)RCC_CCIPR_LPUART1SEL_HSI16 2RCC_CCIPR_USART2SEL_SHIFT 2SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)SPI_CR2_DS_8BIT (0x7 << 8)__UTA_FBIT__ 64RCC_APBENR1_UCPD1EN (1 << 25)SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10)__thumb__ 1RCC_CFGR_MCO_SYSCLK 0x1LIBOPENCM3_MEMORYMAP_COMMON_H signed charSPI_SR_BSY (1 << 7)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77RCC_CCIPR_CECSEL_MASK 0x1RCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_PPRE_DIV8 0x6__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSPI_CR1_LSBFIRST (1 << 7)RCC_APBENR1_TIM2EN (1 << 0)RCC_CCIPR_RNGDIV_2 1__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RCC_APBSMENR2_TIM15SMEN (1 << 16)SPI_CR2_DS_13BIT (0xC << 8)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)RCC_APBENR1_WWDGEN (1 << 11)RCC_APBRSTR1_DAC1RST (1 << 29)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5PWR_CR1_LPMS_MASK 0x07__ARM_ARCH_EXT_IDIV__SPI_SR_TXE (1 << 1)__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))PWR_CR3_EWUP4 (1 << 3)SPI_I2SCFGR_DATLEN_24BIT 0x1RCC_APBENR1_LPTIM2EN (1 << 30)RCC_CFGR_HPRE_MASK 0xf__UINT16_MAX__ 0xffffRCC_APBSMENR2_USART1SMEN (1 << 14)__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32RCC_CCIPR_USART1SEL_SYSCLK 1uint16_tRCC_CCIPR_RNGDIV_8 3SPI_SR_UDR (1 << 3)RCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32RCC_APBRSTR2_OFFSET 0x30PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xfCEC_BASE (PERIPH_BASE_APB + 0x7800)PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)PWR_CR2_PVDRT_2V6 0x03UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RCC_AHBENR_AESEN (1 << 16)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_APBRSTR1_LPTIM2RST (1 << 30)SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)__USA_IBIT__ 16RCC_CFGR_SW_LSE 0x4PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)__SFRACT_MAX__ 0X7FP-7HR__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)SPI_CR1_BIDIOE (1 << 14)RCC_CFGR_SWS_PLLRCLK 0x2RCC_APBENR1_UCPD2EN (1 << 26)__FLT_MIN__ 1.1754943508222875e-38FRCC_CR_HSIDIV_DIV1 0__HA_FBIT__ 7RCC_APBRSTR2_TIM1RST (1 << 11)__FDPIC__LIBOPENCM3_RCC_H SPI_CR2_LDMA_TX (1 << 14)PWR_CR1_VOS_RANGE_1 1__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2RCC_CSR_LPWRRSTF (1 << 31)RCC_APBSMENR1_PWRSMEN (1 << 28)RCC_IOPENR_OFFSET 0x34SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c)SPI_I2SCFGR_I2SE (1 << 10)INT_FAST64_MINRCC_CCIPR_TIM15SEL_TIMPCLK 0__USFRACT_IBIT__ 0../common/spi_common_v2.cPWR_CR2_PVDRT_MASK 0x07__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7__USFRACT_MIN__ 0.0UHRSPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONSPI_CR1_CRCL (1 << 11)PWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xffSPI_I2SCFGR_DATLEN_16BIT 0x0__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H SPI_CR2_DS_MASK (0xF << 8)SPI_CR2_FRF_TI_MODE (1 << 4)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)RCC_CCIPR_USART2SEL_LSE 3RCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_CCIPR_USART1SEL_MASK 0x3SPI_CR2_SSOE (1 << 2)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3RCC_ICSCR_HSICAL_SHIFT 0__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_CSR MMIO32(RCC_BASE + 0x60)_REG_BIT(offset,bit) (((offset) << 5) + (bit))__ULLACCUM_EPSILON__ 0x1P-32ULLKCOMP_BASE (PERIPH_BASE_APB + 0x10200)__INT_LEAST32_WIDTH__ 32INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_APBENR1_PWREN (1 << 28)PWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29USART3_BASE (PERIPH_BASE_APB + 0x4800)RCC_APBENR2_SPI1EN (1 << 12)__UACCUM_MIN__ 0.0UKRCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR2_PVDRT_2V5 0x02spi_set_data_sizeRCC_CCIPR_I2S1SEL_SYSCLK 0PWR_CR2_PVDFT_MASK 0x07RCC_APBENR2_ADCEN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)SPI_CR1_BIDIMODE (1 << 15)__ARM_FEATURE_MATMUL_INT8LIBOPENCM3_PWR_H PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0RCC_PLLCFGR_PLLPEN (1 << 16)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8RCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2cpolRCC_APBRSTR1_OFFSET 0x2c__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)SPI_CR1_BR_FPCLK_DIV_256 0x7__FLT32_HAS_QUIET_NAN__ 1RCC_APBRSTR1_UCPD2RST (1 << 26)RCC_CCIPR_USART2SEL_PCLK 0RCC_CSR_OBLRSTF (1 << 25)SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308RCC_APBENR2_TIM1EN (1 << 11)__ARM_PCS 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolSPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)INT16_MAX __INT16_MAX__RCC_APBSMENR2_TIM16SMEN (1 << 17)SPI2_CR2 SPI_CR2(SPI2_BASE)SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)RCC_CIER MMIO32(RCC_BASE + 0x18)RCC_CFGR_PPRE_SHIFT 12LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)__DEC_EVAL_METHOD__ 2RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04RCC_BDCR_LSERDY (1 << 1)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APBSMENR1_USART3SMEN (1 << 18)RCC_APBENR2_TIM17EN (1 << 18)RCC_CCIPR_CECSEL_SHIFT 6__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APBENR1_USART4EN (1 << 19)PWR_CR2_PVDFT_2V9 0x06PWR_CR1_VOS_MASK 0x3SPI_CR2_LDMA_RX (1 << 13)PWR_CR3_APC (1 << 10)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CFGR_SWS_SHIFT 3__UINT32_MAX__ 0xffffffffULRCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_RNGDIV_SHIFT 28__INT_LEAST8_MAX__ 0x7fRCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)__FLT_DECIMAL_DIG__ 9PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_CCIPR_ADCSEL_PLLPCLK 1RCC_PLLCFGR_PLLQ_MASK 0x7__UINT_LEAST32_MAX__ 0xffffffffULRCC_APBRSTR2_TIM14RST (1 << 15)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)RCC_ICSCR_HSITRIM_SHIFT 8__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcPWR_SR2_FLASHRDY (1 << 8)PERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_CR2_PVDFT_2V2 0x01UINT_LEAST16_MAX __UINT_LEAST16_MAX__SPI_CR2_FRF (1 << 4)INT_FAST32_MINSPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_ICSCR_HSITRIM_MASK 0x1f__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)UINT_FAST16_MAXRCC_APBSMENR2_SYSCFGSMEN (1 << 0)__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RSPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffLPWR_CR4_WP6 (1 << 5)SPI_CR2_RXDMAEN (1 << 0)RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICSPI_CR1_BR_FPCLK_DIV_4 0x1PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_CCIPR_LPTIM2SEL_LSI 1__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)RCC_CFGR_SWS_HSISYS 0x0RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_CECSEL_LSE 1UINTPTR_MAXPWR_CR1_LPMS_STOP_0 0SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLSPI3_DR SPI_DR(SPI3_BASE)RCC_APBRSTR1_I2C1RST (1 << 21)SPI_CR2_DS_11BIT (0xA << 8)__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)RCC_APBENR1_DBGEN (1 << 27)RCC_APBSMENR1_TIM3SMEN (1 << 1)SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)RCC_CIFR_HSIRDYF (1 << 3)__GNUC__ 12RCC_CR_HSIDIV_DIV2 1SPI1_DR8 SPI_DR8(SPI1_BASE)WCHAR_MAXSPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)RCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKRCC_APBENR2_SYSCFGEN (1 << 0)__ARM_ARCH 6RCC_CFGR_SW_MASK 0x3RCC_PLLCFGR_PLLQ_SHIFT 25__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)INT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SPI2_DR8 SPI_DR8(SPI2_BASE)RCC_APBSMENR2_OFFSET 0x50__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_CFGR_MCOPRE_DIV64 6TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28RCC_APBRSTR2_USART1RST (1 << 14)__INT_FAST32_TYPE__ int__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7CRC_BASE (PERIPH_BASE_AHB + 0x03000)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024PWR_SR1_WUFI (1 << 15)UINT16_MAXRCC_AHBRSTR_FLASHRST (1 << 8)SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRCC_APBRSTR1_LPUART1RST (1 << 20)PWR_CR1_LPMS_STANDBY 3RCC_CCIPR_LPTIM2SEL_PCLK 0RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long intLIBOPENCM3_SPI_COMMON_ALL_H __CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SPI_CR1_SPE (1 << 6)ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))SPI_CR1_SSM (1 << 9)GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_CSR_PINRSTF (1 << 26)RCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_CCIPR MMIO32(RCC_BASE + 0x54)RCC_BDCR_RTCEN (1 << 15)__UFRACT_MAX__ 0XFFFFP-16URRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)INT64_MAXPWR_CR2_PVDRT_2V1 0x00PWR_CR3_EWUP2 (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0__ULACCUM_IBIT__ 32RCC_CCIPR_LPUART1SEL_PCLK 0RCC_APBENR1_USART3EN (1 << 18)RCC_CFGR_SWS_HSE 0x1__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32SPI3 SPI3_BASEINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CCIPR_I2S1SEL_MASK 0x3SPI_CR1_CRCL_16BIT (1 << 11)RCC_PLLCFGR_PLLSRC_HSI16 2__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_AHBSMENR_OFFSET 0x48SPI2_BASE (PERIPH_BASE_APB + 0x3800)RCC_APBENR1_DAC1EN (1 << 29)RCC_APBENR2_TIM15EN (1 << 16)SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)PWR_CR2_PVDRT_3V0 0x06RCC_CICR_HSERDYC (1 << 4)RCC_APBSMENR1_DBGSMEN (1 << 27)data_sSPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)__GCC_ASM_FLAG_OUTPUTS__RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)RCC_CCIPR_RNGDIV_4 2ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKPWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)SPI2_CR1 SPI_CR1(SPI2_BASE)PWR_SCR_CWUF1 (1 << 0)__FLT_EVAL_METHOD__ 0RCC_APBSMENR1_LPTIM2SMEN (1 << 30)unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CR_PLLON (1 << 24)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXRCC_CCIPR_RNGSEL_MASK 0x3__UQQ_FBIT__ 8PWR_CR4_WP5 (1 << 4)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_BDCR_RTCSEL_NONE 0__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charPWR_CR2_PVDFT_2V5 0x03SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0SPI_CR1_CRCEN (1 << 13)SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18)RCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"RCC_CFGR_MCOPRE_DIV32 5INT8_MINRCC_CCIPR_LPUART1SEL_MASK 0x3RCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_APBRSTR1_DBGRST (1 << 27)__LDBL_MIN_10_EXP__ (-307)RCC_AHBSMENR_SRAMSMEN (1 << 9)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1SPI_CR1(spi_base) MMIO32((spi_base) + 0x00)RCC_CR_CSSON (1 << 19)RCC_PLLCFGR_PLLR_MASK 0x7__LFRACT_EPSILON__ 0x1P-31LRRCC_CIFR_HSERDYF (1 << 4)RCC_CCIPR_USART2SEL_SYSCLK 1spi_set_crcl_16bitRCC_CCIPR_I2S1SEL_SHIFT 14SPI_SR_OVR (1 << 6)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_APBRSTR1_TIM3RST (1 << 1)__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CR_HSIDIV_DIV16 4__FLT32_MIN_10_EXP__ (-37)SPI2 SPI2_BASEINFO_BASE (0x1fff7500U)RCC_APBENR1_TIM7EN (1 << 5)__ARM_FP16_FORMAT_ALTERNATIVERCC_PLLCFGR_PLLSRC_SHIFT 0__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)INTPTR_MINspi_send8DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64SPI_CR2_TXDMAEN (1 << 1)SPI_CR2_DS_16BIT (0xF << 8)SPI_CR2_DS_7BIT (0x6 << 8)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1RCC_PLLCFGR_PLLP_SHIFT 17__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)RCC_CR_HSIDIV_DIV128 7_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)RCC_APBSMENR2_TIM17SMEN (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1SPI2_CRCPR SPI_CRCPR(SPI2_BASE)PWR_CR1_LPMS_SHUTDOWN 4__FLT32_DIG__ 6SPI_CR1_CPHA (1 << 0)INT_LEAST16_MAXSPI1_SR SPI_SR(SPI1_BASE)TIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7RCC_APBSMENR1_TIM2SMEN (1 << 0)INT32_MAXRCC_BDCR_BDRST (1 << 16)__ACCUM_MIN__ (-0X1P15K-0X1P15K)lsbfirstRCC_CCIPR_I2C1SEL_HSI16 2__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9PWR_SCR_CWUF5 (1 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__UINT_FAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_ULPEN (1 << 9)RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SPI_CR2_DS_10BIT (0x9 << 8)SPI_CR1_BR_FPCLK_DIV_2 0x0__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fffspi_set_crcl_8bit__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)INT_LEAST64_MAX__SACCUM_IBIT__ 8reg32__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intSPI3_I2SPR SPI_I2SPR(SPI3_BASE)SPI1 SPI1_BASEINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_ADCSEL_SYSCLK 0__UINT_LEAST16_TYPE__ short unsigned int__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15RCC_APBSMENR1_SPI2SMEN (1 << 14)SPI_I2SCFGR_CHLEN (1 << 0)SPI3_DR8 SPI_DR8(SPI3_BASE)SPI3_CRCPR SPI_CRCPR(SPI3_BASE)__UTQ_FBIT__ 128PWR_CR2_PVDRT_2V9 0x05SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)__FINITE_MATH_ONLY__ 0RCC_CR_HSEBYP (1 << 18)__INT_FAST16_MAX__ 0x7fffffffRCC_APBSMENR2_SPI1SMEN (1 << 12)PTRDIFF_MAX __PTRDIFF_MAX__PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)SPI_CR2_DS_5BIT (0x4 << 8)RCC_CR_PLLRDY (1 << 25)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CCIPR_RNGSEL_PLLQCLK 3UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intSPI_CR2_FRXTH (1 << 12)RCC_CCIPR_LPTIM2SEL_LSE 3RCC_BDCR_LSEDRV_HIGH 3GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)SPI_SR_MODF (1 << 5)WCHAR_MINPWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3RCC_CFGR_SWS_LSE 0x4BEGIN_DECLS PWR_CR2_PVDRT_PVD_IN 0x07GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)RCC_CFGR_MCO_LSI 0x6__ARM_NEON_FPSPI1_CR2 SPI_CR2(SPI1_BASE)SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15RCC_CSR_RMVF (1 << 23)__FLT32X_MAX__ 1.7976931348623157e+308F32xSPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)__QQ_IBIT__ 0SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)PWR_CR2_PVDFT_2V8 0x05RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)__USQ_IBIT__ 0SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)SPI_CR1_CRCNEXT (1 << 12)RCC_CCIPR_LPTIM1SEL_PCLK 0__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)spi_fifo_reception_threshold_8bit__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSPI2_SR SPI_SR(SPI2_BASE)RCC_CIER_PLLRDYIE (1 << 5)RCC_CCIPR_TIM1SEL_PLLQCLK 1INT64_MINSPI_CR2_ERRIE (1 << 5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRCC_CCIPR_TIM1SEL_MASK 0x1UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APBSMENR1_LPUART1SMEN (1 << 20)RCC_CCIPR_LPTIM1SEL_SHIFT 18__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_APBSMENR1_TIM7SMEN (1 << 5)__FRACT_IBIT__ 0CORESIGHT_LAR_OFFSET 0xfb0RCC_CCIPR_TIM15SEL_SHIFT 24RCC_BDCR_LSEON (1 << 0)SPI_CR1_BR_FPCLK_DIV_16 0x3short intRCC_APBRSTR1_TIM6RST (1 << 4)__UINT16_C(c) cSPI_SR_RXNE (1 << 0)__UDA_IBIT__ 32UINT_LEAST32_MAXRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)__ATOMIC_RELAXED 0__UHQ_FBIT__ 16__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)__GCC_ATOMIC_BOOL_LOCK_FREE 1BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14)SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)SPI_SR_CHSIDE (1 << 2)__DBL_DECIMAL_DIG__ 17LIBOPENCM3_SPI_H BIT8 (1<<8)SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)INT16_C(c) __INT16_C(c)RCC_CCIPR_I2S1SEL_PLLPLCK 1RCC_APBSMENR1_UCPD2SMEN (1 << 26)__INT16_MAX__ 0x7fffRCC_CFGR_MCOPRE_DIV16 4SPI_CR1_BR_FPCLK_DIV_64 0x5__INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)PWR_CR1_VOS_SHIFT 9__QQ_FBIT__ 7RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_CCIPR_I2C1SEL_MASK 0x3PWR_CR1_FPD_STOP (1 << 3)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32SPI_SR_FRE (1 << 8)RCC_CICR_CSSC (1 << 8)__LFRACT_FBIT__ 31__ULLFRACT_EPSILON__ 0x1P-64ULLR__STDC_HOSTED__ 1SPI_CR2(spi_base) MMIO32((spi_base) + 0x04)PWR_CR2_PVDFT_2V0 0x00__SIZEOF_WINT_T__ 4RCC_APBRSTR2_SPI1RST (1 << 12)SPI_CR1_SSI (1 << 8)__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1RCC_APBSMENR1_USART4SMEN (1 << 19)__FLT32X_HAS_DENORM__ 1PWR_CR2_PVDRT_2V7 0x04__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)__LDBL_IS_IEC_60559__ 2RCC_APBENR1_TIM6EN (1 << 4)RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)SPI_I2SCFGR_I2SSTD_PCM 0x3SPI_I2SCFGR_I2SSTD_LSB 4SPI_I2SCFGR_I2SMOD (1 << 11)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_CCIPR_I2C1SEL_PCLK 0RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1RCC_APBENR1_OFFSET 0x3cSPI_CR1_CPOL (1 << 1)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_AHBRSTR_AESRST (1 << 16)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tBIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_HPRE_DIV2 0x8RCC_CIFR_PLLRDYF (1 << 5)RCC_CFGR_SW_SHIFT 0SPI1_CR1 SPI_CR1(SPI1_BASE)SPI3_SR SPI_SR(SPI3_BASE)__UINT_FAST16_TYPE__ unsigned intRCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)PWR_SR1_WUF4 (1 << 3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)SPI1_I2SPR SPI_I2SPR(SPI1_BASE)__WINT_MIN__ 0UINT_LEAST16_MINSPI_I2SCFGR_CKPOL (1 << 3)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APBENR2_TIM16EN (1 << 17)__INT_LEAST16_TYPE__ short intRCC_CFGR_MCOPRE_DIV8 3SPI1_CRCPR SPI_CRCPR(SPI1_BASE)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RCC_CCIPR_TIM15SEL_MASK 0x1UINTMAX_C__LDBL_MAX_10_EXP__ 308RCC_CCIPR_RNGSEL_NONE 0RCC_CCIPR_I2S1SEL_I2S_CKIN 2INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1PWR_SR1_SBF (1 << 8)__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_SHIFT 30BIT26 (1<<26)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)PWR_CR1_VOS_RANGE_2 2__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)INTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)SPI_CR2_DS_6BIT (0x5 << 8)RCC_CCIPR_USART2SEL_HSI16 2RCC_AHBRSTR_RNGRST (1 << 18)RCC_CCIPR_ADCSEL_HSI16 2RCC_AHBENR_OFFSET 0x38INT_LEAST64_MINPTRDIFF_MAXRCC_AHBSMENR_CRCSMEN (1 << 12)RNG_BASE (PERIPH_BASE_AHB + 0x05000)PWR_CR1_DBP (1 << 8)RCC_PLLCFGR_PLLN_SHIFT 0x8__LLFRACT_EPSILON__ 0x1P-63LLRRCC_CR_HSIKERON (1 << 9)RCC_CCIPR_LPTIM1SEL_LSI 1__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__PWR_CR1_LPMS_SHIFT 0WINT_MAX__INT16_C(c) cSPI5 SPI5_BASEINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_APBRSTR1_USART3RST (1 << 18)SPI2_I2SPR SPI_I2SPR(SPI2_BASE)__ATOMIC_ACQ_REL 4SPI_CR2_TXEIE (1 << 7)SPI6 SPI6_BASE__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SPI_CR2_DS_9BIT (0x8 << 8)PWR_CR4_VBRS (1 << 9)dataRCC_CFGR_MCO_HSI16 0x3SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)RCC_CCIPR_USART1SEL_SHIFT 0SPI3_CR2 SPI_CR2(SPI3_BASE)RCC_CFGR_PPRE_DIV2 0x4RCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32I2C1_BASE (PERIPH_BASE_APB + 0x5400)SPI_CR1_CRCL_8BIT (0 << 11)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53SPI_CR1_BR_FPCLK_DIV_32 0x4__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)RCC_CR_HSION (1 << 8)INT_FAST16_MAXPWR_SR2_REGLPS (1 << 8)SPI_SR(spi_base) MMIO32((spi_base) + 0x08)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_PLLCFGR_PLLQEN (1 << 24)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_CICR_LSERDYC (1 << 1)SPI_CR2_NSSP (1 << 3)UINT32_CRCC_CR_HSIDIV_DIV64 6GCC: (15:12.2.rel1-1) 12.2.1 20221205 | $A     A+aeabi!6S-M M      8:"$&(*,.0246<>o7k   ;>   8$H R\n  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" !! 0/! /! /" !/ !! /! /! /! /! /! /! /! /! /! /'!' ./)!) ./! /! /" / /! /! /! /! /! /! /!!!.! #/p   1 #/ v   .!  #!p  1  #! v  .! #/ r   1 #/x   .!  #! r  1  #!x  .!  //  /   /   1  1  1  2  1  /$ =!! /  #   1   #.  1    y.  2  1  3  //  /   3 P.  1  1  1  2  1  /$ =!! /  ! c    1   #.  1    y.  2  1  .! #/ r   1 #/x   .!  #! r  1  #!x  .! .u h #!n  # w. # # # .! .u h /n 1??11 .! .u h /n 1??11 .! .u h #!n  # w. # # #  .!. l h /n 11111 .!.l h /n  # # # # #  .!!r !"!"! ! =  !/ ! =  !/ ! =  !/ ! =  !/ ! =  !/ ! =  !/ !/  !/  ! ! .!h &!/$/ t  &!/1 &!/$/ &!/ .!h &!/$/ t  &!/1 &!/$/ &!/ 0+. 1# %!/ /r +.?# %!/ /n L / /x  / / %!,%   / &!-&   / $!/!/ $!/!//  0" " / !" / !TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1UINT16_C(c) __UINT16_C(c)__UACCUM_FBIT__ 16__APCS_32__ 1timer_ic_set_filter__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__TIM6 TIM6_BASEunsigned intRCC_IOPSMENR_OFFSET 0x44RCC_APBSMENR1_UCPD2SMEN (1 << 26)eventTIM16_TISEL TIM_TISEL(TIM16)__FLT_NORM_MAX__ 3.4028234663852886e+38FPWR_CR1_VOS_MASK 0x3RCC_CIER_LSIRDYIE (1 << 0)TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)UINT_FAST32_MAX__ARM_FEATURE_MATMUL_INT8PWR_SR2_REGLPS (1 << 8)TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)RCC_APBENR2_SPI1EN (1 << 12)__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16TIM13_CCR1 TIM_CCR1(TIM13)INTPTR_MIN (-INTPTR_MAX - 1)RCC_CFGR_SWS_MASK 0x3TIM12_DIER TIM_DIER(TIM12)TIM_IC_OFFTIM_CCMR1_OC2M_ACTIVE (0x1 << 12)TIM_BDTR_OSSR (1 << 11)__INT_FAST16_MAX__ 0x7fffffffRCC_APBENR2_TIM16EN (1 << 17)RCC_CFGR_HPRE_DIV512 0xf__FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_APBRSTR1_I2C1RST (1 << 21)UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffffTIM_SMCR(tim_base) MMIO32((tim_base) + 0x08)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C)RCC_CR_HSIDIV_DIV4 2RCC_CICR MMIO32(RCC_BASE + 0x20)alignment__FLT32_HAS_INFINITY__ 1timer_disable_preload__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffRCC_CFGR_HPRE_DIV2 0x8INT64_MIN (-INT64_MAX - 1)timer_set_alignmentRCC_CICR_CSSC (1 << 8)__FLT64_MIN_10_EXP__ (-307)TIM1_CCER TIM_CCER(TIM1)TIM15_EGR TIM_EGR(TIM15)TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)BIT10 (1<<10)UINT_FAST64_MAXTIM3_CCER TIM_CCER(TIM3)__STDC__ 1_BoolGNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsTIM2_CCR3 TIM_CCR3(TIM2)__ULLFRACT_IBIT__ 0INT_LEAST32_MAXRCC_APBRSTR1_USART2RST (1 << 17)__FLT32_MAX_EXP__ 128__CHAR32_TYPE__ long unsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32RCC_APBSMENR1_USART2SMEN (1 << 17)TIM17_BASE (PERIPH_BASE_APB + 0x14800)TIM_SMCR_ETF_MASK (0xF << 8)__DBL_MAX_10_EXP__ 308INT_LEAST32_MIN__UINT_FAST64_MAX__ 0xffffffffffffffffULLPWR_CR1_LPMS_SHIFT 0TIM_BDTR_DBL_MASK (0x1F << 8)TIM_CCMR1_OC2M_FROZEN (0x0 << 12)__WCHAR_TYPE__ unsigned intRNG_BASE (PERIPH_BASE_AHB + 0x05000)__SA_IBIT__ 16__UDA_IBIT__ 32tim_ic_id__ELF__ 1RCC_CCIPR_CECSEL_LSE 1ADC1_BASE (PERIPH_BASE_APB + 0x12400)__SIZEOF_LONG__ 4TIM16_DCR TIM_DCR(TIM16)TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)TIM1_SR TIM_SR(TIM1)RCC_CFGR_SWS_SHIFT 3BIT11 (1<<11)TIM2_CCMR1 TIM_CCMR1(TIM2)LIBOPENCM3_MEMORYMAP_H TIM6_EGR TIM_EGR(TIM6)RCC_CSR_IWDGRSTF (1 << 29)BIT3 (1<<3)timer_enable_preloadTIM17_CCER TIM_CCER(TIM17)TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)RCC_CCIPR_ADCSEL_SHIFT 30__ARM_FEATURE_DSPRCC_PLLCFGR_PLLQ_MASK 0x7__UINT_LEAST64_TYPE__ long long unsigned intTIM1_CCMR2 TIM_CCMR2(TIM1)RCC_CFGR_HPRE_DIV4 0x9_STDBOOL_H clock_divSIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1TIM10_CNT TIM_CNT(TIM10)RCC_APBRSTR1_UCPD1RST (1 << 25)WINT_MINTIM_SMCR_SMS_RM (0x4 << 0)timer_set_oc_value__DQ_FBIT__ 63__INT64_TYPE__ long long int__INT_FAST16_WIDTH__ 32TIM_SMCR_SMS_TM (0x6 << 0)timer_set_oc_idle_state_set__FLT_HAS_INFINITY__ 1TIM8_CNT TIM_CNT(TIM8)BIT1 (1<<1)TIM8_ARR TIM_ARR(TIM8)__ARM_FEATURE_BF16_VECTOR_ARITHMETICTIM_SMCR_SMS_ECM1 (0x7 << 0)INT_FAST64_MAX __INT_FAST64_MAX__TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34)TIM7_DIER TIM_DIER(TIM7)TIM4_CCMR2 TIM_CCMR2(TIM4)PWR_CR3_EIWUL (1 << 15)TIM_CCMR2_IC4PSC_2 (0x1 << 10)RCC_CFGR_MCO_HSE 0x4TIM13_PSC TIM_PSC(TIM13)TIM4_CCR2 TIM_CCR2(TIM4)TIM12_CCMR1 TIM_CCMR1(TIM12)PWR_CR4_WP6 (1 << 5)TIM_SMCR_ETPS_OFF (0x0 << 12)RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_MCO_LSI 0x6TIM_CR1_CEN (1 << 0)RCC_APBSMENR1_RTCAPBSMEN (1 << 10)RCC_CIFR_LSIRDYF (1 << 0)TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)RCC_APBENR1_UCPD1EN (1 << 25)TIM11_CCER TIM_CCER(TIM11)__INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_CCIPR_LPTIM1SEL_LSE 3RCC_APBSMENR1_LPUART1SMEN (1 << 20)TIM_IC_CK_INT_N_2__INT_LEAST32_TYPE__ long intTIM_IC_CK_INT_N_4__DBL_HAS_INFINITY__ 1__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKTIM_IC_CK_INT_N_8TIM_CCER_CC1NE (1 << 2)BIT13 (1<<13)__FLT_HAS_QUIET_NAN__ 1RCC_CFGR_SWS_LSE 0x4__SHRT_MAX__ 0x7fffTIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)RCC_AHBRSTR_AESRST (1 << 16)BIT4 (1<<4)TIM14_TISEL TIM_TISEL(TIM14)RCC_APBRSTR1_LPUART1RST (1 << 20)RCC_CSR_RMVF (1 << 23)RCC_CCIPR_USART1SEL_PCLK 0TIM_CR1_ARPE (1 << 7)TIM_CCMR1_IC1F_MASK (0xF << 4)PWR_CR4_WP1 (1 << 0)RCC_APBENR2_TIM14EN (1 << 15)TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)RCC_APBRSTR2_TIM17RST (1 << 18)timer_set_clock_divisionRCC_APBRSTR1_LPTIM1RST (1 << 31)PWR_CR1_LPMS_MASK 0x07RTC_BASE (PERIPH_BASE_APB + 0x2800)TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_ATOMIC_CHAR_LOCK_FREE 1__UINT_FAST16_TYPE__ unsigned intRCC_BDCR_LSERDY (1 << 1)MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLTIM_EGR_CC2G (1 << 2)RCC_CIER_HSIRDYIE (1 << 3)TIM_CR2_OIS_MASK (0x7f << 8)TIM_SMCR_MSM (1 << 7)__ARMEL__ 1TIM_CCMR2_IC4PSC_4 (0x2 << 10)__FLT32X_MAX_10_EXP__ 308TIM4_CR2 TIM_CR2(TIM4)timer_set_disabled_off_state_in_idle_modeTIM4_CCR1 TIM_CCR1(TIM4)TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)__SIG_ATOMIC_TYPE__ intLPUART1_BASE (PERIPH_BASE_APB + 0x8000)TIM_CCER_CC3NP (1 << 11)TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)TIM6_ARR TIM_ARR(TIM6)TIM_DIER_BIE (1 << 7)__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intTIM8_SMCR TIM_SMCR(TIM8)TIM2_AF1 TIM_AF1(TIM2)RCC_CFGR_PPRE_DIV4 0x5timer_set_counterTIM_CCMR2_OC4M_TOGGLE (0x3 << 12)RCC_PLLCFGR_PLLSRC_MASK 0x3RCC_APBENR1_DAC1EN (1 << 29)UINTMAX_MAX__HAVE_SPECULATION_SAFE_VALUE 1UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7DESIG_FLASH_SIZE_BASE (0x1FFF75E0)timer_enable_breakBIT15 (1<<15)TIM_CCMR2_IC3F_MASK (0xF << 4)RCC_CCIPR_I2S1SEL_I2S_CKIN 2__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)TIM_CCER_CC1E (1 << 0)PWR_CR1_LPMS_STOP_1 1BIT5 (1<<5)__BIGGEST_ALIGNMENT__ 8PWR_SR1_WUF1 (1 << 0)__ARM_ARCH__UINT8_TYPE__ unsigned chartimer_set_break_lockRCC_CCIPR_LPTIM1SEL_MASK 0x3TIM5_CR1 TIM_CR1(TIM5)__FLT32_MIN_10_EXP__ (-37)TIM15_BDTR TIM_BDTR(TIM15)TIM_IC_DTF_DIV_4_N_6PWR_CR1_DBP (1 << 8)TIM_IC_DTF_DIV_4_N_8__UINTMAX_TYPE__ long long unsigned intRCC_CFGR_SW_LSE 0x4__INT_LEAST16_MAX__ 0x7fffTIM2_BASE (PERIPH_BASE_APB + 0x0000)BIT12 (1<<12)TIM_CCER_CC3P (1 << 9)TIM9_CNT TIM_CNT(TIM9)TIM9_ARR TIM_ARR(TIM9)TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)__TA_IBIT__ 64TIM12_SR TIM_SR(TIM12)RCC_CR_PLLON (1 << 24)BIT16 (1<<16)__SACCUM_IBIT__ 8TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)TIM2_SMCR TIM_SMCR(TIM2)TIM2_EGR TIM_EGR(TIM2)__ARM_ASM_SYNTAX_UNIFIED____SIZEOF_WCHAR_T__ 4PWR_SCR_CWUF4 (1 << 3)TIM4_SMCR TIM_SMCR(TIM4)RCC_CFGR_MCOPRE_DIV8 3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32timer_clear_flag__FLT32X_HAS_INFINITY__ 1RCC_CCIPR_LPTIM1SEL_PCLK 0TIM_OCM_ACTIVETIM_CCMR2_OC3FE (1 << 2)TIM_CCMR2_IC4PSC_8 (0x3 << 10)RCC_CCIPR_LPUART1SEL_LSE 3RCC_CCIPR_USART2SEL_LSE 3__INT8_C(c) cRCC_APBRSTR1_SPI2RST (1 << 14)AES_BASE (PERIPH_BASE_AHB + 0x06000)__ARM_EABI__ 1UINT64_C(c) __UINT64_C(c)TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)__FLT32_EPSILON__ 1.1920928955078125e-7F32TIM7_PSC TIM_PSC(TIM7)TIM_CCMR2_IC3PSC_4 (0x2 << 2)TIM14_ARR TIM_ARR(TIM14)INT_LEAST8_MAX __INT_LEAST8_MAX__PWR_CR3_ULPEN (1 << 9)false 0__FLT_MAX_EXP__ 128RCC_CR_HSIDIV_DIV32 5__INT64_MAX__ 0x7fffffffffffffffLLBIT17 (1<<17)__ATOMIC_SEQ_CST 5TIM2_TISEL TIM_TISEL(TIM2)TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)PWR_SR2_FLASHRDY (1 << 8)RCC_CR MMIO32(RCC_BASE + 0x00)TIM_SMCR_TS_MASK (0x7 << 4)TIM17_BDTR TIM_BDTR(TIM17)RCC_CR_HSIDIV_DIV1 0TIM_SMCR_ECE (1 << 14)__FLT32X_MAX_EXP__ 1024__FLT32_MANT_DIG__ 24__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8TIM_CR2_MMS_MASK (0x7 << 4)__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15RCC_CSR_PWRRSTF (1 << 27)INTPTR_MAX __INTPTR_MAX__TIM9_CCR2 TIM_CCR2(TIM9)TIM_CCMR1_OC1CE (1 << 7)__DECIMAL_DIG__ 17__ARM_FEATURE_SIMD32PWR_SR1_SBF (1 << 8)INT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_AHBENR_FLASHEN (1 << 8)TIM17_PSC TIM_PSC(TIM17)TIM15_CR2 TIM_CR2(TIM15)__ARM_BF16_FORMAT_ALTERNATIVERCC_APBSMENR1_USART4SMEN (1 << 19)TIM16_CR1 TIM_CR1(TIM16)RCC_CFGR_MCO_PLLRCLK 0x5TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)TIM3_DMAR TIM_DMAR(TIM3)UINT64_CTIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)__UINT64_TYPE__ long long unsigned intTIM5_CR2 TIM_CR2(TIM5)TIM5_DMAR TIM_DMAR(TIM5)TIM_ET_FALLINGBIT18 (1<<18)__LFRACT_IBIT__ 0long long unsigned intRCC_BDCR_BDRST (1 << 16)RCC_CFGR_SWS_HSISYS 0x0__USER_LABEL_PREFIX__ RCC_PLLCFGR_PLLM_SHIFT 0x4TIM_SMCR_TS_ETRF (0x7 << 4)RCC_APBSMENR1_PWRSMEN (1 << 28)TIM3_DIER TIM_DIER(TIM3)RCC_CIFR_PLLRDYF (1 << 5)timer_enable_break_automatic_outputINT64_MAX __INT64_MAX__TIM_EGR_UG (1 << 0)__QQ_IBIT__ 0TIM3_AF1 TIM_AF1(TIM3)RCC_CR_HSIDIV_DIV64 6TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)UINT_LEAST64_MAXRCC_CCIPR_I2S1SEL_MASK 0x3RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)RCC_CR_HSIRDY (1 << 10)TIM_CCER_CC2P (1 << 5)TIM_OC2NTIM_CCMR1_IC2F_MASK (0xF << 12)__INT_FAST8_MAX__ 0x7fffffff__INT16_MAX__ 0x7fffVREFBUF_BASE (PERIPH_BASE_APB + 0x10030)TIM2_CCMR2 TIM_CCMR2(TIM2)__INT_FAST8_WIDTH__ 32timer_set_modeTIM16_BASE (PERIPH_BASE_APB + 0x14400)TIM8_RCR TIM_RCR(TIM8)TIM_CCMR1_IC1PSC_2 (0x1 << 2)__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_CCIPR_RNGDIV_SHIFT 28TIM_OR1_OCREF_CLR_COMP1 (0)__ARM_FP16_ARGSRCC_CCIPR_I2S1SEL_SYSCLK 0__FLT32_MIN_EXP__ (-125)TIM12_SMCR TIM_SMCR(TIM12)CORESIGHT_LSR_SLK (1<<1)TIM16_CCR1 TIM_CCR1(TIM16)RCC_BDCR_LSEDRV_MASK 0x3RCC_APBRSTR1_TIM6RST (1 << 4)__LDBL_MIN_EXP__ (-1021)RCC_APBENR1_WWDGEN (1 << 11)__DBL_MIN_10_EXP__ (-307)RCC_CCIPR_TIM15SEL_TIMPCLK 0BIT7 (1<<7)RCC_APBSMENR2_TIM15SMEN (1 << 16)TIM15_RCR TIM_RCR(TIM15)TIM8_BDTR TIM_BDTR(TIM8)TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)TIM6_CR1 TIM_CR1(TIM6)/build/libopencm3/lib/stm32/g0RCC_PLLCFGR_PLLSRC_NONE 0TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)TIM17_CCMR1 TIM_CCMR1(TIM17)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)TIM_CCMR1_IC2F_OFF (0x0 << 12)timer_peripheral__ARM_FEATURE_SATINT_LEAST64_MAX __INT_LEAST64_MAX__INT64_CTIM_PSC(tim_base) MMIO32((tim_base) + 0x28)PWR_CR2_PVDRT_SHIFT 4__UDQ_IBIT__ 0RCC_CCIPR_USART1SEL_HSI16 2__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_CCR4 TIM_CCR4(TIM1)TIM_CCMR2_IC4F_MASK (0xF << 12)__PTRDIFF_WIDTH__ 32TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)INT8_MAX __INT8_MAX____ULLACCUM_MIN__ 0.0ULLKTIM15_DIER TIM_DIER(TIM15)I2C1_BASE (PERIPH_BASE_APB + 0x5400)TIM3_CCR4 TIM_CCR4(TIM3)TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)RCC_APBENR1_UCPD2EN (1 << 26)INT_FAST64_MAXPWR_SCR_CWUF1 (1 << 0)timer_set_oc_modeTIM12_CCR2 TIM_CCR2(TIM12)timer_set_prescalerDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__ULFRACT_IBIT__ 0TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)__FLT64_EPSILON__ 2.2204460492503131e-16F64TIM_SR_CC3OF (1 << 11)__WINT_MAX__ 0xffffffffUTIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0)__ARM_FP16_FORMAT_ALTERNATIVE__arm__ 1RCC_CCIPR_TIM15SEL_SHIFT 24TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)UINTPTR_MAXINT32_C(c) __INT32_C(c)PWR_CR2_PVDFT_2V6 0x04__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned intRCC_AHBSMENR_CRCSMEN (1 << 12)__FLT_EPSILON__ 1.1920928955078125e-7FPWR_CR1_LPMS_STANDBY 3TIM_CCER_CC4P (1 << 13)RCC_CFGR_PPRE_SHIFT 12__UINT8_C(c) cRCC_APBENR2_OFFSET 0x40RCC_PLLCFGR_PLLR_MASK 0x7TIM_SR_UIF (1 << 0)RCC_AHBSMENR_RNGSMEN (1 << 18)__ARM_FEATURE_NUMERIC_MAXMINRCC_APBENR1_LPTIM2EN (1 << 30)RCC_CFGR_MCOPRE_MASK 0x7TIM14_BASE (PERIPH_BASE_APB + 0x2000)INT8_C(c) __INT8_C(c)UINT16_MAX __UINT16_MAX____ULLFRACT_MIN__ 0.0ULLRdirectionTIM_CCMR2_OC3M_PWM2 (0x7 << 4)TIM17 TIM17_BASEunsigned charTIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)PWR_CR2_PVDFT_2V5 0x03__LDBL_DIG__ 15__ARM_FEATURE_QRDMX__SOFTFP__ 1RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)BIT8 (1<<8)__SFRACT_IBIT__ 0RCC_APBRSTR2_TIM1RST (1 << 11)__ARM_FEATURE_QBITTIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)RCC_CIFR_HSIRDYF (1 << 3)TIM2_CCER TIM_CCER(TIM2)TIM_IC2TIM_IC3TIM_IC4TIM9_SMCR TIM_SMCR(TIM9)TIM17_DIER TIM_DIER(TIM17)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))TIM4_CCER TIM_CCER(TIM4)__FLT_DIG__ 6TIM14_EGR TIM_EGR(TIM14)RCC_CCIPR_RNGSEL_NONE 0TIM3_CCR3 TIM_CCR3(TIM3)__DBL_MAX_EXP__ 1024TIM_CCMR2_OC3M_PWM1 (0x6 << 4)TIM_CR2_MMS_ENABLE (0x1 << 4)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffffTIM6_CR2 TIM_CR2(TIM6)__SIZE_WIDTH__ 32TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)__ARM_FEATURE_FP16_FMLTIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)__ULFRACT_FBIT__ 32BIT2 (1<<2)TIM_CR1_CMS_CENTER_1 (0x1 << 5)TIM17_DMAR TIM_DMAR(TIM17)I2C2_BASE (PERIPH_BASE_APB + 0x5800)TIM_CCMR2_OC4M_MASK (0x7 << 12)DAC_BASE (PERIPH_BASE_APB + 0x7400)RCC_AHBENR_DMAEN (1 << 0)RCC_CCIPR_LPTIM2SEL_LSE 3RCC_CR_HSIDIV_DIV2 1TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)PWR_CR3_EWUP4 (1 << 3)TIM12_CCR1 TIM_CCR1(TIM12)TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)SIG_ATOMIC_MAXINT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_CSR_LSION (1 << 0)TIM_SR_CC1OF (1 << 9)TIM15_DCR TIM_DCR(TIM15)RCC_APBENR2_USART1EN (1 << 14)TIM_BDTR_BKP (1 << 13)__UACCUM_EPSILON__ 0x1P-16UKRCC_CFGR_SWS_LSI 0x3BEGIN_DECLS tim_et_pol__SFRACT_FBIT__ 7__LLACCUM_EPSILON__ 0x1P-31LLKRCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)TIM1_CCMR1 TIM_CCMR1(TIM1)PWR_CR2_PVDRT_2V6 0x03__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)SIZE_MAXWCHAR_MAX __WCHAR_MAX____FLT32_DECIMAL_DIG__ 9TIM_CCMR2_OC3M_MASK (0x7 << 4)TIM_CCMR1_IC2PSC_MASK (0x3 << 10)TIM7_CR1 TIM_CR1(TIM7)BIT9 (1<<9)TIM_SMCR_TS_TI1F_ED (0x4 << 4)TIM14_CCER TIM_CCER(TIM14)timer_set_output_idle_state__FLT32X_MANT_DIG__ 53TIM3 TIM3_BASERCC_CR_HSIKERON (1 << 9)TIM8_DIER TIM_DIER(TIM8)__WINT_TYPE__ unsigned intTIM_EGR_BG (1 << 7)RCC_AHBRSTR_OFFSET 0x28RCC_CSR_WWDGRSTF (1 << 30)PWR_CR4_WP2 (1 << 1)SCB_BASE (SCS_BASE + 0x0D00)TIM5_CCR2 TIM_CCR2(TIM5)RCC_CFGR_HPRE_SHIFT 8TIM_CR2_OIS3 (1 << 12)RCC_PLLCFGR_PLLSRC_HSI16 2TIM12_PSC TIM_PSC(TIM12)__FLT_MANT_DIG__ 24__ULACCUM_FBIT__ 32RCC_CCIPR_LPUART1SEL_HSI16 2__FLT64_HAS_QUIET_NAN__ 1TIM2_DCR TIM_DCR(TIM2)TIM5_CCMR2 TIM_CCMR2(TIM5)TIM1_RCR TIM_RCR(TIM1)RCC_BDCR_RTCSEL_NONE 0__ARM_ARCH_PROFILE 77RCC_APBSMENR1_DBGSMEN (1 << 27)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)timer_update_on_anyTIM14_CNT TIM_CNT(TIM14)TIM10_SR TIM_SR(TIM10)BIT20 (1<<20)modetimer_disable_break_automatic_output__INT_LEAST8_MAX__ 0x7ftimer_get_flag__FLT_MIN_EXP__ (-125)TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)oc_idRCC_CCIPR_I2C1SEL_HSI16 2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____UINT64_C(c) c ## ULL__FRACT_IBIT__ 0RCC_APBSMENR1_SPI2SMEN (1 << 14)PWR_CR2_PVDRT_2V7 0x04__FLT_RADIX__ 2__USA_FBIT__ 16TIM_DCR(tim_base) MMIO32((tim_base) + 0x48)RCC_CCIPR_I2S1SEL_PLLPLCK 1__LDBL_IS_IEC_60559__ 2TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16LTIM1_CR2 TIM_CR2(TIM1)TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)TIM16_CCER TIM_CCER(TIM16)TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)__FLT_EVAL_METHOD_TS_18661_3__ 0PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)TIM8_CCR4 TIM_CCR4(TIM8)__SQ_FBIT__ 31timer_set_oc_polarity_high__UINTMAX_MAX__ 0xffffffffffffffffULLTIM_DIER_CC4IE (1 << 4)__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15K__INTPTR_TYPE__ intRCC_APBSMENR1_TIM3SMEN (1 << 1)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbRCC_CCIPR_TIM15SEL_PLLQCLK 1TIM12_ARR TIM_ARR(TIM12)BIT21 (1<<21)PWR_SR1_WUF2 (1 << 1)TIM5_CCR1 TIM_CCR1(TIM5)RCC_CCIPR_TIM1SEL_PLLQCLK 1TIM11_SR TIM_SR(TIM11)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15RTIM_CCMR2_CC4S_IN_TI3 (0x2 << 8)__FLT_MIN_10_EXP__ (-37)timer_disable_compare_control_update_on_triggerTIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3TIM7_CR2 TIM_CR2(TIM7)RCC_CCIPR_USART1SEL_SYSCLK 1TIM11_CCMR1 TIM_CCMR1(TIM11)__INT_WIDTH__ 32RCC_CIER_PLLRDYIE (1 << 5)RCC_BDCR_LSCOEN (1 << 24)TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)RCC_APBSMENR2_TIM1SMEN (1 << 11)TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)RCC_CFGR_SW_SHIFT 0TIM16_PSC TIM_PSC(TIM16)TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C)RCC_CFGR_MCO_HSI16 0x3CORESIGHT_LAR_KEY 0xC5ACCE55NVIC_BASE (SCS_BASE + 0x0100)__UDQ_FBIT__ 64TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)__FLT64_DIG__ 15__ARM_NEONcountRCC_APBRSTR1_TIM7RST (1 << 5)timer_get_counter__INT16_C(c) cRCC_ICSCR_HSICAL_SHIFT 0INT_FAST8_MAXPWR_SCR_CWUF5 (1 << 4)BIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17timer_enable_irqTIM9_SR TIM_SR(TIM9)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1TIM10_CCER TIM_CCER(TIM10)__INT16_TYPE__ short intTIM_CR2_OIS1N (1 << 9)UINTMAX_CRCC_APBENR1_USART2EN (1 << 17)__bool_true_false_are_defined 1__FRACT_MIN__ (-0.5R-0.5R)TIM_CR2_CCDS (1 << 3)TIM_CCMR2_OC4PE (1 << 11)TIM10_CR1 TIM_CR1(TIM10)RCC_CCIPR_LPUART1SEL_SHIFT 10TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)RCC_CCIPR_I2C1SEL_SHIFT 12TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)TIM14_SR TIM_SR(TIM14)__GCC_ATOMIC_LONG_LOCK_FREE 1_GCC_STDINT_H TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)PTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0__UHQ_FBIT__ 16uint8_tINT16_C(c) __INT16_C(c)INTMAX_MIN (-INTMAX_MAX - 1)timer_one_shot_modeRCC_BDCR_LSCOSEL (1 << 25)TIM_CR1_DIR_UP (0 << 4)TIM8_CR1 TIM_CR1(TIM8)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)RCC_CFGR_MCOPRE_DIV16 4__INT_MAX__ 0x7fffffffRCC_BDCR_LSEDRV_LOW 0timer_disable_irqBIT23 (1<<23)TIM5_CCMR1 TIM_CCMR1(TIM5)TIM3_SMCR TIM_SMCR(TIM3)__WCHAR_MIN__ 0UPWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)RCC_CIFR MMIO32(RCC_BASE + 0x1c)TIM_DIER_TDE (1 << 14)TIM5_SMCR TIM_SMCR(TIM5)PWR_CR1_FPD_LPRUN (1 << 4)TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)TIM_CCMR1_IC1PSC_OFF (0x0 << 2)RCC_BDCR_LSEDRV_MEDHIGH 2TIM_CCMR2_IC3PSC_OFF (0x0 << 2)TIM10_ARR TIM_ARR(TIM10)timer_set_dma_on_update_eventRCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)_REG_BIT(offset,bit) (((offset) << 5) + (bit))RCC_APBRSTR2_SYSCFGRST (1 << 0)TIM_CCMR2_OC3M_INACTIVE (0x2 << 4)__INT_LEAST32_MAX__ 0x7fffffffLRCC_APBRSTR1_OFFSET 0x2cRCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15TIM_CCMR1_OC1M_FROZEN (0x0 << 4)PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)__ATOMIC_ACQ_REL 4__INT32_MAX__ 0x7fffffffLTIM_CCMR2_CC4S_MASK (0x3 << 8)TIM_CR2_OIS2 (1 << 10)__CHAR_UNSIGNED__ 1TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)RCC_APBENR1_OFFSET 0x3cBIT24 (1<<24)TIM_CCMR1_IC2PSC_2 (0x1 << 10)TIM4_CR1 TIM_CR1(TIM4)__SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1TIM13_ARR TIM_ARR(TIM13)TIM13_CNT TIM_CNT(TIM13)INT16_MAX __INT16_MAX__RCC_APBENR1_TIM7EN (1 << 5)RCC_APBENR1_CECEN (1 << 24)TIM_IC_DTF_DIV_8_N_6TIM_IC_DTF_DIV_8_N_8timer_disable_counter__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CIFR_HSERDYF (1 << 4)RCC_PLLCFGR_PLLQEN (1 << 24)tim_ic_pscTIM15_CCR1 TIM_CCR1(TIM15)LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)TIM2_CR2 TIM_CR2(TIM2)__ULFRACT_EPSILON__ 0x1P-32ULRTIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)TIM8_SR TIM_SR(TIM8)INT_LEAST32_MAX __INT_LEAST32_MAX__TIM_EGR_CC3G (1 << 3)RCC_APBRSTR1_DBGRST (1 << 27)TIM_IC_PSC_4TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)TIM_CR1_UDIS (1 << 1)TIM_CCMR1_IC1PSC_8 (0x3 << 2)PWR_SR1_WUFI (1 << 15)__ARM_ARCH_EXT_IDIV__UINT_FAST64_MAX __UINT_FAST64_MAX__timer_slave_set_prescalerBIT25 (1<<25)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xTIM_SR_CC2IF (1 << 2)RCC_APBENR1_DBGEN (1 << 27)TIM_CCMR2_OC4M_PWM2 (0x7 << 12)TIM2_DIER TIM_DIER(TIM2)TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)TIM8_CR2 TIM_CR2(TIM8)RCC_CCIPR_CECSEL_SHIFT 6RCC_CCIPR_RNGSEL_HSI16 1TIM4_DIER TIM_DIER(TIM4)TIM1_PSC TIM_PSC(TIM1)TIM2_OR1 TIM_OR1(TIM2)__SCHAR_WIDTH__ 8TIM8_CCR2 TIM_CCR2(TIM8)__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2timer_set_disabled_off_state_in_run_modeRCC_PLLCFGR_PLLP_MASK 0x1f__INT_FAST32_WIDTH__ 32RCC_BDCR_RTCSEL_HSE_DIV32 3__INT_FAST64_TYPE__ long long inttimer_set_master_mode__ACCUM_FBIT__ 15__INT_LEAST64_MAX__ 0x7fffffffffffffffLLTIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)__UHQ_IBIT__ 0__UINT32_C(c) c ## ULTIM_SR_CC2OF (1 << 10)UINT32_C(c) __UINT32_C(c)deadtimeRCC_APBRSTR1_LPTIM2RST (1 << 30)TIM_CCMR1_IC2PSC_4 (0x2 << 10)__SACCUM_MAX__ 0X7FFFP-7HKTIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)INTMAX_MAXTIM_CR1_OPM (1 << 3)TIM2 TIM2_BASETIM3_EGR TIM_EGR(TIM3)__ACCUM_IBIT__ 16UINT64_MAX __UINT64_MAX__TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)TIM8_CCER TIM_CCER(TIM8)__INTMAX_WIDTH__ 64RCC_CCIPR_RNGSEL_PLLQCLK 3TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38)timer_slave_set_triggerTIM_IC_IN_TI1__INT_LEAST64_WIDTH__ 64valueRCC_APBENR2_TIM17EN (1 << 18)TIM_DIER_CC1DE (1 << 9)TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)__ATOMIC_RELAXED 0TIM9_CR1 TIM_CR1(TIM9)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0__ULACCUM_IBIT__ 32TIM_SMCR_SMS_EM3 (0x3 << 0)__THUMB_INTERWORK__ 1PPBI_BASE (0xE0000000U)TIM4_CCR4 TIM_CCR4(TIM4)CEC_BASE (PERIPH_BASE_APB + 0x7800)BIT27 (1<<27)PWR_CR2_PVDFT_2V0 0x00TIM_CR2_MMS_UPDATE (0x2 << 4)RCC_CCIPR_TIM1SEL_MASK 0x1__FRACT_MAX__ 0X7FFFP-15RRCC_CFGR_HPRE_DIV64 0xcTIM_BDTR_LOCK_MASK (0x3 << 8)TIM7_BASE (PERIPH_BASE_APB + 0x1400)RCC_BASE (PERIPH_BASE_AHB + 0x01000)__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UFRACT_IBIT__ 0TIM_SMCR_SMS_EM2 (0x2 << 0)TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40)TIM_CCMR2_OC4M_FROZEN (0x0 << 12)RCC_CCIPR_LPTIM2SEL_LSI 1RCC_APBSMENR2_TIM17SMEN (1 << 18)TIM9_CCMR1 TIM_CCMR1(TIM9)MMIO32(addr) (*(volatile uint32_t *)(addr))TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)TIM_CCMR2_CC4S_IN_TI4 (0x1 << 8)TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)TIM_DIER_UDE (1 << 8)TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)SPI1_BASE (PERIPH_BASE_APB + 0x13000)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)RCC_PLLCFGR_PLLPEN (1 << 16)__SIZE_MAX__ 0xffffffffUtimer_disable_break_main_output__ATOMIC_RELEASE 3rcc_apb2_frequency rcc_apb1_frequencyRCC_APBSMENR2_TIM14SMEN (1 << 15)BIT28 (1<<28)__GNUC__ 12__INT_LEAST8_WIDTH__ 8PWR_CR3_EWUP5 (1 << 4)TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)PWR_CR2_PVDRT_2V2 0x01TIM_SMCR_SMS_MASK (0x7 << 0)__ARM_FEATURE_COPROCRCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intTIM4_SR TIM_SR(TIM4)RCC_APBENR1_LPTIM1EN (1 << 31)TIM_SR_CC4OF (1 << 12)__INT_LEAST32_WIDTH__ 32__FLT32_IS_IEC_60559__ 2__UTQ_IBIT__ 0TIM_BDTR_DTG_MASK 0x00FFTIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)__DBL_IS_IEC_60559__ 2RCC_PLLCFGR_PLLN_MUL(x) (x)TIM_CCMR1_IC2PSC_8 (0x3 << 10)__UTA_IBIT__ 64TIM_CR2_OIS3N (1 << 13)__SIZEOF_WINT_T__ 4RCC_CFGR_HPRE_DIV256 0xeTIM5_CCER TIM_CCER(TIM5)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)INT_FAST8_MINTIM_CCMR2_IC3PSC_8 (0x3 << 2)RCC_APBENR1_I2C1EN (1 << 21)TIM_CCMR2_IC4PSC_OFF (0x0 << 10)TIM_CCMR2_OC3CE (1 << 7)RCC_APBSMENR1_CECSMEN (1 << 24)RCC_APBRSTR1_DAC1RST (1 << 29)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)RCC_CCIPR_LPUART1SEL_PCLK 0PWR_CR2_PVDRT_2V1 0x00TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)TIM13_EGR TIM_EGR(TIM13)__FLT_MAX__ 3.4028234663852886e+38FTIM_OR1(tim_base) MMIO32((tim_base) + 0x50)__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)PWR_SR1_WUF5 (1 << 4)INT32_CTIM_CCMR1_IC1PSC_MASK (0x3 << 2)TIM_IC_PSC_OFFTIM_SMCR_SMS_OFF (0x0 << 0)__ARM_ARCH_ISA_THUMB../common/timer_common_all.c__FLT64_IS_IEC_60559__ 2timer_disable_oc_preloadTIM16 TIM16_BASETIM11_DIER TIM_DIER(TIM11)INTMAX_CTIM2_PSC TIM_PSC(TIM2)__USACCUM_MAX__ 0XFFFFP-8UHK__WINT_MIN__ 0U__INT8_MAX__ 0x7ftimer_slave_set_filterRCC_CCIPR_TIM15SEL_MASK 0x1TIM_CCER_CC2NP (1 << 7)DESIG_UNIQUE_ID_BASE (0x1FFF7590)TIM_CCMR2_CC3S_OUT (0x0 << 0)RCC_AHBRSTR_CRCRST (1 << 12)TIM_SR_CC3IF (1 << 3)TIM_OR1_OCREF_CLR (1 << 0)TIM17_ARR TIM_ARR(TIM17)TIM_CCER_CC2NE (1 << 6)TIM17_CNT TIM_CNT(TIM17)__USACCUM_EPSILON__ 0x1P-8UHKPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)RCC_CFGR MMIO32(RCC_BASE + 0x08)periodPERIPH_BASE_APB (PERIPH_BASE + 0x00000)__USFRACT_EPSILON__ 0x1P-8UHRRCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__UINT_FAST16_MAX__ 0xffffffffU__UINT_FAST64_TYPE__ long long unsigned intRCC_APBRSTR1_PWRRST (1 << 28)RCC_CFGR_MCOPRE_DIV1 0INFO_BASE (0x1fff7500U)BIT0 (1<<0)TIM4_EGR TIM_EGR(TIM4)TIM_RCR(tim_base) MMIO32((tim_base) + 0x30)RCC_CFGR_MCOPRE_DIV64 6__UFRACT_EPSILON__ 0x1P-16URTIM17_CCR1 TIM_CCR1(TIM17)RCC_CSR_SFTRSTF (1 << 28)TIM_OCM_FORCE_HIGH__ULACCUM_MIN__ 0.0ULK__SIZEOF_SIZE_T__ 4PWR_CR2_PVDFT_MASK 0x07TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)RCC_APBSMENR2_USART1SMEN (1 << 14)LIBOPENCM3_MEMORYMAP_COMMON_H TIM_IC_IN_TI2TIM_IC_IN_TI3TIM_IC_IN_TI4BIT19 (1<<19)timer_slave_set_polarity__UINT_FAST8_MAX__ 0xffffffffUTIM_IC_DTF_DIV_2_N_6TIM9_DIER TIM_DIER(TIM9)TIM_IC_DTF_DIV_2_N_8TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)RCC_AHBRSTR_FLASHRST (1 << 8)STM32G0 1__SQ_IBIT__ 0TIM_CCMR2_OC4FE (1 << 10)flag__thumb2__INT_FAST16_MIN (-INT_FAST16_MAX - 1)TIM_BDTR_DBA_MASK (0x1F << 0)TIM3_SR TIM_SR(TIM3)RCC_PLLCFGR_PLLSRC_SHIFT 0PWR_CR2_PVDRT_3V0 0x06TIM1_CCR3 TIM_CCR3(TIM1)TIM3_OR1 TIM_OR1(TIM3)PWR_CR3_APC (1 << 10)RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)__SFRACT_MIN__ (-0.5HR-0.5HR)TIM16_AF1 TIM_AF1(TIM16)RCC_APBENR1_LPUART1EN (1 << 20)__LACCUM_FBIT__ 31TIM_IC_DTF_DIV_16_N_5TIM_IC_DTF_DIV_16_N_6TIM_CCMR1_OC2M_MASK (0x7 << 12)TIM_IC_DTF_DIV_16_N_8USART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CFGR_SW_HSE 0x1TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44)__ARM_32BIT_STATETIM_CCMR1_IC1PSC_4 (0x2 << 2)RCC_PLLCFGR_PLLN_SHIFT 0x8__LONG_MAX__ 0x7fffffffLTIM16_DMAR TIM_DMAR(TIM16)timer_set_dma_on_compare_event__INT32_C(c) c ## LTIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64TIM_DIER_CC3IE (1 << 3)TIM_OR1_OCREF_CLR_COMP2 (1)WINT_MAX __WINT_MAX__TIM_CCMR1_OC2M_PWM2 (0x7 << 12)PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)triggerINT_FAST16_MAX __INT_FAST16_MAX__RCC_CCIPR_RNGDIV_MASK 0x3TIM_CR2(tim_base) MMIO32((tim_base) + 0x04)RCC_CCIPR_USART2SEL_PCLK 0RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)__FLT32X_IS_IEC_60559__ 2__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE_MASK 0x7timer_direction_downUINT_FAST32_MAX __UINT_FAST32_MAX__TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)TIM1_CNT TIM_CNT(TIM1)UINT32_CTIM1_ARR TIM_ARR(TIM1)short unsigned int__LDBL_DECIMAL_DIG__ 17signed charPWR_SCR_CWUF6 (1 << 5)RCC_CCIPR_I2S1SEL_HSI16 2TIM_EGR_CC4G (1 << 4)LIBOPENCM3_RCC_H RCC_CCIPR_USART2SEL_SYSCLK 1TIM_CCMR2_CC3S_MASK (0x3 << 0)TIM_CCMR2_IC4PSC_MASK (0x3 << 10)INTMAX_C(c) __INTMAX_C(c)timer_generate_eventTIM9_PSC TIM_PSC(TIM9)PWR_CR4_VBRS (1 << 9)TIM_SR_CC4IF (1 << 4)__CHAR_BIT__ 8INTMAX_MINRCC_BDCR MMIO32(RCC_BASE + 0x5c)TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)TIM13_CCER TIM_CCER(TIM13)RCC_APBENR1_PWREN (1 << 28)TIM14_CCMR1 TIM_CCMR1(TIM14)TIM_CCMR2_CC4S_OUT (0x0 << 8)USART2_BASE (PERIPH_BASE_APB + 0x4400)timer_set_oc_slow_modeTIM_BDTR_AOE (1 << 14)RCC_CCIPR_I2C1SEL_PCLK 0timer_disable_break__ARM_FEATURE_DOTPRODRCC_CCIPR_USART1SEL_LSE 3TIM_CCMR1_OC1M_PWM2 (0x7 << 4)RCC_APBRSTR1_UCPD2RST (1 << 26)timer_set_periodTIM1 TIM1_BASETIM_SR_TIF (1 << 6)TIM3_PSC TIM_PSC(TIM3)PWR_SR2_REGLPF (1 << 9)TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)__CHAR16_TYPE__ short unsigned int__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__UINT16_TYPE__ short unsigned intINTPTR_MAX__GCC_ATOMIC_POINTER_LOCK_FREE 1timer_interrupt_sourceRCC_APBSMENR1_LPTIM2SMEN (1 << 30)RCC_APBENR1_SPI2EN (1 << 14)__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1TIM_CCMR1_OC1M_PWM1 (0x6 << 4)RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)__FLT32_MAX_10_EXP__ 38__ORDER_LITTLE_ENDIAN__ 1234TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)TIM_TISEL(tim_base) MMIO32((tim_base) + 0x68)RCC_PLLCFGR_PLLP_SHIFT 17TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)TIM5_EGR TIM_EGR(TIM5)INT_LEAST8_MAX__WINT_WIDTH__ 32timer_set_enabled_off_state_in_run_modePERIPH_BASE (0x40000000U)__SIZEOF_INT__ 4tim_ic_filter__LDBL_HAS_DENORM__ 1USART4_BASE (PERIPH_BASE_APB + 0x4C00)TIM5 TIM5_BASEtimer_disable_oc_output__ARM_FP16_FORMAT_IEEETIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)TIM17_EGR TIM_EGR(TIM17)RCC_CIFR_CSSF (1 << 8)__ARM_FEATURE_IDIV__USES_INITFINI__ 1__GCC_ATOMIC_INT_LOCK_FREE 1BIT30 (1<<30)__FLT64_MAX_EXP__ 1024RCC_CR_HSIDIV_DIV16 4RCC_CR_HSIDIV_MASK 0x7TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)__REGISTER_PREFIX__ RCC_BDCR_RTCSEL_LSE 1__USFRACT_MAX__ 0XFFP-8UHRTIM4_DCR TIM_DCR(TIM4)RCC_APBRSTR1_I2C2RST (1 << 22)RCC_APBENR1_USART3EN (1 << 18)RCC_APBRSTR2_TIM14RST (1 << 15)__FLT32_MAX__ 3.4028234663852886e+38F32TIM10_CCMR1 TIM_CCMR1(TIM10)TIM4_CCMR1 TIM_CCMR1(TIM4)TIM_CR2_CCPC (1 << 0)RCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)TIM_CCMR2_OC4M_PWM1 (0x6 << 12)RCC_CCIPR_LPTIM2SEL_PCLK 0timer_ic_disableRCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)RCC_APBENR1_TIM6EN (1 << 4)TIM_EGR(tim_base) MMIO32((tim_base) + 0x14)TIM1_CCR2 TIM_CCR2(TIM1)TIM_CCMR1_OC1M_MASK (0x7 << 4)TIM_CCMR1_OC1PE (1 << 3)RCC_CCIPR_RNGDIV_4 2__USQ_FBIT__ 32RCC_APBSMENR2_TIM16SMEN (1 << 17)TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)__INT_FAST8_TYPE__ intTIM_ET_RISINGUINT8_C(c) __UINT8_C(c)UINT32_MAX__ARM_FEATURE_BF16_SCALAR_ARITHMETICCOMP_BASE (PERIPH_BASE_APB + 0x10200)PWR_CR4_VBE (1 << 8)__FLT_MIN__ 1.1754943508222875e-38FPWR_SR2_VOSF (1 << 10)TIM5_SR TIM_SR(TIM5)TIM15_CR1 TIM_CR1(TIM15)RCC_AHBRSTR_DMARST (1 << 0)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLTIM_CCER_CC4E (1 << 12)TIM16_SR TIM_SR(TIM16)__UACCUM_MAX__ 0XFFFFFFFFP-16UKTIM12_CNT TIM_CNT(TIM12)RCC_CSR_LPWRRSTF (1 << 31)RCC_PLLCFGR_PLLM_DIV(x) ((x)-1)TIM_SMCR_ETPS_MASK (0X3 << 12)TIM_OCM_FROZENlong intRCC_CFGR_MCO_SYSCLK 0x1TIM_SR_CC1IF (1 << 1)TIM2_CNT TIM_CNT(TIM2)__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)TIM2_ARR TIM_ARR(TIM2)INT16_MAX__DBL_HAS_DENORM__ 1TIM_CCMR1_OC1M_TOGGLE (0x3 << 4)__ARM_FEATURE_FMAoc_mode__FLT64_MAX_10_EXP__ 308__PTRDIFF_TYPE__ intTIM8_CCR1 TIM_CCR1(TIM8)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1__FLT32X_HAS_DENORM__ 1TIM_CCMR2_OC3M_FROZEN (0x0 << 4)TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1PWR_CR3_RRS (1 << 8)TIM5_CNT TIM_CNT(TIM5)UINT64_MAXGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM15_PSC TIM_PSC(TIM15)PWR_CR2_PVDFT_2V9 0x06RCC_CICR_PLLRDYC (1 << 5)TIM14_CR1 TIM_CR1(TIM14)RCC_CICR_LSERDYC (1 << 1)IOPORT_BASE (0x50000000U)TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)UINT_FAST8_MAX__WCHAR_WIDTH__ 32RCC_CFGR_SW_LSI 0x3TIM5_DIER TIM_DIER(TIM5)__UTQ_FBIT__ 128LIBOPENCM3_CM3_COMMON_H RCC_CCIPR_USART2SEL_SHIFT 2RCC_APBSMENR1_DAC1SMEN (1 << 29)RCC_APBSMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_RNGSEL_SYSCLK 2TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)TIM9_EGR TIM_EGR(TIM9)TIM11_CCR1 TIM_CCR1(TIM11)RCC_AHBENR_CRCEN (1 << 12)__ARM_FEATURE_CRYPTOTIM4_PSC TIM_PSC(TIM4)TIM_OCM_TOGGLESYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)TIM_CCER_CC2E (1 << 4)RCC_CCIPR_LPTIM2SEL_SHIFT 20LIBOPENCM3_PWR_H __FLT32_HAS_DENORM__ 1TIM12_CR1 TIM_CR1(TIM12)__UINT_FAST32_TYPE__ unsigned intRCC_CFGR_MCO_MASK 0xfPWR_CR2_PVDFT_2V8 0x05INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_BDCR_LSEDRV_SHIFT 3__SACCUM_FBIT__ 7__HQ_FBIT__ 15TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)__LLACCUM_IBIT__ 32uint32_tPWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)__ARM_FPtimer_enable_compare_control_update_on_triggertimer_set_repetition_counterTIM_EGR_CC1G (1 << 1)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__TIM_CCER_CC1NP (1 << 3)__GCC_ATOMIC_SHORT_LOCK_FREE 1TIM_BDTR_BKE (1 << 12)tim_oc_mode__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRPWR_CR1_VOS_RANGE_1 1__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_MASK 0x3TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)UINT_LEAST64_MAX __UINT_LEAST64_MAX__RCC_CR_HSIDIV_SHIFT 11RCC_APBSMENR1_USART3SMEN (1 << 18)TIM_OCM_FORCE_LOWtimer_set_oc_polarity_low__INTPTR_WIDTH__ 32TIM_IC_IN_TRCPWR_CR3_EWUP6 (1 << 5)INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXLIBOPENCM3_RCC_COMMON_ALL_H INTPTR_MINTIM5_CCR4 TIM_CCR4(TIM5)RCC_APBENR1_TIM3EN (1 << 1)RCC_CFGR_MCOPRE_DIV128 7TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)RCC_CCIPR_LPUART1SEL_SYSCLK 1PWR_CR4_WP5 (1 << 4)__FLT64_HAS_INFINITY__ 1TIM_CR2_OIS2N (1 << 11)__GCC_DESTRUCTIVE_SIZE 64RCC_APBRSTR1_USART4RST (1 << 19)RCC_APBENR1_RTCAPBEN (1 << 10)TIM5_DCR TIM_DCR(TIM5)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CFGR_PPRE_DIV8 0x6RCC_CR_PLLRDY (1 << 25)TIM10_DIER TIM_DIER(TIM10)timer_ic_set_prescalerTIM2_CCR1 TIM_CCR1(TIM2)__ULLACCUM_EPSILON__ 0x1P-32ULLK__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"TIM1_BDTR TIM_BDTR(TIM1)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C)RCC_CFGR_PPRE_NODIV 0x0PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0TIM_CNT(tim_base) MMIO32((tim_base) + 0x24)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)RCC_CCIPR_ADCSEL_MASK 0x3PWR_CR2_PVDRT_2V9 0x05INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1__ULACCUM_EPSILON__ 0x1P-32ULKTIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)PWR_SR1_WUF6 (1 << 5)TIM10_PSC TIM_PSC(TIM10)TIM_IC_DTF_DIV_32_N_5TIM_IC_DTF_DIV_32_N_6TIM_IC_DTF_DIV_32_N_8TIM17_RCR TIM_RCR(TIM17)TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)__LONG_LONG_WIDTH__ 64INT_LEAST64_MINTIM8_CCMR1 TIM_CCMR1(TIM8)__VERSION__ "12.2.1 20221205"BIT26 (1<<26)PWR_CR1_LPMS_STOP_0 0TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)PWR_CR4_WP4 (1 << 3)TIM_CR1(tim_base) MMIO32((tim_base) + 0x00)RCC_APBRSTR1_TIM3RST (1 << 1)__ULLACCUM_FBIT__ 32TIM_CCER_CC1P (1 << 1)TIM3_CNT TIM_CNT(TIM3)__LDBL_HAS_QUIET_NAN__ 1TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)TIM3_ARR TIM_ARR(TIM3)RCC_CR_CSSON (1 << 19)TIM2_CCR4 TIM_CCR4(TIM2)__WCHAR_MAX__ 0xffffffffUTIM14_DIER TIM_DIER(TIM14)RCC_BDCR_LSEON (1 << 0)RCC_CCIPR_RNGDIV_2 1TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)TIM5_CCR3 TIM_CCR3(TIM5)SPI2_BASE (PERIPH_BASE_APB + 0x3800)__ULLACCUM_IBIT__ 32__LDBL_MANT_DIG__ 53RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__ULLFRACT_FBIT__ 64WCHAR_MAX__DQ_IBIT__ 0TIM12_EGR TIM_EGR(TIM12)TIM_CCER(tim_base) MMIO32((tim_base) + 0x20)__FLT64_MAX__ 1.7976931348623157e+308F64TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)INT_LEAST8_MINTIM_SMCR_TS_TI2FP2 (0x6 << 4)TIM_CR1_URS (1 << 2)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0PWR_CR1_LPR (1 << 14)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))timer_set_enabled_off_state_in_idle_modePWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)TIM_CCMR2_OC4CE (1 << 15)__SIG_ATOMIC_WIDTH__ 32RCC_AHBSMENR_AESSMEN (1 << 16)timer_enable_preload_complementry_enable_bitsTIM_CR1_CKD_CK_INT (0x0 << 8)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)TIM17_SR TIM_SR(TIM17)__ARM_FEATURE_CDETIM2_SR TIM_SR(TIM2)TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)TIM1_EGR TIM_EGR(TIM1)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)TIM10_EGR TIM_EGR(TIM10)PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)SYS_TICK_BASE (SCS_BASE + 0x0010)TIM_BDTR_OSSI (1 << 10)RCC_APBSMENR1_TIM6SMEN (1 << 4)__ARM_FEATURE_LDREXTIM16_ARR TIM_ARR(TIM16)TIM16_CNT TIM_CNT(TIM16)__UINT_LEAST32_MAX__ 0xffffffffULRCC_APBENR1_I2C2EN (1 << 22)TIM_CR2_CCUS (1 << 2)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__SIZE_TYPE__ unsigned int__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSEGPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)PWR_SR1_WUF4 (1 << 3)__UFRACT_MAX__ 0XFFFFP-16URTIM_CCMR1_OC2M_PWM1 (0x6 << 12)BIT14 (1<<14)TIM15 TIM15_BASETIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C)TIM_CCMR2_IC3PSC_MASK (0x3 << 2)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)RCC_APBRSTR2_USART1RST (1 << 14)TIM7_EGR TIM_EGR(TIM7)timer_enable_oc_outputtrue 1timer_enable_break_main_outputTIM_DIER_COMIE (1 << 5)TIM_EGR_COMG (1 << 5)TIM17_CR2 TIM_CR2(TIM17)RCC_PLLCFGR_PLLREN (1<<28)RCC_CFGR_SWS_HSE 0x1lockTIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)TIM15_CCMR1 TIM_CCMR1(TIM15)__FLT_DECIMAL_DIG__ 9TIM_DIER_TIE (1 << 6)BIT31 (1<<31)__INT32_TYPE__ long int__USACCUM_IBIT__ 8TIM14_CCR1 TIM_CCR1(TIM14)RCC_CCIPR_ADCSEL_PLLPCLK 1timer_enable_oc_preload__ULFRACT_MIN__ 0.0ULRRCC_CCIPR_RNGSEL_MASK 0x3tim_ic_inputTIM1_DMAR TIM_DMAR(TIM1)TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)TIM_DIER_CC2IE (1 << 2)RCC_CCIPR_I2C1SEL_MASK 0x3__UINTPTR_TYPE__ unsigned intRCC_AHBSMENR_FLASHSMEN (1 << 8)TIM_SMCR_ETP (1 << 15)__FINITE_MATH_ONLY__ 0RCC_AHBENR_OFFSET 0x38UINT8_MAX __UINT8_MAX__TIM_DIER_CC3DE (1 << 11)__ARM_FEATURE_UNALIGNEDRCC_CCIPR_USART2SEL_MASK 0x3__LFRACT_FBIT__ 31PWR_CR1_VOS_RANGE_2 2RCC_APBSMENR2_OFFSET 0x50__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_MCO_SHIFT 24RCC_CCIPR_CECSEL_HSI16 0RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_TISEL TIM_TISEL(TIM17)RCC_BDCR_LSEBYP (1 << 2)UINT8_MAXRCC_APBENR2_SYSCFGEN (1 << 0)RCC_APBSMENR1_TIM2SMEN (1 << 0)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_CSR MMIO32(RCC_BASE + 0x60)PWR_CR2_PVDE (1 << 0)__INT64_C(c) c ## LLPWR_SCR_CWUF2 (1 << 1)__ARM_FEATURE_CRC32INT_LEAST16_MAXRCC_APBSMENR1_I2C2SMEN (1 << 22)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32TIM_CCMR1_OC2CE (1 << 15)SIZE_MAX __SIZE_MAX__timer_set_oc_idle_state_unsetINT8_MINTIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)RCC_CFGR_SW_HSISYS 0x0TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18)__GCC_ATOMIC_BOOL_LOCK_FREE 1INT_FAST64_MINIWDG_BASE (PERIPH_BASE_APB + 0x3000)__INT_FAST32_MAX__ 0x7fffffffRCC_CFGR_MCOPRE_DIV4 2__FLT_MAX_10_EXP__ 38TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)TIM4_CNT TIM_CNT(TIM4)WINT_MIN __WINT_MIN__TIM4_ARR TIM_ARR(TIM4)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX____GCC_IEC_559_COMPLEX 0__TQ_FBIT__ 127__VFP_FP__ 1TIM_CR2_OIS4 (1 << 14)TIM_IC_OUTRCC_APBSMENR2_SPI1SMEN (1 << 12)TIM_CR2_OIS1 (1 << 8)RCC_PLLCFGR_PLLQ_SHIFT 25RCC_CICR_HSIRDYC (1 << 3)INT32_MAXTIM9_CCR1 TIM_CCR1(TIM9)PWR_CR1_VOS_SHIFT 9RCC_PLLCFGR_PLLM_MASK 0x7__UFRACT_MIN__ 0.0URRCC_CFGR_PPRE_DIV16 0x7PWR_SR2_PVDO (1 << 11)TIM5_PSC TIM_PSC(TIM5)RCC_CCIPR_LPTIM2SEL_MASK 0x3RCC_APBENR2_TIM15EN (1 << 16)TIM_CCMR2_CC3S_IN_TI4 (0x2 << 0)TIM_BDTR_MOE (1 << 15)__ARM_SIZEOF_WCHAR_T 4UINT_LEAST32_MAX __UINT_LEAST32_MAX____SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)RCC_BDCR_RTCSEL_MASK 0x3RCC_APBENR2_TIM1EN (1 << 11)TIM_SR(tim_base) MMIO32((tim_base) + 0x10)RCC_APBRSTR2_TIM16RST (1 << 17)RCC_AHBENR_RNGEN (1 << 18)__GCC_ASM_FLAG_OUTPUTS__RCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICTIM6_PSC TIM_PSC(TIM6)TIM_SMCR_TS_ITR1 (0x1 << 4)TIM_CCMR1_CC2S_MASK (0x3 << 8)RCC_APBENR2_ADCEN (1 << 20)RCC_CFGR_SW_PLLRCLK 0x2RCC_CCIPR_RNGDIV_1 0TIM_IC1__INTMAX_MAX__ 0x7fffffffffffffffLLINT64_MAXRCC_BDCR_RTCEN (1 << 15)TIM15_DMAR TIM_DMAR(TIM15)UINT_LEAST16_MAX __UINT_LEAST16_MAX__PWR_CR1_FPD_STOP (1 << 3)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1TIM_BDTR_LOCK_OFF (0x0 << 8)TIM_CCMR1_IC2PSC_OFF (0x0 << 10)TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)TIM10_CCR1 TIM_CCR1(TIM10)TIM15_BASE (PERIPH_BASE_APB + 0x14000)PTRDIFF_MINTIM8_EGR TIM_EGR(TIM8)RCC_APBRSTR1_USART3RST (1 << 18)TIM1_DCR TIM_DCR(TIM1)RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1RCC_CCIPR_ADCSEL_HSI16 2TIM1_CR1 TIM_CR1(TIM1)RCC_APBRSTR2_OFFSET 0x30TIM16_EGR TIM_EGR(TIM16)TIM_CR2_MMS_RESET (0x0 << 4)TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)TIM1_CCR1 TIM_CCR1(TIM1)timer_set_ti1_ch1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_PLLCFGR_PLLN_MASK 0x7f__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324Ltimer_set_ti1_ch123_xorRCC_CCIPR_LPTIM1SEL_HSI16 2RCC_CCIPR_TIM1SEL_SHIFT 20TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)TIM_CR1_CMS_EDGE (0x0 << 5)PWR_CR2_PVDFT_SHIFT 1TIM13_CCMR1 TIM_CCMR1(TIM13)UINT_LEAST32_MAXTIM_SMCR_TS_ITR3 (0x3 << 4)__ACCUM_MAX__ 0X7FFFFFFFP-15K__DBL_HAS_QUIET_NAN__ 1RCC_CIFR_LSECSSF (1 << 9)__ARM_PCS 1RCC_CCIPR MMIO32(RCC_BASE + 0x54)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intTIM_CR1_DIR_DOWN (1 << 4)TIM12_CCER TIM_CCER(TIM12)__ARM_NEON__RCC_AHBSMENR_SRAMSMEN (1 << 9)ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))PWR_CR2_PVDFT_2V4 0x02PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)TIM3_CCMR1 TIM_CCMR1(TIM3)TIM17_DCR TIM_DCR(TIM17)INT8_MAXRCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)TIM_SMCR_TS_ITR2 (0x2 << 4)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CFGR_MCO_LSE 0x7TIM8_CCMR2 TIM_CCMR2(TIM8)RCC_CCIPR_RNGDIV_8 3WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)TIM_OC1TIM_OC2TIM_OC3TIM_OC4RCC_APBSMENR1_WWDGSMEN (1 << 11)timer_set_oc_fast_mode__ARM_ARCH_PROFILETIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)TIM_OCM_INACTIVE__LACCUM_IBIT__ 32RCC_CCIPR_LPTIM1SEL_SHIFT 18TIM11_ARR TIM_ARR(TIM11)TIM11_CNT TIM_CNT(TIM11)MMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)TIM_CCMR2_IC3PSC_2 (0x1 << 2)TIM15_SR TIM_SR(TIM15)INT16_MINWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPTIM1SEL_LSI 1TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)__SA_FBIT__ 15RCC_ICSCR_HSITRIM_SHIFT 8TIM5_ARR TIM_ARR(TIM5)__SIZEOF_SHORT__ 2UINTPTR_MAX __UINTPTR_MAX__timer_enable_counterTIM8_DMAR TIM_DMAR(TIM8)timer_set_break_polarity_low__UINT8_MAX__ 0xffRCC_CR_HSIDIV_DIV8 3__ARM_FEATURE_CLZUCPD1_BASE (PERIPH_BASE_APB + 0xA000)TIM_EGR_TG (1 << 6)TIM14_PSC TIM_PSC(TIM14)RCC_CCIPR_USART1SEL_MASK 0x3timer_continuous_modeoutputsPWR_CR2_PVDFT_2V2 0x01TIM13_CR1 TIM_CR1(TIM13)TIM_SMCR_TS_ITR0 (0x0 << 4)TIM_CCMR1_CC1S_OUT (0x0 << 0)TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)TIM3_CCR2 TIM_CCR2(TIM3)TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)TIM_CCMR1_OC1FE (1 << 2)RCC_APBSMENR1_OFFSET 0x4cTIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)TIM_SMCR_SMS_GM (0x5 << 0)timer_enable_oc_clearRCC_APBSMENR2_ADCSMEN (1 << 20)UINT_FAST16_MAX__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEX__UACCUM_MIN__ 0.0UKTIM_CCMR2_OC3M_TOGGLE (0x3 << 4)TIM4_CCR3 TIM_CCR3(TIM4)__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1timer_disable_update_eventTIM11_CR1 TIM_CR1(TIM11)__INT_LEAST16_TYPE__ short intRCC_CFGR_SWS_PLLRCLK 0x2TIM_CCMR1_CC1S_MASK (0x3 << 0)END_DECLS TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)INT32_MAX __INT32_MAX__TIM13_DIER TIM_DIER(TIM13)__USFRACT_FBIT__ 8__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1__USACCUM_MIN__ 0.0UHK__LLFRACT_FBIT__ 63RCC_APBENR1_TIM2EN (1 << 0)TIM16_BDTR TIM_BDTR(TIM16)__SIZEOF_PTRDIFF_T__ 4TIM1_DIER TIM_DIER(TIM1)PWR_CR2_PVDRT_PVD_IN 0x07__DA_IBIT__ 32TIM7 TIM7_BASEDEBUG_BASE (SCS_BASE + 0x0DF0)PWR_CR3_EWUP1 (1 << 0)PWR_CR3_EWUP2 (1 << 1)RCC_CCIPR_TIM1SEL_TIMPCLK 0RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"timer_set_deadtimeRCC_IOPENR_OFFSET 0x34__DBL_MIN_EXP__ (-1021)TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C)TIM_SMCR_TS_TI1FP1 (0x5 << 4)TIM7_SR TIM_SR(TIM7)RCC_APBRSTR1_TIM2RST (1 << 0)USART3_BASE (PERIPH_BASE_APB + 0x4800)MPU_BASE (SCS_BASE + 0x0D90)PWR_CR1_LPMS_SHUTDOWN 4TIM_CR2_TI1S (1 << 7)UINT16_MAXINT_LEAST16_MINTIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)__LDBL_MAX_10_EXP__ 308RCC_CIER_LSERDYIE (1 << 1)TIM3_CCR1 TIM_CCR1(TIM3)RCC_APBSMENR1_TIM7SMEN (1 << 5)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)TIM_CCMR1_OC2PE (1 << 11)TIM8_DCR TIM_DCR(TIM8)WWDG_BASE (PERIPH_BASE_APB + 0x2c00)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)TIM_CCMR1_IC1F_OFF (0x0 << 4)__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)bool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_AHBENR_AESEN (1 << 16)RCC_ICSCR_HSITRIM_MASK 0x1fTIM_SMCR_ETF_OFF (0x0 << 8)__UINT_LEAST32_TYPE__ long unsigned inttimer_disable_preload_complementry_enable_bitsTIM_CCMR2_IC4F_OFF (0x0 << 12)TIM_SMCR_SMS_EM1 (0x1 << 0)INT32_MIN__HA_IBIT__ 8TIM_IC_PSC_2TIM_CR1_CMS_CENTER_3 (0x3 << 5)TIM_CCMR2_OC3PE (1 << 3)PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)TIM_IC_PSC_8INT8_MIN (-INT8_MAX - 1)TIM16_RCR TIM_RCR(TIM16)INT16_CTIM_DIER_COMDE (1 << 13)__FLT32_HAS_QUIET_NAN__ 1RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0TIM6_BASE (PERIPH_BASE_APB + 0x1000)long long intRCC_APBRSTR2_TIM15RST (1 << 16)__FLT_EVAL_METHOD__ 0RCC_CIFR_LSERDYF (1 << 1)RCC_IOPRSTR_OFFSET 0x24GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)TIM2_CR1 TIM_CR1(TIM2)RCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)__UHA_FBIT__ 8timer_reset_output_idle_stateTIM_CR1_CMS_CENTER_2 (0x2 << 5)RCC_CCIPR_RNGSEL_SHIFT 26ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))TIM6_CNT TIM_CNT(TIM6)timer_disable_oc_clearRCC_CR_HSIDIV_DIV128 7TIM6_DIER TIM_DIER(TIM6)SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)TIM_CCMR1_CC2S_OUT (0x0 << 8)TIM8_CCR3 TIM_CCR3(TIM8)__FDPIC__RCC_APBRSTR2_SPI1RST (1 << 12)CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffPWR_CR1_FPD_LPSLP (1 << 5)__ARM_ARCH 6RCC_CR_HSION (1 << 8)RCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)RCC_CCIPR_LPTIM2SEL_HSI16 2RCC_APBRSTR2_ADCRST (1 << 20)tim_oc_idTIM_CCER_CC3NE (1 << 10)TIM11_EGR TIM_EGR(TIM11)RCC_CCIPR_I2S1SEL_SHIFT 14TIM1_SMCR TIM_SMCR(TIM1)__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3BIT6 (1<<6)PWR_CR2_PVDRT_MASK 0x07RCC_AHBSMENR_OFFSET 0x48RCC_AHBSMENR_DMASMEN (1 << 0)__ARM_ARCH_6M__ 1PWR_SCR_CSBF (1 << 8)__USFRACT_IBIT__ 0TIM6_SR TIM_SR(TIM6)__FLT32X_MIN_10_EXP__ (-307)WINT_MAXtimer_enable_update_eventRCC_CFGR_HPRE_MASK 0xf__DEC_EVAL_METHOD__ 2TIM3_CR2 TIM_CR2(TIM3)INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)long unsigned intRCC_CFGR_PPRE_DIV2 0x4TIM8_PSC TIM_PSC(TIM8)TIM3_TISEL TIM_TISEL(TIM3)__SFRACT_MAX__ 0X7FP-7HRTIM_OC1NTIM15_ARR TIM_ARR(TIM15)TIM15_CCER TIM_CCER(TIM15)TIM15_CNT TIM_CNT(TIM15)TIM_DIER_CC2DE (1 << 10)TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)RCC_CFGR_MCOPRE_DIV32 5RCC_CFGR_SW_MASK 0x3TIM_CCER_CC3E (1 << 8)TIM_SR_BIF (1 << 7)__SIZEOF_LONG_DOUBLE__ 8__FLT64_HAS_DENORM__ 1TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__FLT_HAS_DENORM__ 1__LLACCUM_FBIT__ 31UINT_LEAST8_MAX__THUMBEL__ 1TIM_DIER_CC1IE (1 << 1)RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_SHIFT 29__GCC_CONSTRUCTIVE_SIZE 64TIM3_DCR TIM_DCR(TIM3)timer_direction_upTIM16_CCMR1 TIM_CCMR1(TIM16)TIM16_CR2 TIM_CR2(TIM16)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0TIM16_DIER TIM_DIER(TIM16)TIM11_PSC TIM_PSC(TIM11)__FLT32X_MIN__ 2.2250738585072014e-308F32xTIM17_CR1 TIM_CR1(TIM17)TIM_SR_COMIF (1 << 5)__SIZEOF_FLOAT__ 4TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)RCC_APBENR1_USART4EN (1 << 19)TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)TIM2_DMAR TIM_DMAR(TIM2)__UINT_LEAST8_TYPE__ unsigned chartimer_update_on_overflowUINT16_CTIM4_DMAR TIM_DMAR(TIM4)TIM14 TIM14_BASE__ARM_NEON_FPTIM_CCMR2_IC3F_OFF (0x0 << 4)TIM_CCER_CC4NP (1 << 15)__UFRACT_FBIT__ 16TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)TIM1_BASE (PERIPH_BASE_APB + 0x12C00)RCC_AHBRSTR_RNGRST (1 << 18)TIM3_CCMR2 TIM_CCMR2(TIM3)TIM15_SMCR TIM_SMCR(TIM15)TIM_OC3NTIM_DIER_UIE (1 << 0)__ARM_FEATURE_MVE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32TAMP_BASE (PERIPH_BASE_APB + 0xB000)PWR_CR2_PVDRT_2V5 0x02TIM9_CCER TIM_CCER(TIM9)RCC_CIER_HSERDYIE (1 << 4)RCC_BDCR_RTCSEL_LSI 2PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROCRCC_APBSMENR1_UCPD1SMEN (1 << 25)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRtimer_set_break_polarity_highTIM_CR1_CMS_MASK (0x3 << 5)timer_ic_enableshort int__UQQ_FBIT__ 8timer_slave_set_modeTIM2_CCR2 TIM_CCR2(TIM2)__GNUC_MINOR__ 2CRC_BASE (PERIPH_BASE_AHB + 0x03000)RCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_CSR_PINRSTF (1 << 26)TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)TIM3_CR1 TIM_CR1(TIM3)INTMAX_MAX __INTMAX_MAX__RCC_CR_HSEON (1 << 16)__INTMAX_TYPE__ long long int__UINT_LEAST16_TYPE__ short unsigned intTIM_DIER_CC4DE (1 << 12)__ULLFRACT_EPSILON__ 0x1P-64ULLRTIM3_BASE (PERIPH_BASE_APB + 0x0400)TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)INT16_MIN (-INT16_MAX - 1)RCC_CCIPR_ADCSEL_SYSCLK 0RCC_CCIPR_CECSEL_MASK 0x1TIM15_CCR2 TIM_CCR2(TIM15)RCC_CCIPR_USART2SEL_HSI16 2TIM7_CNT TIM_CNT(TIM7)TIM7_ARR TIM_ARR(TIM7)RCC_APBSMENR2_SYSCFGSMEN (1 << 0)__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MAX __INT_FAST32_MAX__UINTMAX_MAX __UINTMAX_MAX__UINT8_CINT_FAST64_MIN (-INT_FAST64_MAX - 1)TIM17_AF1 TIM_AF1(TIM17)__UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 1__HA_FBIT__ 7__UINT32_MAX__ 0xffffffffULRCC_CFGR_HPRE_DIV128 0xdtimer_ic_set_inputTIM_AF1(tim_base) MMIO32((tim_base) + 0x60)TIM13_SR TIM_SR(TIM13)DMA1_BASE (PERIPH_BASE_AHB + 0x00000)TIM_OCM_PWM1TIM_OCM_PWM2TIM_CCMR1_OC2FE (1 << 10)__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205 |     A         :B@B:B@BB:B@BHB>B>BHB:BTB&B       A   XBXB h       A+aeabi!6S-M M     !!""##$$%%&&''(())**++,,--..//00111333<3555777<799949<99999:9B9x9;;;===<=???<?AAACCCEEE<EGGGIII8IKKKMMNN NOOPP PQQRR RSSTT TUUVV VWWXX XYYZZ\\]]^^____T_aaaaTaccdcddeefffggghhhiijjkmnprt1133557799;;==??AACCEEGGIIKKvxz|~Ar:n      5FXo~      2 H \ u    ! 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( %; !"( . / 0"  !" !!!" !!"! !!!" !!! /! / #!/K $0 =! /! /! /! /! /! /! /! /! /! /! /! /! /! /RCC_CCIPR_RNGDIV_2 1RCC_CICR_PLLRDYC (1 << 5)USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)baudRCC_AHBSMENR_DMASMEN (1 << 0)SCB_BASE (SCS_BASE + 0x0D00)RCC_CCIPR_LPTIM1SEL_MASK 0x3__UHA_FBIT__ 8RCC_APBRSTR1_TIM3RST (1 << 1)usart_set_parityPERIPH_BASE_APB (PERIPH_BASE + 0x00000)PWR_SR1_WUF1 (1 << 0)GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__INTMAX_C(c) c ## LL__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)USART4_CR2 USART_CR2(USART4_BASE)PWR_CR3_RRS (1 << 8)__CHAR_UNSIGNED__ 1USART_CR3_DEP (1 << 15)STM32G0 1USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT)PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)RCC_CCIPR_RNGSEL_SYSCLK 2RCC_CICR_LSECSSC (1 << 9)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffUSART_CR1_DEDT_VAL(x) ((x) << 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unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32USART_ISR_LBDF (1 << 8)RCC_APBRSTR1_PWRRST (1 << 28)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9RCC_AHBRSTR_CRCRST (1 << 12)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)PWR_CR1_FPD_LPSLP (1 << 5)__UINT8_C(c) c__INT16_TYPE__ short intUSART_STOPBITS_1 USART_CR2_STOPBITS_1__FLT64_MAX__ 1.7976931348623157e+308F64RCC_CFGR_MCOPRE_DIV32 5UINT_FAST32_MAXUSART_GTPR_GT_SHIFT 8RCC_CFGR_MCO_HSE 0x4PWR_CR3_EIWUL (1 << 15)USART_GTPR_PSC_SHIFT 0RCC_CIER_LSIRDYIE (1 << 0)USART1_RTOR USART_RTOR(USART1_BASE)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)RCC_PLLCFGR_PLLSRC_NONE 0INT_FAST64_MAX __INT_FAST64_MAX__USART_CR3_IRLP (1 << 2)usart_enable_idle_interruptusart_sendUSART_ICR_EOBCF (1 << 12)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_RNGSEL_HSI16 1USART_CR3_DDRE (1 << 13)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intUSART3_CR2 USART_CR2(USART3_BASE)RCC_APBSMENR1_OFFSET 0x4cUSART_CR1_M USART_CR1_M0usart_disable_rx_interruptINT32_MIN (-INT32_MAX - 1)RCC_CCIPR_RNGSEL_NONE 0__FLT32_MAX_10_EXP__ 38USART_CR2_ADDM7 (1 << 4)RCC_CFGR_HPRE_DIV8 0xaPWR_SCR_CWUF1 (1 << 0)PWR_SR2_REGLPF (1 << 9)RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHR__ARM_FEATURE_CLZUSART_CR1_PS (1 << 9)__UINTPTR_MAX__ 0xffffffffUUSART_CR3_SCARCNT_SHIFT 17__FLT32_MIN_EXP__ (-125)usart_disable_tx_dmaST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8))USART3_BRR USART_BRR(USART3_BASE)USART4_ISR USART_ISR(USART4_BASE)PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12TIM3_BASE (PERIPH_BASE_APB + 0x0400)PWR_CR2_PVDRT_SHIFT 4PWR_CR3_EWUP5 (1 << 4)USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)__WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32PWR_SR1_WUF5 (1 << 4)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_PLLCFGR_PLLSRC_MASK 0x3RCC_BDCR_RTCSEL_HSE_DIV32 3RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRUSART_CR2_STOPBITS_MASK (0x03 << 12)USART_CR2_ABRMOD_FRAME_0x7F (0x2 << USART_CR2_ABRMOD_SHIFT)RCC_IOPSMENR_OFFSET 0x44__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXUSART_CR2_SWAP (1 << 15)__UINTPTR_TYPE__ unsigned int__SQ_FBIT__ 31RCC_CCIPR_TIM15SEL_PLLQCLK 1RCC_APBSMENR1_USART2SMEN (1 << 17)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)__UHQ_FBIT__ 16RCC_AHBSMENR_FLASHSMEN (1 << 8)USART_CR1_DEDT_SHIFT 16__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32INT_FAST8_MAXDMA1_BASE (PERIPH_BASE_AHB + 0x00000)__UINT_FAST8_MAX__ 0xffffffffURCC_APBENR1_LPTIM1EN (1 << 31)USART4 USART4_BASEPWR_SR2_VOSF (1 << 10)UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLP_DIV(x) ((x)-1)__LACCUM_IBIT__ 32PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)RCC_APBSMENR1_SPI2SMEN (1 << 14)PWR_SCR_CWUF2 (1 << 1)RCC_CCIPR_LPTIM2SEL_HSI16 2__INT_FAST16_WIDTH__ 32RCC_APBRSTR2_TIM16RST (1 << 17)INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffPWR_SR2_PVDO (1 << 11)__UINT_FAST16_MAX__ 0xffffffffULPUART1_BASE (PERIPH_BASE_APB + 0x8000)RCC_CR_HSIDIV_SHIFT 11USART_STOPBITS_2 USART_CR2_STOPBITS_2RCC_CCIPR_USART1SEL_SHIFT 0RCC_APBRSTR2_ADCRST (1 << 20)RCC_APBSMENR2_SPI1SMEN (1 << 12)__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URRCC_APBSMENR1_RTCAPBSMEN (1 << 10)USART_CR2_STOPBITS_1 (0x00 << 12)RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APBSMENR1_LPTIM1SMEN (1 << 31)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__AES_BASE (PERIPH_BASE_AHB + 0x06000)PWR_CR4_WP4 (1 << 3)USART_ICR_WUCF (1 << 20)USART_CR3_DMAT (1 << 7)__UINT_LEAST8_TYPE__ unsigned charPWR_CR2_PVDRT_MASK 0x07RCC_APBRSTR2_TIM17RST (1 << 18)__ACCUM_FBIT__ 15USART3 USART3_BASEUSART1_CR1 USART_CR1(USART1_BASE)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__RCC_APBENR1_TIM3EN (1 << 1)PWR_CR2_PVDRT_2V2 0x01__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_CCIPR_LPUART1SEL_HSI16 2RCC_APBSMENR1_LPTIM2SMEN (1 << 30)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32LIBOPENCM3_USART_COMMON_ALL_H __USACCUM_EPSILON__ 0x1P-8UHK__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charPWR_CR4_WP6 (1 << 5)__GCC_ATOMIC_BOOL_LOCK_FREE 1PWR_CR2_PVDFT_2V4 0x02RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RCC_CFGR_PPRE_MASK 0x7__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__usart_enable_tx_complete_interrupt__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_PLLCFGR_PLLREN (1<<28)GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000)USART1_CR2 USART_CR2(USART1_BASE)short unsigned intusart_enable_rx_interruptPWR_CR4_WP1 (1 << 0)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)usart_set_baudrateRCC_CCIPR_I2S1SEL_HSI16 2UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICUSART_ISR(usart_base) MMIO32((usart_base) + 0x1C)LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CCIPR_LPTIM2SEL_MASK 0x3USART2_BASE (PERIPH_BASE_APB + 0x4400)__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__RCC_CFGR_SW_HSISYS 0x0USART_CR2_STOPBITS_2 (0x02 << 12)USART_CR2_ABREN (1 << 20)USART_MODE_TX USART_CR1_TEPWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)RCC_CCIPR_RNGDIV_1 0USART_CR2_CPHA (1 << 9)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32USART_PARITY_EVEN USART_CR1_PCE__FLT32X_MIN_EXP__ (-1021)RCC_AHBRSTR_OFFSET 0x28RCC_APBENR1_UCPD2EN (1 << 26)RCC_APBSMENR1_UCPD1SMEN (1 << 25)RCC_CCIPR_I2C1SEL_SYSCLK 1TIM17_BASE (PERIPH_BASE_APB + 0x14800)USART_ISR_RWU (1 << 19)RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_APBRSTR1_SPI2RST (1 << 14)BIT27 (1<<27)RCC_APBENR1_SPI2EN (1 << 14)TIM7_BASE (PERIPH_BASE_APB + 0x1400)RCC_CR_HSIDIV_DIV1 0RCC_APBRSTR1_LPTIM2RST (1 << 30)RCC_CCIPR_USART2SEL_SHIFT 2USART_CR1_TCIE (1 << 6)__UTA_FBIT__ 64usartRCC_APBENR1_UCPD1EN (1 << 25)__FLT_DECIMAL_DIG__ 9PWR_CR2_PVDRT_3V0 0x06__thumb__ 1RCC_CFGR_MCO_SYSCLK 0x1LIBOPENCM3_MEMORYMAP_COMMON_H signed charRCC_CR_HSIDIV_DIV128 7RCC_APBSMENR2_TIM14SMEN (1 << 15)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)PWR_SR1_WUF6 (1 << 5)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1usart_recv__FRACT_FBIT__ 15RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1RCC_APBRSTR1_I2C2RST (1 << 22)PTRDIFF_MINRCC_CFGR_MCO_NOCLK 0x0__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77RCC_CCIPR_CECSEL_MASK 0x1RCC_APBENR1_PWREN (1 << 28)RCC_CFGR_PPRE_DIV16 0x7PWR_CR4_WP5 (1 << 4)RCC_CFGR_PPRE_DIV8 0x6__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_ICSCR_HSITRIM_MASK 0x1fRCC_APBENR1_TIM2EN (1 << 0)__UINT_FAST32_TYPE__ unsigned int__aeabi_uidivEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RCC_APBSMENR2_TIM15SMEN (1 << 16)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3INT_LEAST32_MAX __INT_LEAST32_MAX__VREFBUF_BASE (PERIPH_BASE_APB + 0x10030)RCC_AHBENR_DMAEN (1 << 0)USART_ICR_IDLECF (1 << 4)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5PWR_CR1_LPMS_MASK 0x07__ARM_ARCH_EXT_IDIV__RCC_CIER_PLLRDYIE (1 << 5)USART_CR3_SCARCNT_MASK 0x7__FLT32X_IS_IEC_60559__ 2ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA))PWR_CR3_EWUP4 (1 << 3)USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)USART2_CR3 USART_CR3(USART2_BASE)RCC_APBRSTR1_OFFSET 0x2cRCC_APBENR1_LPTIM2EN (1 << 30)RCC_CSR_LSION (1 << 0)__UINT16_MAX__ 0xffffUSART_CR2_RXINV (1 << 16)__TQ_FBIT__ 127RCC_APBENR2_TIM14EN (1 << 15)usart_set_stopbitsUSART_CR3_WUFIE (1 << 22)TIM14_BASE (PERIPH_BASE_APB + 0x2000)__USQ_FBIT__ 32USART_CR1(usart_base) MMIO32((usart_base) + 0x00)RCC_CCIPR_USART1SEL_SYSCLK 1uint16_tRCC_CCIPR_RNGDIV_8 3USART_ISR_CTSIF (1 << 9)USART_RQR(usart_base) MMIO32((usart_base) + 0x18)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32USART_ISR_CMF (1 << 17)PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)RCC_CR_HSIDIV_DIV64 6SPI1_BASE (PERIPH_BASE_APB + 0x13000)INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xfCEC_BASE (PERIPH_BASE_APB + 0x7800)PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)PWR_CR2_PVDRT_2V6 0x03UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8USART_ISR_RXNE (1 << 5)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__USART4_BRR USART_BRR(USART4_BASE)USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)__USA_IBIT__ 16RCC_CFGR_SW_LSE 0x4PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)UCPD2_BASE (PERIPH_BASE_APB + 0xA400)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)RCC_APBENR1_TIM6EN (1 << 4)__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)RCC_CFGR_SWS_PLLRCLK 0x2__FLT_MIN__ 1.1754943508222875e-38Fusart_set_flow_control__HA_FBIT__ 7RCC_APBRSTR2_TIM1RST (1 << 11)__FDPIC__PWR_CR1_VOS_RANGE_1 1__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2RCC_CSR_LPWRRSTF (1 << 31)USART_CR3_WUS_START_BIT (0x2 << 20)RCC_IOPENR_OFFSET 0x34RCC_CSR_PINRSTF (1 << 26)INT_FAST64_MINRCC_APBRSTR1_TIM7RST (1 << 5)__USFRACT_IBIT__ 0RCC_CFGR_SWS_SHIFT 3__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CR_HSIDIV_MASK 0x7USART_CR2(usart_base) MMIO32((usart_base) + 0x04)USART_CR3_SCEN (1 << 5)__USFRACT_MIN__ 0.0UHRRCC_CCIPR_I2C1SEL_MASK 0x3BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)__ARM_NEONPWR_SCR_CSBF (1 << 8)__UINT8_MAX__ 0xffRCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_AHBENR_CRCEN (1 << 12)USART3_CR3 USART_CR3(USART3_BASE)__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H PWR_CR2_PVDRT_2V5 0x02USART_FLAG_ORE USART_ISR_OREUSART1_ICR USART_ICR(USART1_BASE)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_CCIPR_LPTIM2SEL_PCLK 0USART_FLAG_TC USART_ISR_TCRCC_APBSMENR1_CECSMEN (1 << 24)RCC_CIER_HSERDYIE (1 << 4)RCC_APBENR1_I2C1EN (1 << 21)USART1_BRR USART_BRR(USART1_BASE)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3USART_ISR_ABRE (1 << 14)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LUSART_FLAG_PE USART_ISR_PEusart_disable_tx_complete_interruptRCC_CIFR_HSIRDYF (1 << 3)usart_enableRCC_CCIPR_LPTIM2SEL_LSI 1RCC_ICSCR_HSICAL_SHIFT 0COMP_BASE (PERIPH_BASE_APB + 0x10200)RCC_APBENR1_OFFSET 0x3cINT_LEAST8_MAX __INT_LEAST8_MAX__USART_FLAG_NF USART_ISR_NFPWR_SCR_CWUF6 (1 << 5)RCC_PLLCFGR_PLLR_SHIFT 29USART3_BASE (PERIPH_BASE_APB + 0x4800)USART_CR2_CLKEN (1 << 11)RCC_APBSMENR2_TIM17SMEN (1 << 18)RCC_APBENR2_SPI1EN (1 << 12)__UACCUM_MIN__ 0.0UKRCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)__FLT_EPSILON__ 1.1920928955078125e-7FUSART_CR1_RTOIE (1 << 26)USART_ISR_ABRF (1 << 15)RCC_PLLCFGR_PLLSRC_SHIFT 0RCC_CCIPR_I2S1SEL_SYSCLK 0USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)PWR_CR2_PVDFT_MASK 0x07RCC_PLLCFGR_PLLP_MASK 0x1f__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_APBRSTR1_UCPD1RST (1 << 25)RCC_CSR MMIO32(RCC_BASE + 0x60)__ARM_FEATURE_MATMUL_INT8USART_ISR_REACK (1 << 22)PWR_CR1_LPR (1 << 14)__GCC_ATOMIC_SHORT_LOCK_FREE 1false 0RCC_PLLCFGR_PLLPEN (1 << 16)DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)__USACCUM_FBIT__ 8usart_recv_blocking__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CCIPR_LPTIM1SEL_HSI16 2USART_ICR_RTOCF (1 << 11)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)TIM16_BASE (PERIPH_BASE_APB + 0x14400)RCC_CICR_LSERDYC (1 << 1)__FLT32_HAS_QUIET_NAN__ 1RCC_APBRSTR1_UCPD2RST (1 << 26)USART_CR1_RE (1 << 2)RCC_CSR_OBLRSTF (1 << 25)USART_ISR_TXE (1 << 7)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308RCC_APBENR2_TIM1EN (1 << 11)USART_ISR_TC (1 << 6)__ARM_PCS 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_APBENR2_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__PWR_CR2_PVDFT_SHIFT 1__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)USART_CR1_MME (1 << 13)USART_CR2_ABRMOD_FRAME_0x55 (0x3 << USART_CR2_ABRMOD_SHIFT)INT16_MAX __INT16_MAX__RCC_APBSMENR2_TIM16SMEN (1 << 17)USART_CR3_DEM (1 << 14)RCC_CFGR_MCO_PLLRCLK 0x5SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080)PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)RCC_CIER MMIO32(RCC_BASE + 0x18)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)__DEC_EVAL_METHOD__ 2RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLPWR_CR2_PVDFT_2V6 0x04RCC_BDCR_LSERDY (1 << 1)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APBSMENR1_USART3SMEN (1 << 18)RCC_APBENR2_TIM17EN (1 << 18)USART1_RDR USART_RDR(USART1_BASE)__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APBENR1_USART4EN (1 << 19)USART1 USART1_BASEPWR_CR2_PVDFT_2V9 0x06PWR_CR1_VOS_MASK 0x3USART_CR3_WUS_ADDRMATCH (0x0 << 20)USART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT)PWR_CR3_APC (1 << 10)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULRCC_PLLCFGR_PLLM_DIV(x) ((x)-1)RCC_CFGR_HPRE_DIV16 0xbflowcontrol__INT_LEAST8_MAX__ 0x7fRCC_AHBSMENR_AESSMEN (1 << 16)RCC_CICR MMIO32(RCC_BASE + 0x20)__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_BASE (PERIPH_BASE_APB + 0x7400)USART_CR3_WUS_RXNE (0x3 << 20)PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)RCC_PLLCFGR_PLLP_SHIFT 17RCC_ICSCR_HSICAL_MASK 0xff__aeabi_uidivmod__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_BDCR_LSEON (1 << 0)RCC_CCIPR_ADCSEL_PLLPCLK 1__UINT_LEAST32_MAX__ 0xffffffffULRCC_APBRSTR2_TIM14RST (1 << 15)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fPWR_CR1_VOS_RANGE_2 2BIT14 (1<<14)RCC_ICSCR_HSITRIM_SHIFT 8__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVEUSART_ICR_LBDCF (1 << 8)USART_CR2_LBDIE (1 << 6)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intUSART_CR2_CPOL (1 << 10)USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT)PWR_SR2_FLASHRDY (1 << 8)__SOFTFP__ 1PWR_CR2_PVDFT_2V2 0x01UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINRCC_CFGR_MCOPRE_DIV16 4__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8rcc_apb2_frequency rcc_apb1_frequencyBIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned intUSART_RQR_RXFRQ (1 << 3)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RRCC_CFGR_PPRE_SHIFT 12BIT24 (1<<24)RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)__INT32_MAX__ 0x7fffffffL__INT64_C(c) c ## LLRCC_PLLCFGR_PLLR_MASK 0x7RCC_CICR_LSIRDYC (1 << 0)RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_CCIPR_TIM15SEL_TIMPCLK 0LIBOPENCM3_RCC_H PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__PWR_CR4_VBE (1 << 8)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1/build/libopencm3/lib/stm32/g0__DBL_MAX_EXP__ 1024UCPD1_BASE (PERIPH_BASE_APB + 0xA000)__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_APBRSTR2_USART1RST (1 << 14)clockRCC_CR_HSION (1 << 8)__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)RCC_CFGR_SWS_HSISYS 0x0RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CCIPR_RNGSEL_SHIFT 26__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_CECSEL_LSE 1UINTPTR_MAXPWR_CR1_LPMS_STOP_0 0__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLLUSART_CR3_DMAR (1 << 6)__ULLFRACT_IBIT__ 0USART_CR1_WAKE (1 << 11)USART_FLAG_FE USART_ISR_FE__INTMAX_WIDTH__ 64MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APBSMENR2_TIM1SMEN (1 << 11)RCC_APBENR1_DBGEN (1 << 27)USART_FLOWCONTROL_NONE 0x00RCC_APBSMENR1_TIM3SMEN (1 << 1)USART_RDR(usart_base) MMIO32((usart_base) + 0x24)USART_CR3_OVRDIS (1 << 12)__GNUC__ 12RCC_BDCR_LSCOSEL (1 << 25)RCC_CR_HSIDIV_DIV2 1WCHAR_MAXRCC_APBSMENR1_I2C1SMEN (1 << 21)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CFGR_SWS_MASK 0x3USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUSART_CR2_LINEN (1 << 14)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1__ULACCUM_MIN__ 0.0ULKRCC_APBENR2_SYSCFGEN (1 << 0)RCC_APBENR2_ADCEN (1 << 20)__INT_MAX__ 0x7fffffffRCC_CFGR_SW_MASK 0x3RCC_CCIPR_CECSEL_SHIFT 6RCC_PLLCFGR_PLLQ_SHIFT 25__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXrcc_apb1_frequency__LDBL_HAS_QUIET_NAN__ 1RCC_APBSMENR1_DAC1SMEN (1 << 29)RCC_APBSMENR2_OFFSET 0x50__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_CFGR_MCOPRE_DIV64 6TAMP_BASE (PERIPH_BASE_APB + 0xB000)RCC_CFGR_MCOPRE_SHIFT 28PWR_CR2_PVDRT_2V7 0x04__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FPRCC_CCIPR_RNGDIV_MASK 0x3__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7CRC_BASE (PERIPH_BASE_AHB + 0x03000)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024PWR_SR1_WUFI (1 << 15)UINT16_MAXRCC_AHBRSTR_FLASHRST (1 << 8)__FLT64_MIN__ 2.2250738585072014e-308F64GNU C99 12.2.1 20221205 -mcpu=cortex-m0plus -mthumb -mfloat-abi=soft -march=armv6s-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsUSART_CR1_CMIE (1 << 14)PWR_CR1_LPMS_STANDBY 3RCC_APBRSTR1_TIM2RST (1 << 0)RCC_CCIPR_USART1SEL_MASK 0x3__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA))LIBOPENCM3_PWR_H USART_ISR_NF (1 << 2)RCC_CCIPR MMIO32(RCC_BASE + 0x54)USART_ICR_NCF (1 << 2)RCC_BDCR_RTCEN (1 << 15)__UFRACT_MAX__ 0XFFFFP-16URUSART_CR3_HDSEL (1 << 3)RCC_CCIPR_CECSEL_HSI16 0usart_disable_rx_dmaINT64_MAXPWR_CR2_PVDRT_2V1 0x00PWR_CR3_EWUP2 (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2../common/usart_common_all.cUSART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5USART_CR1_UE (1 << 0)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RCC_APBSMENR1_LPUART1SMEN (1 << 20)RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1)USART_CR3_EIE (1 << 0)SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CCIPR_I2S1SEL_MASK 0x3RCC_CCIPR_I2C1SEL_HSI16 2RCC_PLLCFGR_PLLSRC_HSI16 2USART_FLAG_TXE USART_ISR_TXE__ARM_32BIT_STATE__UFRACT_FBIT__ 16usart_enable_tx_dma__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_AHBSMENR_OFFSET 0x48SPI2_BASE (PERIPH_BASE_APB + 0x3800)RCC_APBENR1_DAC1EN (1 << 29)LPUART1 LPUART1_BASEUSART_RQR_MMRQ (1 << 2)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)RCC_APBSMENR1_DBGSMEN (1 << 27)unsigned int__GCC_ASM_FLAG_OUTPUTS__USART_CR2_LBCL (1 << 8)RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)_REG_BIT(offset,bit) (((offset) << 5) + (bit))__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1USART_FLAG_RXNE USART_ISR_RXNERCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)USART2_CR1 USART_CR1(USART2_BASE)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8RCC_CSR_PWRRSTF (1 << 27)USART_ISR_RTOF (1 << 11)ADC1_BASE (PERIPH_BASE_APB + 0x12400)RCC_APBSMENR1_I2C2SMEN (1 << 22)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKPWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)RCC_APBRSTR1_I2C1RST (1 << 21)USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT)__FLT_EVAL_METHOD__ 0USART_CR2_ABRMOD_MASK 3__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__RCC_CSR_RMVF (1 << 23)LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXRCC_CCIPR_RNGSEL_MASK 0x3USART_RQR_TXFRQ (1 << 4)__UQQ_FBIT__ 8USART_TDR_MASK (0x1FF << 0)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4bits__STDC__ 1RCC_CFGR_PPRE_NODIV 0x0RCC_APBSMENR1_TIM7SMEN (1 << 5)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned charPWR_CR2_PVDFT_2V5 0x03RCC_CCIPR_USART1SEL_HSI16 2PWR_CR1_LPMS_SHUTDOWN 4__SIG_ATOMIC_TYPE__ intUSART4_CR3 USART_CR3(USART4_BASE)RCC_APBRSTR1_LPTIM1RST (1 << 31)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"RCC_CR_HSIRDY (1 << 10)INT8_MINRCC_PLLCFGR_PLLM_SHIFT 0x4RCC_CCIPR_LPUART1SEL_MASK 0x3RCC_APBENR2_USART1EN (1 << 14)PERIPH_BASE (0x40000000U)true 1USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)USART_ISR_TEACK (1 << 21)RCC_APBRSTR1_DBGRST (1 << 27)RCC_CSR_IWDGRSTF (1 << 29)__LDBL_MIN_10_EXP__ (-307)RCC_AHBSMENR_SRAMSMEN (1 << 9)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CR_CSSON (1 << 19)USART_CR1_OVER8 (1 << 15)__LFRACT_EPSILON__ 0x1P-31LRRCC_CIFR_HSERDYF (1 << 4)USART_CR1_M1 (1 << 28)RCC_CCIPR_I2S1SEL_SHIFT 14RCC_PLLCFGR_PLLQ_MASK 0x7__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__unsigned char__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xUSART3_CR1 USART_CR1(USART3_BASE)__arm__ 1usart_disable_tx_interruptRCC_CR_HSIDIV_DIV16 4USART2_RQR USART_RQR(USART2_BASE)USART3_RDR USART_RDR(USART3_BASE)__FLT32_MIN_10_EXP__ (-37)RCC_APBSMENR2_SYSCFGSMEN (1 << 0)INFO_BASE (0x1fff7500U)RCC_APBENR1_TIM7EN (1 << 5)__ARM_FP16_FORMAT_ALTERNATIVEUSART_CR3_RTSE (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308LPWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)INTPTR_MINRCC_AHBRSTR_RNGRST (1 << 18)DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64__ARM_FEATURE_SIMD32RCC_CCIPR_LPTIM1SEL_LSI 1__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_MCOPRE_DIV128 7RCC_APBSMENR2_ADCSMEN (1 << 20)RCC_CFGR_SWS_LSI 0x3__ARM_ARCH_ISA_THUMB 1USART_ISR_SBKF (1 << 18)USART_ICR_FECF (1 << 1)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APBRSTR2_SYSCFGRST (1 << 0)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART_CR2_MSBFIRST (1 << 19)INT64_C(c) __INT64_C(c)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0RCC_AHBENR_FLASHEN (1 << 8)USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)USART_CR1_TE (1 << 3)USART2_ICR USART_ICR(USART2_BASE)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1RCC_APBSMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_I2C1SEL_PCLK 0USART_CR3_CTSE (1 << 9)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)RCC_IOPRSTR_OFFSET 0x24PWR_CR1_LPMS_STOP_1 1USART_CR1_IDLEIE (1 << 4)USART4_CR1 USART_CR1(USART4_BASE)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7RCC_APBSMENR1_TIM2SMEN (1 << 0)INT32_MAXUSART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)RCC_BDCR_BDRST (1 << 16)USART3_RQR USART_RQR(USART3_BASE)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_CFGR_HPRE_MASK 0xfusart_enable_error_interrupt__ARM_FEATURE_CRYPTOUSART_ISR_PE (1 << 0)__INT_LEAST32_TYPE__ long intRCC_CCIPR_LPTIM1SEL_LSE 3RCC_CFGR_HPRE_DIV4 0x9USART_CR1_RXNEIE (1 << 5)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLPWR_CR3_EWUP1 (1 << 0)__FRACT_IBIT__ 0USART2_RDR USART_RDR(USART2_BASE)RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)RCC_CR_HSIDIV_DIV8 3long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)RCC_CFGR_SWS_HSE 0x1__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)__APCS_32__ 1__DQ_FBIT__ 63USART_CR2_STOPBITS_1_5 (0x03 << 12)RCC_CFGR_HPRE_SHIFT 8INT_LEAST64_MAX__SACCUM_IBIT__ 8USART_CR2_STOPBITS_0_5 (0x01 << 12)reg32__UHQ_IBIT__ 0INT_LEAST8_MINUSART_CR2_RTOEN (1 << 23)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_ADCSEL_SYSCLK 0__UINT_LEAST16_TYPE__ short unsigned intUSART_FLAG_IDLE USART_ISR_IDLE__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intusart_disable_error_interrupt__FLT32X_DIG__ 15USART3_ICR USART_ICR(USART3_BASE)USART_ICR_CMCF (1 << 17)PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)__UTQ_FBIT__ 128USART4_GTPR USART_GTPR(USART4_BASE)USART_CR3_ONEBIT (1 << 11)usart_wait_send_ready__FINITE_MATH_ONLY__ 0RCC_CR_HSEBYP (1 << 18)__INT_FAST16_MAX__ 0x7fffffffRCC_AHBENR_AESEN (1 << 16)RCC_BDCR_RTCSEL_MASK 0x3USART_CR1_PEIE (1 << 8)PTRDIFF_MAX __PTRDIFF_MAX__PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)__ARM_ARCH 6USART_CR2_LBDL (1 << 5)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUSART4_RQR USART_RQR(USART4_BASE)RCC_CCIPR_RNGSEL_PLLQCLK 3UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_PLLCFGR_PLLN_MUL(x) (x)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_APBENR2_OFFSET 0x40RCC_CCIPR_LPTIM2SEL_LSE 3USART_ICR_ORECF (1 << 3)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)usart_disable_idle_interruptWCHAR_MINPWR_CR1_FPD_LPRUN (1 << 4)RCC_CCIPR_USART2SEL_MASK 0x3usart_disableRCC_CFGR_SWS_LSE 0x4BEGIN_DECLS USART_ISR_EOBF (1 << 12)PWR_CR2_PVDRT_PVD_IN 0x07GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)USART_CR2_STOPBITS_SHIFT 12USART_ICR_TCCF (1 << 6)RCC_CFGR_SW_PLLRCLK 0x2__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xUSART2_RTOR USART_RTOR(USART2_BASE)USART_ISR_CTS (1 << 10)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1USART_RQR_SBKRQ (1 << 1)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)USART2_TDR USART_TDR(USART2_BASE)__QQ_IBIT__ 0USART_ICR_PECF (1 << 0)RCC_APBRSTR2_SPI1RST (1 << 12)USART_FLOWCONTROL_RTS USART_CR3_RTSEUSART4_ICR USART_ICR(USART4_BASE)RCC_CR_PLLON (1 << 24)PWR_CR2_PVDFT_2V8 0x05RCC_APBENR1_USART2EN (1 << 17)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINUSART_CR1_TXEIE (1 << 7)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1PWR_CR3_ULPEN (1 << 9)RCC_APBRSTR1_USART4RST (1 << 19)RCC_AHBENR_RNGEN (1 << 18)INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)USART_RTOR_RTO_SHIFT 0RCC_CCIPR_LPTIM1SEL_PCLK 0__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_APBRSTR2_OFFSET 0x30USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CRCC_APBSMENR1_PWRSMEN (1 << 28)RCC_CCIPR_TIM1SEL_PLLQCLK 1USART4_RDR USART_RDR(USART4_BASE)USART2 USART2_BASEINT64_MINRCC_BDCR_RTCSEL_NONE 0__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_Cusart_wait_recv_readyMMIO64(addr) (*(volatile uint64_t *)(addr))RCC_CCIPR_TIM1SEL_MASK 0x1UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRUSART1_GTPR USART_GTPR(USART1_BASE)__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)USART4_RTOR USART_RTOR(USART4_BASE)usart_enable_tx_interrupt__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16USART_CR2_DATAINV (1 << 18)CORESIGHT_LAR_OFFSET 0xfb0RCC_CCIPR_TIM15SEL_SHIFT 24USART_ISR_FE (1 << 1)USART3_TDR USART_TDR(USART3_BASE)RCC_CCIPR_RNGDIV_4 2USART_ICR_CTSCF (1 << 9)RCC_CIFR_LSERDYF (1 << 1)RCC_APBRSTR1_DAC1RST (1 << 29)short intRCC_APBRSTR1_TIM6RST (1 << 4)USART_RDR_MASK (0x1FF << 0)PWR_SCR_CWUF4 (1 << 3)__UINT16_C(c) cUSART_BRR(usart_base) MMIO32((usart_base) + 0x0C)__UDA_IBIT__ 32modeUSART_CR1_EOBIE (1 << 27)USART_FLOWCONTROL_CTS USART_CR3_CTSEUINT_LEAST32_MAXRCC_CR_HSIDIV_DIV32 5BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)RCC_BDCR_LSEDRV_LOW 0__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_BDCR_LSEBYP (1 << 2)USART_CR1_M0 (1 << 12)usart_set_databitsBIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1USART_CR3_CTSIE (1 << 10)RCC_APBENR1_LPUART1EN (1 << 20)__DBL_DECIMAL_DIG__ 17RCC_CFGR_SW_LSI 0x3BIT8 (1<<8)USART_CR3_IREN (1 << 1)INT16_C(c) __INT16_C(c)RCC_CCIPR_I2S1SEL_PLLPLCK 1RCC_BDCR_LSEDRV_SHIFT 3RCC_APBSMENR1_TIM6SMEN (1 << 4)RCC_APBSMENR1_UCPD2SMEN (1 << 26)__INT16_MAX__ 0x7fffUSART3_GTPR USART_GTPR(USART3_BASE)RCC_CCIPR_RNGDIV_SHIFT 28USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)USART2_GTPR USART_GTPR(USART2_BASE)__INT_WIDTH__ 32RCC_CCIPR_TIM1SEL_TIMPCLK 0USART_TDR(usart_base) MMIO32((usart_base) + 0x28)PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)PWR_CR1_VOS_SHIFT 9__QQ_FBIT__ 7RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)PWR_SR1_WUF2 (1 << 1)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64USART_MODE_RX USART_CR1_REPWR_CR1_FPD_STOP (1 << 3)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RCC_CCIPR_I2S1SEL_I2S_CKIN 2RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRUSART4_TDR USART_TDR(USART4_BASE)PWR_CR2_PVDFT_2V0 0x00__SIZEOF_WINT_T__ 4USART_ISR_IDLE (1 << 4)PWR_CR1_LPMS_SHIFT 0__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)RCC_CSR_LSIRDY (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RCC_APBENR1_CECEN (1 << 24)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1RCC_APBSMENR1_USART4SMEN (1 << 19)__FLT32X_HAS_DENORM__ 1USART_CR2_ADD_SHIFT 24__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1RCC_BDCR_LSEDRV_HIGH 3RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)USART_CR1_DEAT_SHIFT 21RCC_PLLCFGR_PLLR_DIV(x) ((x)-1)RCC_CR_HSIDIV_DIV4 2RCC_CCIPR_USART2SEL_SYSCLK 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CFGR_MCOPRE_DIV1 0USART_CR3_NACK (1 << 4)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODUSART1_RQR USART_RQR(USART1_BASE)USART1_CR3 USART_CR3(USART1_BASE)RCC_CCIPR_TIM1SEL_SHIFT 20RCC_CFGR_MCOPRE_DIV2 1RCC_APBRSTR1_USART2RST (1 << 17)RCC_APBSMENR2_USART1SMEN (1 << 14)USART1_ISR USART_ISR(USART1_BASE)usart_set_mode__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_CCIPR_USART2SEL_LSE 3USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)RCC_AHBRSTR_AESRST (1 << 16)__GCC_CONSTRUCTIVE_SIZE 64USART_CR3(usart_base) MMIO32((usart_base) + 0x08)__LLFRACT_IBIT__ 0RCC_APBENR1_RTCAPBEN (1 << 10)uint32_tUSART2_CR2 USART_CR2(USART2_BASE)BIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdPWR_SCR_CWUF5 (1 << 4)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CIFR_PLLRDYF (1 << 5)USART_PARITY_NONE 0x00USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)RCC_CFGR_SW_SHIFT 0RCC_APBENR1_USART3EN (1 << 18)RCC_APBRSTR1_LPUART1RST (1 << 20)__UINT_FAST16_TYPE__ unsigned intUSART_CR1_UESM (1 << 1)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)PWR_SR1_WUF4 (1 << 3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKUSART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT)__LDBL_DIG__ 15PWR_CR2_PVDE (1 << 0)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINUSART_ISR_ORE (1 << 3)__FLT64_DIG__ 15RCC_CCIPR_USART2SEL_PCLK 0RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APBENR2_TIM16EN (1 << 17)__INT_LEAST16_TYPE__ short int__ULLACCUM_EPSILON__ 0x1P-32ULLKRCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RCC_CCIPR_TIM15SEL_MASK 0x1UINTMAX_C__LDBL_MAX_10_EXP__ 308stopbitsINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RCC_CFGR MMIO32(RCC_BASE + 0x08)PWR_SR1_SBF (1 << 8)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART3_RTOR USART_RTOR(USART3_BASE)RCC_CCIPR_ADCSEL_SHIFT 30BIT26 (1<<26)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffUUSART_CR2_ABRMOD_SHIFT 21__ARM_FEATURE_SATPWR_CR3_EWUP6 (1 << 5)USART_ICR(usart_base) MMIO32((usart_base) + 0x20)usart_send_blocking__ARM_ARCHRCC_APBENR1_I2C2EN (1 << 22)INTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1RCC_CCIPR_USART2SEL_HSI16 2RCC_APBENR1_WWDGEN (1 << 11)RCC_PLLCFGR_PLLM_MASK 0x7RCC_CCIPR_ADCSEL_HSI16 2RCC_AHBENR_OFFSET 0x38INT_LEAST64_MINPTRDIFF_MAXRCC_AHBSMENR_CRCSMEN (1 << 12)RNG_BASE (PERIPH_BASE_AHB + 0x05000)PWR_CR1_DBP (1 << 8)RCC_PLLCFGR_PLLN_SHIFT 0x8__LLFRACT_EPSILON__ 0x1P-63LLRRCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__RCC_CFGR_MCO_LSI 0x6USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)WINT_MAXRCC_CCIPR_LPUART1SEL_SYSCLK 1__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32USART_CR1_PCE (1 << 10)RCC_APBRSTR1_USART3RST (1 << 18)USART_RTOR_BLEN_SHIFT 24parity__ATOMIC_ACQ_REL 4RCC_CCIPR_LPUART1SEL_PCLK 0__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)PWR_CR4_VBRS (1 << 9)dataRCC_CFGR_MCO_HSI16 0x3RCC_CFGR_MCO_LSE 0x7RCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)RCC_CFGR_PPRE_DIV2 0x4USART_ISR_WUF (1 << 20)USART2_ISR USART_ISR(USART2_BASE)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)RCC_CCIPR_USART1SEL_PCLK 0USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)USART_CR2_TXINV (1 << 17)USART_RQR_ABKRQ (1 << 0)INT_FAST16_MAXUSART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)LIBOPENCM3_USART_H __INT_LEAST64_TYPE__ long long intusart_enable_rx_dmaIWDG_BASE (PERIPH_BASE_APB + 0x3000)RCC_PLLCFGR_PLLQEN (1 << 24)PWR_CR2_PVDRT_2V9 0x05__ARM_FEATURE_CDE_COPROCUSART_ISR_BUSY (1 << 16)PWR_SR2_REGLPS (1 << 8)UINT32_CUSART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)GCC: (15:12.2.rel1-1) 12.2.1 20221205 | DB     AA A+aeabi!6S-M M  8     !!""##$$%%&&''(())**+-.024NP68:<>@BDFHJLRAr:n   A QT    oD   ,@Vau      ! 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H9 7?bS/9Ya >4&TP/`+ \JNEDCh$X[6X";':8 &eHA?RobG+ J27"+K+J"T)] i E.m&!N1IjU/Db@Zy0jQY]rU7+B2X] _`P=FO[(;,8fM&%#;>`pACc"!K:L"G`~$%sWs\C6vREAI#Rx+OLKY6AMR;(')*P*+B ,84 ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/g0../../../include/libopencm3/stm32/commonusart_common_v2.cstdint.husart.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.husart.husart_common_all.husart_common_v2.h)! =8 !/! = !/! = !/! /! /$!/$ !!! = !/! = !/  ! !/,  , /-  - / ! $ =USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)MMIO64(addr) (*(volatile uint64_t *)(addr))SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)USART4_CR2 USART_CR2(USART4_BASE)__CHAR_UNSIGNED__ 1USART_CR3_DEP (1 << 15)STM32G0 1USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ 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2__UINT_FAST64_TYPE__ long long unsigned intGPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)TIM2_BASE (PERIPH_BASE_APB + 0x0000)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2USART_CR3_WUS_START_BIT (0x2 << 20)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LUSART_CR2(usart_base) MMIO32((usart_base) + 0x04)USART_CR3_SCEN (1 << 5)__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xffUSART3_CR3 USART_CR3(USART3_BASE)__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H USART_FLAG_ORE USART_ISR_OREUSART1_ICR USART_ICR(USART1_BASE)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)USART_FLAG_TC USART_ISR_TCUSART1_BRR USART_BRR(USART1_BASE)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffUSART_ISR_ABRE (1 << 14)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LUSART_FLAG_PE USART_ISR_PE__ULLACCUM_EPSILON__ 0x1P-32ULLKCOMP_BASE (PERIPH_BASE_APB + 0x10200)INT_LEAST8_MAX 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-std=c99 -fno-common -ffunction-sections -fdata-sectionsUSART_ISR_NF (1 << 2)USART_ICR_NCF (1 << 2)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5USART_CR1_UE (1 << 0)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__USART_CR3_EIE (1 << 0)SYS_TICK_BASE (SCS_BASE + 0x0010)USART_FLAG_TXE USART_ISR_TXE__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)SPI2_BASE (PERIPH_BASE_APB + 0x3800)LPUART1 LPUART1_BASEUSART_RQR_MMRQ (1 << 2)__INT_FAST32_TYPE__ intUSART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT)unsigned int__GCC_ASM_FLAG_OUTPUTS____LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1USART_FLAG_RXNE USART_ISR_RXNEUSART2_CR1 USART_CR1(USART2_BASE)IOPORT_BASE (0x50000000U)__USACCUM_IBIT__ 8USART_ISR_RTOF (1 << 11)ADC1_BASE (PERIPH_BASE_APB + 0x12400)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKUSART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT)__FLT_EVAL_METHOD__ 0USART_CR2_ABRMOD_MASK 3__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__thumb2__LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00)__ARM_FEATURE_LDREXUSART_RQR_TXFRQ (1 << 4)__UQQ_FBIT__ 8USART_TDR_MASK (0x1FF << 0)INT16_Cflag__ARM_FP16_ARGS__GCC_IEC_559 0DESIG_FLASH_SIZE_BASE (0x1FFF75E0)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__usart_disable_rx_inversion__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__SOFTFP__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RTC_BASE (PERIPH_BASE_APB + 0x2800)__UINT8_TYPE__ unsigned char__SIG_ATOMIC_TYPE__ intUSART4_CR3 USART_CR3(USART4_BASE)usart_disable_rx_timeout__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINPERIPH_BASE (0x40000000U)true 1USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)USART_ISR_TEACK (1 << 21)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1usart_enable_rx_timeoutUSART_CR1_OVER8 (1 << 15)__LFRACT_EPSILON__ 0x1P-31LRUSART_CR1_M1 (1 << 28)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xUSART3_CR1 USART_CR1(USART3_BASE)__arm__ 1USART2_RQR USART_RQR(USART2_BASE)USART3_RDR USART_RDR(USART3_BASE)__FLT32_MIN_10_EXP__ (-37)INFO_BASE (0x1fff7500U)__ARM_FP16_FORMAT_ALTERNATIVEUSART_CR3_RTSE (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)EXTI_BASE (PERIPH_BASE_AHB + 0x01800)__TA_IBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1USART_ISR_SBKF (1 << 18)USART_ICR_FECF (1 << 1)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART_CR2_MSBFIRST (1 << 19)__USQ_IBIT__ 0USART_CR3(usart_base) MMIO32((usart_base) + 0x08)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1LPTIM2_BASE (PERIPH_BASE_APB + 0x9400)USART_CR1_TE (1 << 3)USART2_ICR USART_ICR(USART2_BASE)INT8_MIN (-INT8_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1USART_CR3_CTSE (1 << 9)__FLT32_DIG__ 6INT_LEAST16_MAXTIM6_BASE (PERIPH_BASE_APB + 0x1000)BIT15 (1<<15)USART_CR1_IDLEIE (1 << 4)USART4_CR1 USART_CR1(USART4_BASE)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAXUSART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)USART3_RQR USART_RQR(USART3_BASE)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUSART_ISR_PE (1 << 0)__INT_LEAST32_TYPE__ long intUSART_CR1_RXNEIE (1 << 5)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0USART2_RDR USART_RDR(USART2_BASE)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART1_BASE (PERIPH_BASE_APB + 0x13800)long long unsigned intPERIPH_BASE_AHB (PERIPH_BASE + 0x20000)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intDESIG_UNIQUE_ID_BASE (0x1FFF7590)usart_get_flag__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8usart_disable_halfduplex__UHQ_IBIT__ 0INT_LEAST8_MINUSART_CR2_RTOEN (1 << 23)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intUSART_FLAG_IDLE USART_ISR_IDLE__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15USART3_ICR USART_ICR(USART3_BASE)USART_ICR_CMCF (1 << 17)__UTQ_FBIT__ 128USART4_GTPR USART_GTPR(USART4_BASE)USART_CR3_ONEBIT (1 << 11)usart_wait_send_ready__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffUSART_CR1_PEIE (1 << 8)PTRDIFF_MAX __PTRDIFF_MAX____ARM_ARCH 6USART_CR2_LBDL (1 << 5)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUSART4_RQR USART_RQR(USART4_BASE)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intUSART_ICR_ORECF (1 << 3)GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)WCHAR_MINUSART_CR2_LBCL (1 << 8)BEGIN_DECLS USART_ISR_EOBF (1 << 12)GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)USART_CR2_STOPBITS_SHIFT 12USART_ICR_TCCF (1 << 6)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xUSART2_RTOR USART_RTOR(USART2_BASE)USART_ISR_CTS (1 << 10)UINT_LEAST8_MAX__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1USART_RQR_SBKRQ (1 << 1)DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800)USART2_TDR USART_TDR(USART2_BASE)__QQ_IBIT__ 0USART_ICR_PECF (1 << 0)USART_FLOWCONTROL_RTS USART_CR3_RTSEUSART4_ICR USART_ICR(USART4_BASE)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__GNUC_MINOR__ 2__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINUSART_CR1_TXEIE (1 << 7)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 1INTMAX_MAXDEBUG_BASE (SCS_BASE + 0x0DF0)USART_RTOR_RTO_SHIFT 0__ARM_FEATURE_FP16_SCALAR_ARITHMETICUSART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)__DBL_HAS_QUIET_NAN__ 1BIT9 (1<<9)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CUSART4_RDR USART_RDR(USART4_BASE)USART2 USART2_BASEINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_Cusart_wait_recv_readyUSART_CR1_WAKE (1 << 11)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRUSART1_GTPR USART_GTPR(USART1_BASE)__ARM_ARCH_6M__ 1__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intI2C2_BASE (PERIPH_BASE_APB + 0x5800)USART4_RTOR USART_RTOR(USART4_BASE)__LONG_MAX__ 0x7fffffffLTIM15_BASE (PERIPH_BASE_APB + 0x14000)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16USART_CR2_DATAINV (1 << 18)CORESIGHT_LAR_OFFSET 0xfb0USART_ISR_FE (1 << 1)USART3_TDR USART_TDR(USART3_BASE)USART_ICR_CTSCF (1 << 9)short intUSART_RDR_MASK (0x1FF << 0)usart_disable_rx_timeout_interrupt__UINT16_C(c) cUSART_BRR(usart_base) MMIO32((usart_base) + 0x0C)__UDA_IBIT__ 32USART_CR1_EOBIE (1 << 27)USART_FLOWCONTROL_CTS USART_CR3_CTSEUINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BASE (PERIPH_BASE_AHB + 0x01000)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53USART_CR1_M0 (1 << 12)USART1_CR1 USART_CR1(USART1_BASE)BIT5 (1<<5)BIT1 (1<<1)USART4_BASE (PERIPH_BASE_APB + 0x4C00)INT8_CINT_LEAST32_MAXWWDG_BASE (PERIPH_BASE_APB + 0x2c00)__USES_INITFINI__ 1USART_CR3_CTSIE (1 << 10)__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)USART_CR3_IREN (1 << 1)INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fffUSART3_GTPR USART_GTPR(USART3_BASE)USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)USART2_GTPR USART_GTPR(USART2_BASE)__INT_WIDTH__ 32USART_TDR(usart_base) MMIO32((usart_base) + 0x28)__QQ_FBIT__ 7POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64USART_MODE_RX USART_CR1_RE__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRUSART4_TDR USART_TDR(USART4_BASE)__SIZEOF_WINT_T__ 4USART_ISR_IDLE (1 << 4)__INT_LEAST32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1USART_CR2_ADD_SHIFT 24__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__GCC_ATOMIC_WCHAR_T_LOCK_FREE 1USART_CR1_DEAT_SHIFT 21USART_CR3_NACK (1 << 4)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODUSART1_RQR USART_RQR(USART1_BASE)USART1_CR3 USART_CR3(USART1_BASE)USART1_ISR USART_ISR(USART1_BASE)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H __GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tUSART2_CR2 USART_CR2(USART2_BASE)BIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKUSART_PARITY_NONE 0x00USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)__UINT_FAST16_TYPE__ unsigned intUSART_CR1_UESM (1 << 1)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKUSART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT)__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXLIBOPENCM3_CM3_MEMORYMAP_H BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINUSART_ISR_ORE (1 << 3)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308USART_CR3_HDSEL (1 << 3)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1USART3_RTOR USART_RTOR(USART3_BASE)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffU../common/usart_common_v2.c__ARM_FEATURE_SATUSART_ICR(usart_base) MMIO32((usart_base) + 0x20)__ARM_ARCHINTMAX_C(c) __INTMAX_C(c)__STRICT_ANSI__ 1usart_set_rx_timeout_valueINT_LEAST64_MINPTRDIFF_MAXRNG_BASE (PERIPH_BASE_AHB + 0x05000)__SIZE_TYPE__ unsigned int__LLFRACT_EPSILON__ 0x1P-63LLR__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53__ARM_ASM_SYNTAX_UNIFIED__USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32USART_CR1_PCE (1 << 10)USART_ISR_LBDF (1 << 8)USART_RTOR_BLEN_SHIFT 24USART_CR2_STOPBITS_0_5 (0x01 << 12)__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)dataUSART_ISR_WUF (1 << 20)USART2_ISR USART_ISR(USART2_BASE)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)I2C1_BASE (PERIPH_BASE_APB + 0x5400)UINT64_C(c) __UINT64_C(c)USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53USART_CR2_STOPBITS_1_5 (0x03 << 12)SYSCFG_BASE (PERIPH_BASE_APB + 0x10000)USART_CR2_TXINV (1 << 17)UINT64_MAX __UINT64_MAX__INT_FAST16_MAXusart_enable_data_inversionLIBOPENCM3_USART_H __INT_LEAST64_TYPE__ long long intIWDG_BASE (PERIPH_BASE_APB + 0x3000)__ARM_FEATURE_CDE_COPROCUSART_ISR_BUSY (1 << 16)UINT32_CUSART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)GCC: (15:12.2.rel1-1) 12.2.1 20221205 |         A+aeabi!6S-M M          "#%')?A+-/13579;=C@q9m  BE   .K e    2 Tw  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1)NVIC_SPI1_IRQ 25__SFRACT_MAX__ 0X7FP-7HR__UINT_FAST64_TYPE__ long long unsigned int__preinit_array_enddebug_monitor__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____FLT32_IS_IEC_60559__ 2INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024SCB_ICSR_RETOBASE (1 << 11)__DBL_HAS_DENORM__ 1__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308Lvector_tableINT_LEAST32_MAX __INT_LEAST32_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKhard_faultINT_LEAST8_MAX __INT_LEAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UKSCS_BASE (PPBI_BASE + 0xE000)__init_array_start__DBL_MAX_10_EXP__ 308NVIC_IRQ_COUNT 32__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__GCC_ATOMIC_SHORT_LOCK_FREE 1SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)NVIC_TIM1_BRK_UP_TRG_COM_IRQ 13__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)__FLT32_HAS_QUIET_NAN__ 1SCB_SCR_SLEEPDEEP (1 << 2)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1../../cm3/vector.cbool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____PRAGMA_REDEFINE_EXTNAME 1__FLT32X_IS_IEC_60559__ 2LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16NVIC_RCC_IRQ 4__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRSCB_SCR_SEVONPEND (1 << 4)SCB_ICSR_PENDSTCLR (1 << 25)CORESIGHT_LSR_SLI (1<<0)INT64_MIN__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__IRQ_HANDLERS [NVIC_WWDG_IRQ] = wwdg_isr, [NVIC_PVD_IRQ] = pvd_isr, [NVIC_RTC_IRQ] = rtc_isr, [NVIC_FLASH_IRQ] = flash_isr, [NVIC_RCC_IRQ] = rcc_isr, [NVIC_EXTI0_1_IRQ] = exti0_1_isr, [NVIC_EXTI2_3_IRQ] = exti2_3_isr, [NVIC_EXTI4_15_IRQ] = exti4_15_isr, [NVIC_UCPD1_UCPD2_IRQ] = ucpd1_ucpd2_isr, [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, [NVIC_DMA1_CHANNEL2_3_IRQ] = dma1_channel2_3_isr, [NVIC_DMA1_CHANNEL4_7_DMAMUX_IRQ] = dma1_channel4_7_dmamux_isr, [NVIC_ADC_COMP_IRQ] = adc_comp_isr, [NVIC_TIM1_BRK_UP_TRG_COM_IRQ] = tim1_brk_up_trg_com_isr, [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, [NVIC_TIM2_IRQ] = tim2_isr, [NVIC_TIM3_IRQ] = tim3_isr, [NVIC_TIM6_DAC_LPTIM1_IRQ] = tim6_dac_lptim1_isr, [NVIC_TIM7_LPTIM2_IRQ] = tim7_lptim2_isr, [NVIC_TIM14_IRQ] = tim14_isr, [NVIC_TIM15_IRQ] = tim15_isr, [NVIC_TIM16_IRQ] = tim16_isr, [NVIC_TIM17_IRQ] = tim17_isr, [NVIC_I2C1_IRQ] = i2c1_isr, [NVIC_I2C2_IRQ] = i2c2_isr, [NVIC_SPI1_IRQ] = spi1_isr, [NVIC_SPI2_IRQ] = spi2_isr, [NVIC_USART1_IRQ] = usart1_isr, [NVIC_USART2_IRQ] = usart2_isr, [NVIC_USART3_USART4_LPUART1_IRQ] = usart3_usart4_lpuart1_isr, [NVIC_CEC_IRQ] = cec_isr, [NVIC_AES_RNG_IRQ] = aes_rng_isr__UINT32_MAX__ 0xffffffffULSCB_CCR_UNALIGN_TRP (1 << 3)__INT_LEAST8_MAX__ 0x7f__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12NVIC_TIM7_LPTIM2_IRQ 18NVIC_HARD_FAULT_IRQ -13__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_TIM1_CC_IRQ 14__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned int__SOFTFP__ 1UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RNVIC_EXTI2_3_IRQ 6__UINT_LEAST16_TYPE__ short unsigned int__INT32_MAX__ 0x7fffffffLSCB_ICSR_NMIPENDSET (1 << 31)__ARM_PCS 1UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT32_MANT_DIG__ 24LIBOPENCM3_NVIC_H __FLT32_DENORM_MIN__ 1.4012984643248171e-45F32SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)WCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1SCB_VTOR_TBLOFF_LSB 7__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LNVIC_I2C1_IRQ 23__INT64_MAX__ 0x7fffffffffffffffLL__ULLFRACT_IBIT__ 0STM32G0 1MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))__GNUC__ 12WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 1NVIC_USART3_USART4_LPUART1_IRQ 29__ULACCUM_MIN__ 0.0ULK__ARM_ARCH 6memory_manage_fault_stack__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__FLT_EPSILON__ 1.1920928955078125e-7F__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)NVIC_UCPD1_UCPD2_IRQ 8SCB_CPUID_IMPLEMENTER_LSB 24__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64LIBOPENCM3_STM32_G0_NVIC_H __INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4NVIC_USART1_IRQ 27__UFRACT_MAX__ 0XFFFFP-16URblocking_handler__UINT32_TYPE__ long unsigned intINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__ARM_32BIT_STATE__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308reset__INT_FAST32_TYPE__ intNVIC_TIM14_IRQ 19unsigned int__GCC_ASM_FLAG_OUTPUTS__NVIC_TIM2_IRQ 15__init_array_end__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8NVIC_DMA1_CHANNEL1_IRQ 9__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SCB_SHPR_PRI_6_USAGEFAULT 2__thumb2____ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned char__SIG_ATOMIC_TYPE__ intNVIC_AES_RNG_IRQ 31UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINtrue 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)pend_sv__FLT32X_MIN_EXP__ (-1021)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 1__LFRACT_EPSILON__ 0x1P-31LR__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX___ebss__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)SCB_AIRCR_SYSRESETREQ (1 << 2)/build/libopencm3/lib/stm32/g0SCB_ICSR_ISRPENDING (1 << 22)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 1__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)__GCC_ATOMIC_POINTER_LOCK_FREE 1__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1__FLT32_DIG__ 6INT_LEAST16_MAXSCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)BIT15 (1<<15)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_ICSR_VECTACTIVE_LSB 0long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intNVIC_IPR32(ipr_id) MMIO32(NVIC_BASE + 0x300 + ((ipr_id) * 4))__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR_data_loadaddr__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128LIBOPENCM3_SCB_H __FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffPTRDIFF_MAX __PTRDIFF_MAX____FLT32_DECIMAL_DIG__ 9__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_PVD_IRQ 1NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))WCHAR_MINBEGIN_DECLS __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKINT_LEAST64_MIN (-INT_LEAST64_MAX - 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16_BSD_PTRDIFF_T_ __WCHAR_WIDTH__ 32__ULFRACT_FBIT__ 32__FLT64_MIN_10_EXP__ (-307)__size_t __bounded BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901L___int_wchar_t_h _REENT_INIT_PTR_ZEROED(var) { (var)->_stdin = _REENT_STDIO_STREAM(var, 0); (var)->_stdout = _REENT_STDIO_STREAM(var, 1); (var)->_stderr = _REENT_STDIO_STREAM(var, 2); (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; }__SFRACT_EPSILON__ 0x1P-7HR__CONCAT1(x,y) x ## y__CC_SUPPORTS___INLINE 1__DBL_MIN_10_EXP__ (-307)__USQ_FBIT__ 32__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__GCC_ATOMIC_CHAR32_T_LOCK_FREE 1__SQ_FBIT__ 31_ELIDABLE_INLINE static __inline____UHQ_FBIT__ 16_REENT_EMERGENCY_SIZE 25__PTRDIFF_WIDTH__ 32INT_FAST8_MAX__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)__UINT_FAST8_MAX__ 0xffffffffUPTRDIFF_MIN_NOTHROW __has_extension __has_featureNULL_REENT_CHECK_MP(ptr) __LACCUM_IBIT__ 32__SCHAR_WIDTH__ 8__NEWLIB_H__ 1__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)__INTPTR_MAX__ 0x7fffffffSCB_SHPR_PRI_9_RESERVED 5__RAND_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_TYPE__ intINT64_C(c) __INT64_C(c)__attribute_pure__ _Nonnull __GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))__UFRACT_MIN__ 0.0UR_N_LISTS 30_WANT_IO_LONG_LONG 1__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX___SYS_SIZE_T_H _REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed)__UINT_LEAST8_TYPE__ unsigned char__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))SCB_BASE (SCS_BASE + 0x0D00)__ACCUM_FBIT__ 15SCB_SCR_SLEEPONEXIT (1 << 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const_SIZE_T_DECLARED UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN____FLT_MIN_10_EXP__ (-37)_READ_WRITE_BUFSIZE_TYPE int__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32_CLOCK_T_ unsigned long_TIME_T_ __int_least64_tBIT27 (1<<27)__LARGEFILE_VISIBLE 0UINT64_MAX__NEWLIB__ 3SCB_CPUID_CONSTANT_LSB 16__GNUC_EXECUTION_CHARSET_NAME "UTF-8"EXIT_SUCCESS 0__UTA_FBIT__ 64__ISO_C_VISIBLE 1999__FLT_DECIMAL_DIG__ 9signed char__asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__))INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__ptr_t void *_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__alloc_align(x) __attribute__((__alloc_align__(x)))SCB_CPUID_VARIANT_LSB 20_RAND48_SEED_2 (0x1234)PPBI_BASE (0xE0000000U)_REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)__predict_true(exp) __builtin_expect((exp), 1)_STDBOOL_H _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__attribute_format_strfmon__(a,b) _BSD_SIZE_T_DEFINED_ __UINT_FAST32_TYPE__ unsigned int___int_size_t_h END_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32x__GNUCLIKE_MATH_BUILTIN_RELOPS __FLT_MAX_10_EXP__ 38__PMT(args) argsSCB_SCR MMIO32(SCB_BASE + 0x10)__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__UINTMAX_C__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5_READ_WRITE_RETURN_TYPE int__ARM_ARCH_EXT_IDIV____DEFINED_size_t BIT8 (1<<8)__need_wint_tBEGIN_DECLS __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))__UINT16_MAX__ 0xffff__TQ_FBIT__ 127__LDBL_MAX_EXP__ 1024__POSIX_VISIBLE 0_HAVE_LONG_DOUBLE 1_Alignas(x) __aligned(x)__GNUCLIKE_BUILTIN_CONSTANT_P 1__SIZEOF_SHORT__ 2__P(protos) protosSCB_SHCSR MMIO32(SCB_BASE + 0x24)__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))__STRICT_ANSI__ 1_SYS_FEATURES_H __returns_twice __attribute__((__returns_twice__))UINT_LEAST8_MAX_MACHSTDLIB_H_ UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__char__USA_IBIT__ 16__need_wchar_t __hidden __attribute__((__visibility__("hidden")))__SFRACT_MAX__ 0X7FP-7HR__UINT_FAST64_TYPE__ long long unsigned intSCB_ICSR_NMIPENDSET (1 << 31)_WINT_T __lock_close(lock) ((void) 0)__FLT_MIN__ 1.1754943508222875e-38F__need_size_t __HA_FBIT__ 7__FDPIC____FLT_MAX__ 3.4028234663852886e+38F__FLT32_IS_IEC_60559__ 2__noinline __attribute__ ((__noinline__))UINT64_C(c) __UINT64_C(c)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__weak_symbol __attribute__((__weak__))__USFRACT_MIN__ 0.0UHR__used __attribute__((__used__))__ARM_NEON_REENT_EMERGENCY(ptr) ((ptr)->_emergency)__UINT8_MAX__ 0xff___int16_t_defined 1UINTMAX_C(c) __UINTMAX_C(c)_REENT _impure_ptr__has_feature(x) 0__exported __attribute__((__visibility__("default")))__SCCSID(s) struct __hackBIT7 (1<<7)__DBL_HAS_DENORM__ 1SCB_ICSR_PENDSVSET (1 << 28)_MB_LEN_MAX 1__DA_FBIT__ 31long long intBIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308L__ULLACCUM_EPSILON__ 0x1P-32ULLK__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))_END_STD_C SCB_SHPR_PRI_14_PENDSV 10_T_SIZE SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)__UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)_Null_unspecified __FLT_EPSILON__ 1.1920928955078125e-7F__XSTRING(x) __STRING(x)__restrict restrictSCB_CPUID_VARIANT (0xF << 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0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FLT32X_IS_IEC_60559__ 2INT_LEAST64_MAX __INT_LEAST64_MAX__LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX_REENT_CHECK_EMERGENCY(ptr) __INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__ATFILE_VISIBLE 0__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)SCB_SCR_SEVONPEND (1 << 4)_Thread_local __thread__OPTIMIZE_SIZE__ 1___int_least32_t_defined 1__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__need_NULLUINT64_C__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)SCB_CCR_UNALIGN_TRP (1 << 3)_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))__INT_LEAST8_MAX__ 0x7f__ARM_FEATURE_IDIV__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEX__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))unsigned signedSCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024SCB_ICSR MMIO32(SCB_BASE + 0x04)BIT21 (1<<21)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__lock_acquire(lock) ((void) 0)__section(x) __attribute__((__section__(x)))__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)SCB_VTOR_TBLOFF_LSB 7__GCC_HAVE_DWARF2_CFI_ASM 1___int8_t_defined 1__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__ARM_FEATURE_UNALIGNED__offsetof(type,field) offsetof(type, field)__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVE__nonnull_all __attribute__((__nonnull__))__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRAND_MAX __RAND_MAX__SOFTFP__ 1UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN_T_SIZE_ __FLT_EVAL_METHOD_TS_18661_3__ 0__attribute_malloc__ __lock_init_recursive(lock) ((void) 0)BIT18 (1<<18)UINT_FAST16_MAX__NULLABILITY_PRAGMA_POP SCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffL__min_size(x) static (x)_TIMER_T_ unsigned longUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__null_sentinel __attribute__((__sentinel__))__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__need_NULL __FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8__LDBL_EPSILON__ 2.2204460492503131e-16LBIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 1INTMAX_C(c) __INTMAX_C(c)__NULLABILITY_PRAGMA_PUSH __DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3__FLT32X_HAS_DENORM__ 1__FLT_MANT_DIG__ 24_RAND48_SEED_1 (0xabcd)__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << 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