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R/1    .! / 2~ <.    0"! / 0  / ~    .f. ! /~  "/!%.<(0~ y ,0LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1__UACCUM_FBIT__ 16__APCS_32__ 1RCC_APB1RSTR_TIM3RST (1 << 1)RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODENRCC_APB1LPENR_CAN2LPEN (1 << 26)__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN___STDDEF_H_ unsigned intRCC_AHB1ENR_ETHMACRXEN (1 << 27)__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_CFGR_HPRE_DIV_2 (0x8 + 0)RCC_APB1LPENR_TIM5LPEN (1 << 3)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RST_WWDG__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16INTPTR_MIN (-INTPTR_MAX - 1)GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRSTRCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASKWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB1ENR_ETHMACTXEN (1 << 26)__INT_FAST16_MAX__ 0x7fffffffRCC_AHB1LPENR_GPIOALPEN (1 << 0)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__FLT64_MANT_DIG__ 53RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8UINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_AHB1RSTR_IOPKRST RCC_AHB1RSTR_GPIOKRST__SIG_ATOMIC_MAX__ 0x7fffffffRCC_APB2RSTR_USART1RST (1 << 4)RCC_DCKCFGR_SAI1SRC_I2SQ 0x1RCC_APB2ENR_TIM9EN (1 << 16)RCC_AHB1RSTR_DMA1RST (1 << 21)RCC_APB2LPENR_SYSCFGLPEN (1 << 14)__ARM_PCS_VFP 1RCC_CFGR_RTCPRE_MASK 0x1f__FLT32_HAS_INFINITY__ 1__USQ_IBIT__ 0RCC_AHB1ENR_GPIOIEN (1 << 8)__PTRDIFF_MAX__ 0x7fffffffINT64_MIN (-INT64_MAX - 1)RCC_AHB1LPENR_GPIOGLPEN (1 << 6)RCC_CFGR_HPRE_DIV16 (0x8 + 3)UINT_FAST32_MAXRCC_CFGR_I2SSRC (1 << 23)BIT10 (1<<10)RST_SAI1RST__STDC__ 1I2C1_FLTR I2C_FLTR(I2C1)RCC_AHB1RSTR_GPIOERST (1 << 4)RCC_APB2RSTR_TIM8RST (1 << 1)__ULLFRACT_IBIT__ 0__FLT32_MAX_EXP__ 128__SA_FBIT__ 15I2C3_FLTR I2C_FLTR(I2C3)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32RCC_CFGR_PLLSRC_HSI_CLK 0x0FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)__DBL_MAX_10_EXP__ 308INT_LEAST32_MINFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)__ARM_FEATURE_IDIV 1__WCHAR_TYPE__ unsigned intRCC_CFGR_PPRE_DIV8 0x6__UDA_IBIT__ 32i2c_speed_unknown__ELF__ 1__SIZEOF_LONG__ 4RCC_CFGR_HPRE_DIV_8 (0x8 + 2)DWT_BASE (PPBI_BASE + 0x1000)__ARM_ARCH 7RCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)LIBOPENCM3_MEMORYMAP_H RCC_CSR_IWDGRSTF (1 << 29)BIT3 (1<<3)RCC_PLLSAICFGR_PLLSAIR_MASK 0x7RCC_AHB3RSTR_FSMCRST (1 << 0)TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)i2c_disable_ackRCC_AHB2LPENR_HASHLPEN (1 << 5)RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)SIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1RCC_APB1ENR_DACEN (1 << 29)WINT_MIN__INTPTR_TYPE__ intRST_FMC__DQ_FBIT__ 63__DBL_HAS_INFINITY__ 1__UACCUM_EPSILON__ 0x1P-16UKRCC_APB1ENR_PWREN (1 << 28)__INT_FAST16_WIDTH__ 32I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00)__FLT_HAS_INFINITY__ 1RCC_APB2ENR MMIO32(RCC_BASE + 0x44)uint16_tRCC_AHB1LPENR_CRCLPEN (1 << 12)BIT1 (1<<1)RST_ETHMACI2C_SR2_GENCALL (1 << 4)RCC_APB1LPENR_TIM2LPEN (1 << 0)INT_FAST64_MAX __INT_FAST64_MAX__RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32RCC_APB2LPENR_ADC3LPEN (1 << 10)PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)I2C_FLTR_ANOFF (1<<4)RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF__SHRT_MAX__ 0x7fffITM_BASE (PPBI_BASE + 0x0000)__FP_FAST_FMAF32 1I2C_WRITE 0RCC_APB1LPENR_DACLPEN (1 << 29)_T_PTRDIFF_ RCC_CIR_LSERDYF (1 << 1)RCC_AHB1ENR_CCMDATARAMEN (1 << 20)RCC_AHB1RSTR_GPIOGRST (1 << 6)RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHENRCC_DCKCFGR_PLLSAIDIVR_MASK 0x3I2C_CR1_ACK (1 << 10)RCC_CFGR_MCO1_HSI 0x0I2C_SR2_DUALF (1 << 7)__USFRACT_MIN__ 0.0UHRI2C_OAR1_ADDMODE_10BIT 1RCC_SSCGR_INCSTEP_SHIFT 13__INT_LEAST32_TYPE__ long intUSART6_BASE (PERIPH_BASE_APB2 + 0x1400)RCC_APB2ENR_SDIOEN (1 << 11)BIT13 (1<<13)readwriteRCC_CFGR_PPRE_DIV_4 0x5BIT4 (1<<4)__FLT_IS_IEC_60559__ 2__FLT_DIG__ 6__ATOMIC_ACQ_REL 4RCC_AHB2ENR_HASHEN (1 << 5)RCC_PLLCFGR_PLLM_SHIFT 0INT32_CI2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRSTRCC_PLLCFGR_PLLN_SHIFT 6__INT_FAST64_MAX__ 0x7fffffffffffffffLL__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intRCC_BDCR_LSERDY (1 << 1)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsLIBOPENCM3_PWR_COMMON_V1_H MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLRCC_APB2LPENR_USART1LPEN (1 << 4)i2c_set_own_7bit_slave_address_twoRCC_APB1ENR_TIM6EN (1 << 4)__SIZEOF_INT__ 4__ARMEL__ 1RCC_APB2ENR_USART6EN (1 << 5)__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)RCC_CSR_RMVF (1 << 24)data__SIG_ATOMIC_TYPE__ int_BSD_SIZE_T_DEFINED_ RCC_APB2ENR_SPI4EN (1 << 13)RCC_APB1RSTR_TIM13RST (1 << 7)PWR_CR_CWUF (1 << 2)__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intRCC_CFGR_PPRE_DIV4 0x5RCC_AHB1RSTR_GPIOFRST (1 << 5)RCC_APB1LPENR_UART8EN (1 << 31)RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24UINTMAX_MAXRCC_APB2LPENR_TIM10LPEN (1 << 17)PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR__HAVE_SPECULATION_SAFE_VALUE 1I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7RCC_AHB1RSTR_GPIOIRST (1 << 8)BIT15 (1<<15)__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CFSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)RCC_AHB2ENR_DCMIEN (1 << 0)RCC_CFGR_HPRE_DIV64 (0x8 + 4)BIT5 (1<<5)__BIGGEST_ALIGNMENT__ 8RCC_CFGR_MCOPRE_DIV_NONE 0x0__ARM_ARCHRCC_AHB1LPENR_GPIOHLPEN (1 << 7)__UINT8_TYPE__ unsigned charRCC_CFGR_MCOPRE_DIV_4 0x6RCC_CFGR_PPRE1_SHIFT 10INT_FAST64_MIN (-INT_FAST64_MAX - 1)__FLT32_MIN_10_EXP__ (-37)RCC_CFGR_PPRE_DIV_16 0x7RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)RCC_PLLCFGR_PLLN_MASK 0x1ff__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__FLT32_NORM_MAX__ 3.4028234663852886e+38F32__INT_LEAST16_MAX__ 0x7fffEXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)RCC_APB2RSTR_LTDCRST (1 << 26)BIT12 (1<<12)RCC_AHB1LPENR_OTGHSLPEN (1 << 29)RCC_APB1ENR_UART4EN (1 << 19)SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)RCC_AHB1ENR_DMA2EN (1 << 22)I2C1_CCR I2C_CCR(I2C1)RCC_CFGR_HPRE_DIV_64 (0x8 + 4)interruptRCC_AHB1LPENR_GPIOCLPEN (1 << 2)RCC_CR_PLLON (1 << 24)BIT16 (1<<16)__SACCUM_IBIT__ 8__UINT16_TYPE__ short unsigned intI2C_CR1_START (1 << 8)RST_DMA1RST_DMA2i2c_disable_dmaRCC_APB1ENR_SPI3EN (1 << 15)__SFRACT_IBIT__ 0__FLT32X_HAS_INFINITY__ 1RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCENRCC_APB1LPENR_CAN1LPEN (1 << 25)I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)RCC_APB1LPENR_PWRLPEN (1 << 28)__INT8_C(c) cRCC_APB2LPENR_TIM8LPEN (1 << 1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)PWR_CSR_BRR (1 << 3)__ARM_EABI__ 1RST_TIM10RST_TIM11RST_TIM12RST_TIM13freq__FLT32_EPSILON__ 1.1920928955078125e-7F32INT_LEAST8_MAX __INT_LEAST8_MAX__false 0__FLT_MAX_EXP__ 128__INT64_MAX__ 0x7fffffffffffffffLLBIT17 (1<<17)__ATOMIC_SEQ_CST 5GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)RCC_BDCR_BDRST (1 << 16)RCC_CR MMIO32(RCC_BASE + 0x00)GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)__FLT32X_MAX_EXP__ 1024__FLT32_MANT_DIG__ 24RCC_APB1ENR_TIM3EN (1 << 1)__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8__UTA_FBIT__ 64RCC_APB1RSTR_UART7RST (1 << 30)DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)I2C2_OAR2 I2C_OAR2(I2C2)__DBL_DIG__ 15RCC_APB2LPENR_USART6LPEN (1 << 5)INTPTR_MAX __INTPTR_MAX__RCC_CKGATENR_SRAM_CKEN (1<<4)__DECIMAL_DIG__ 17INT_FAST16_MIN__SIZEOF_DOUBLE__ 8I2C2_CR1 I2C_CR1(I2C2)PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_C__UINT64_TYPE__ long long unsigned intRCC_AHB1RSTR_GPIOBRST (1 << 1)BIT18 (1<<18)__LFRACT_IBIT__ 0__USER_LABEL_PREFIX__ RCC_APB1ENR_SPI2EN (1 << 14)RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)RCC_APB1RSTR_WWDGRST (1 << 11)_SIZE_T_DECLARED RCC_APB2RSTR_TIM1RST (1 << 0)RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)INT64_MAX __INT64_MAX____QQ_IBIT__ 0clock_megahzRCC_AHB3ENR_FMCEN (1 << 0)RCC_AHB2RSTR_OTGFSRST (1 << 7)UINT_LEAST64_MAX/build/libopencm3/lib/stm32/f4RST_PWRSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)__DBL_MIN__ ((double)2.2250738585072014e-308L)__INT_FAST8_MAX__ 0x7fffffffi2c_speed_sm_100k_WCHAR_T __INT_FAST8_WIDTH__ 32RCC_CFGR_MCO1_SHIFT 21RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_APB1LPENR_TIM7LPEN (1 << 5)__ARM_FP16_ARGS__FLT32_MIN_EXP__ (-125)RCC_CR_PLLSAIRDY (1 << 29)CORESIGHT_LSR_SLK (1<<1)FMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_APB2RSTR_TIM10RST (1 << 17)__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)I2C2_OAR1 I2C_OAR1(I2C2)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)__UFRACT_MIN__ 0.0UR_GCC_PTRDIFF_T RCC_APB2LPENR_SPI5LPEN (1 << 20)_T_SIZE_ __FLT_MIN_10_EXP__ (-37)RCC_PLLCFGR_PLLSRC (1 << 22)RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)RCC_CFGR_HPRE_DIV512 (0x8 + 7)INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0RCC_APB2ENR_TIM10EN (1 << 17)RCC_AHB3LPENR_QSPIEN (1 << 1)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32I2C2_CCR I2C_CCR(I2C2)__FLT64_MAX_EXP__ 1024__ULLACCUM_MIN__ 0.0ULLK__INT_WCHAR_T_H RST_HASHDESIG_FLASH_SIZE_BASE (0x1FFF7A22U)INT_FAST64_MAXDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__size_t __WINT_MAX__ 0xffffffffUPERIPH_BASE_AHB3 0x60000000U__ARM_FP16_FORMAT_ALTERNATIVERCC_CFGR_MCO2_MASK 0x3UINTPTR_MAXPWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)RCC_AHB1RSTR_GPIODRST (1 << 3)INT32_C(c) __INT32_C(c)_REG_BIT(base,bit) (((base) << 5) + (bit))__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_CIR_PLLI2SRDYF (1 << 5)__FLT_EPSILON__ 1.1920928955078125e-7Fdutycycle__UINT8_C(c) cRCC_AHB1ENR_GPIOHEN (1 << 7)RCC_PLLCFGR_PLLR_MASK 0x7RCC_CFGR_SWS_HSE 0x1__ARM_FEATURE_NUMERIC_MAXMINRCC_AHB3ENR_FSMCEN (1 << 0)I2C_SR2_SMBDEFAULT (1 << 5)RST_RNGRCC_CIR_LSERDYIE (1 << 9)UINT16_MAX __UINT16_MAX__RCC_APB1RSTR_I2C2RST (1 << 22)RCC_APB2ENR_SAI1EN (1 << 22)__ULLFRACT_MIN__ 0.0ULLRunsigned charGPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)__LDBL_DIG__ 15__ARM_FEATURE_QRDMXRCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)BIT8 (1<<8)RCC_APB2LPENR_TIM9LPEN (1 << 16)RCC_APB2ENR_ADC3EN (1 << 10)WINT_MAX__ORDER_LITTLE_ENDIAN__ 1234_PTRDIFF_T_DECLARED ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)I2C_SR1_SMBALERT (1 << 15)PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)RST_QSPII2C_CR1_SWRST (1 << 15)MMIO64(addr) (*(volatile uint64_t *)(addr))__DBL_MAX_EXP__ 1024PWR_CR_DBP (1 << 8)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)__ARM_FEATURE_FP16_FMLRCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_HPRE_DIV256 (0x8 + 6)RCC_APB2RSTR_TIM9RST (1 << 16)RCC_PLLCFGR_PLLP_SHIFT 16__SIZEOF_SIZE_T__ 4I2C3_CR1 I2C_CR1(I2C3)CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)_BSD_WCHAR_T__PTRDIFF_T PWR_CR_VOS_SHIFT 14RCC_APB2RSTR_SYSCFGRST (1 << 14)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFENI2C_CCR(i2c_base) MMIO32((i2c_base) + 0x1c)RCC_CR_CSSON (1 << 19)BEGIN_DECLS NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7__LLACCUM_EPSILON__ 0x1P-31LLK_REG_BITPTRDIFF_MIN (-PTRDIFF_MAX - 1)I2C1_OAR1 I2C_OAR1(I2C1)I2C_SR1_SB (1 << 0)RCC_AHB1RSTR_ETHMACRST (1 << 25)__SIZEOF_LONG_LONG__ 8PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)SIZE_MAXRCC_APB1LPENR_TIM13LPEN (1 << 7)RCC_CFGR_MCO2PRE_SHIFT 27RCC_SSCGR_SPREADSEL (1 << 30)__FLT32_DECIMAL_DIG__ 9rcc_periph_rstBIT9 (1<<9)RCC_AHB1RSTR_CRCRST (1 << 12)RCC_APB1RSTR_I2C1RST (1 << 21)RCC_SSCGR_SSCGEN (1 << 31)RCC_CR_PLLI2SON (1 << 26)_WCHAR_T_DEFINED_ PWR_CR_FPDS (1 << 9)__WINT_TYPE__ unsigned intRCC_APB2LPENR MMIO32(RCC_BASE + 0x64)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)UINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_HPRE_SHIFT 4SCB_BASE (SCS_BASE + 0x0D00)I2C3_CCR I2C_CCR(I2C3)RCC_APB2ENR_SPI1EN (1 << 12)i2c_enable_dual_addressing_modeRCC_DCKCFGR_TIMPRE (1 << 24)__INT16_MAX__ 0x7fff__ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24__ULACCUM_FBIT__ 32RCC_AHB1ENR_GPIOEEN (1 << 4)__FLT64_HAS_QUIET_NAN__ 1RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)RCC_APB2ENR_SYSCFGEN (1 << 14)RCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBENINT_LEAST16_MINRCC_BDCR_RTCSEL_NONE 0__ARM_ARCH_PROFILE 77__ULACCUM_IBIT__ 32RCC_APB1RSTR_TIM12RST (1 << 6)__ARM_FEATURE_COPROC 15BIT20 (1<<20)I2C3_DR I2C_DR(I2C3)_WCHAR_T_H __INT_LEAST8_MAX__ 0x7f__UQQ_FBIT__ 8I2C3_CR2 I2C_CR2(I2C3)RCC_CKGATENR_CM4DBG_CKEN (1<<2)PWR_CR_PLS_LSB 5__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____UINT64_C(c) c ## ULLRCC_APB1LPENR_UART7EN (1 << 30)__FLT_RADIX__ 2PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)__USA_FBIT__ 16PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16Li2c_disable_interrupt__ARM_BF16_FORMAT_ALTERNATIVERCC_PLLSAICFGR_PLLSAIP_DIV2 0x0RCC_AHB1ENR_ETHMACPTPEN (1 << 28)__FLT_EVAL_METHOD_TS_18661_3__ 0__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CFGR_PPRE_NODIV 0x0__USA_IBIT__ 16I2C3_TRISE I2C_TRISE(I2C3)__INT32_TYPE__ long intRCC_APB1LPENR_TIM6LPEN (1 << 4)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKSDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)BIT21 (1<<21)RCC_AHB1RSTR_DMA2DRST (1 << 23)DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15Ri2c_read7_v1__GCC_ATOMIC_INT_LOCK_FREE 2BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_APB1LPENR_WWDGLPEN (1 << 11)__INT_WIDTH__ 32RCC_BDCR_RTCSEL_HSE 3RCC_APB1ENR_WWDGEN (1 << 11)RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)I2C_SR1_AF (1 << 10)RCC_AHB1RSTR_DMA2RST (1 << 22)RCC_AHB1ENR_DMA1EN (1 << 21)CORESIGHT_LAR_KEY 0xC5ACCE55I2C_SR2_BUSY (1 << 1)__FLT32_IS_IEC_60559__ 2RCC_APB1RSTR_SPI2RST (1 << 14)RCC_CFGR_PLLSRC_HSE_CLK 0x1__FLT64_DIG__ 15__ARM_NEONRCC_CR_PLLSAION (1 << 28)__INT_LEAST16_WIDTH__ 16RCC_CFGR_MCO1PRE_MASK 0x7__ARM_ARCH_7EM__ 1RCC_CFGR_PPRE_DIV_8 0x6RCC_CFGR_HPRE_DIV_512 (0x8 + 7)__INT16_C(c) cINT_FAST8_MAXBIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17RCC_CFGR_HPRE_DIV_4 (0x8 + 1)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2RCC_CKGATENR MMIO32(RCC_BASE + 0x90)__INT16_TYPE__ short int__bool_true_false_are_defined 1__FRACT_MIN__ (-0.5R-0.5R)__ULFRACT_FBIT__ 32SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)___int_size_t_h RCC_APB1RSTR_TIM6RST (1 << 4)_SIZE_T_DEFINED_ PWR_CSR_BRE (1 << 9)size_t__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H __ARM_FEATURE_CRYPTOPTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0RST_BDCRADC3_BASE (PERIPH_BASE_APB2 + 0x2200)__UHQ_FBIT__ 16I2C2_DR I2C_DR(I2C2)RCC_DCKCFGR_SDMMCSEL (1 << 28)I2C_SR2_SMBHOST (1 << 6)INTMAX_MIN (-INTMAX_MAX - 1)RCC_CFGR_SWS_PLL 0x2NULLRCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1fBIT23 (1<<23)RCC_APB2ENR_TIM8EN (1 << 1)PWR_CR_PVDE (1 << 4)__FP_FAST_FMAF 1__WCHAR_MIN__ 0URCC_BASE (PERIPH_BASE_AHB1 + 0x3800)RCC_CR_HSION (1 << 0)RCC_APB2LPENR_SPI1LPEN (1 << 12)RCC_APB1LPENR_USART3LPEN (1 << 18)RCC_CIR_HSIRDYF (1 << 2)_GCC_WCHAR_T i2c_peripheral_enableRCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15RCC_APB1ENR_TIM2EN (1 << 0)RCC_AHB1RSTR_GPIOARST (1 << 0)addr__FLT32_MAX__ 3.4028234663852886e+38F32RCC_APB1LPENR_SPI2LPEN (1 << 14)RCC_AHB2RSTR_HASHRST (1 << 5)__INT32_MAX__ 0x7fffffffL__CHAR_UNSIGNED__ 1RCC_APB1LPENR_TIM3LPEN (1 << 1)RCC_AHB2ENR_RNGEN (1 << 6)RCC_APB1LPENR_TIM4LPEN (1 << 2)BIT24 (1<<24)RCC_DCKCFGR_SAI1SRC_SAIQ 0x0TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)__SCHAR_MAX__ 0x7fRST_DCMI__GCC_HAVE_DWARF2_CFI_ASM 1RCC_PLLCFGR_PLLQ_MASK 0xfINT16_MAX __INT16_MAX___SIZE_T_ TPIU_BASE (PPBI_BASE + 0x40000)I2C3_SR1 I2C_SR1(I2C3)__SACCUM_EPSILON__ 0x1P-7HKRCC_PLLSAICFGR_PLLSAIP_MASK 0x3I2C_SR1_STOPF (1 << 4)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPEN__need_size_tRCC_PLLSAICFGR_PLLSAIP_SHIFT 16__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CFGR_HPRE_DIV_256 (0x8 + 6)I2C3_OAR2 I2C_OAR2(I2C3)RCC_AHB1ENR_GPIOKEN (1 << 10)I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c)RCC_DCKCFGR_SAI1ASRC_MASK 0x3i2c_speed_fmp_1mRCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN__HA_FBIT__ 7__UACCUM_MIN__ 0.0UKINT_LEAST32_MAX __INT_LEAST32_MAX__RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)RCC_AHB2RSTR_DCMIRST (1 << 0)RCC_APB1ENR MMIO32(RCC_BASE + 0x40)RCC_AHB1LPENR_DMA1LPEN (1 << 21)_STDBOOL_H __FLT_HAS_QUIET_NAN__ 1UINT_FAST64_MAX __UINT_FAST64_MAX__ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPENBIT25 (1<<25)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xSIG_ATOMIC_MAX __SIG_ATOMIC_MAX__GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)I2C_SR2_TRA (1 << 2)I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)UINTMAX_CRCC_AHB3RSTR_QSPIRST (1 << 1)__SCHAR_WIDTH__ 8__ORDER_PDP_ENDIAN__ 3412__UINT32_TYPE__ long unsigned int__ATOMIC_ACQUIRE 2PWR_CSR_PVDO (1 << 2)RST_USART1RST_USART2RST_USART3RCC_CSR MMIO32(RCC_BASE + 0x74)RST_USART6RCC_APB2RSTR_USART6RST (1 << 5)__INT_FAST64_TYPE__ long long intSTM32F4 1__ACCUM_FBIT__ 15__LLACCUM_FBIT__ 31RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)UINT32_C(c) __UINT32_C(c)RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94)RCC_CR_PLLI2SRDY (1 << 27)__SACCUM_MAX__ 0X7FFFP-7HKBIT26 (1<<26)INTMAX_MAX__ACCUM_IBIT__ 16RCC_AHB1RSTR_GPIOCRST (1 << 2)GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)UINT64_MAX __UINT64_MAX__SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)I2C3_OAR1 I2C_OAR1(I2C3)__INTMAX_WIDTH__ 64RCC_AHB1LPENR_DMA2DLPEN (1 << 23)RST_ADC__ARM_FEATURE_LDREX 7RCC_CIR_CSSF (1 << 7)__INT_LEAST64_WIDTH__ 64reg16RCC_CIR MMIO32(RCC_BASE + 0x0c)__ACCUM_EPSILON__ 0x1P-15KINT8_C(c) __INT8_C(c)__ARM_32BIT_STATE 1RCC_CFGR_MCO2_PLLI2S 0x1RCC_CIR_HSERDYIE (1 << 11)RCC_CFGR_PPRE1_MASK 0x7__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CIR_LSIRDYIE (1 << 8)__THUMB_INTERWORK__ 1RCC_APB2ENR_DSIEN (1 << 27)PPBI_BASE (0xE0000000U)__ARM_FEATURE_UNALIGNED 1BIT27 (1<<27)I2C_FLTR_DNF_MASK 0xF__SACCUM_FBIT__ 7__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__FRACT_MAX__ 0X7FFFP-15RRCC_AHB1ENR_GPIOGEN (1 << 6)RCC_CFGR_MCOPRE_DIV_5 0x7__GCC_IEC_559 0FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xADC1_BASE (PERIPH_BASE_APB2 + 0x2000)RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAENRCC_AHB2LPENR_RNGLPEN (1 << 6)RCC_CFGR_HPRE_DIV128 (0x8 + 5)i2c_get_dataMMIO32(addr) (*(volatile uint32_t *)(addr))RCC_CFGR_PPRE2_SHIFT 13PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)RCC_AHB1ENR_CRCEN (1 << 12)__wchar_t__ RCC_APB2ENR_TIM11EN (1 << 18)_WCHAR_T_DECLARED USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)__FRACT_IBIT__ 0BIT28 (1<<28)__INT_LEAST8_WIDTH__ 8I2C_OAR2_ENDUAL (1 << 0)__GNUC__ 12RCC_CFGR_PPRE_DIV_2 0x4I2C_READ 1LTDC_BASE (PERIPH_BASE_APB2 + 0x6800)__FLT32X_HAS_DENORM__ 1__INT_FAST16_TYPE__ intRCC_DCKCFGR_SAI1ASRC_SHIFT 20RCC_CFGR_SWS_MASK 0x3__INT_LEAST32_WIDTH__ 32__UTQ_IBIT__ 0__ARM_FEATURE_COPROC__DBL_IS_IEC_60559__ 2__UTA_IBIT__ 64RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16__SIZEOF_WINT_T__ 4INT_FAST8_MINRCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ffHASH_BASE (PERIPH_BASE_AHB2 + 0x60400)I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04)GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)__ARM_FEATURE_SAT 1i2c_transfer7__INT_MAX__ 0x7fffffffRCC_DCKCFGR_SAI1SRC_ALT 0x2__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)i2c_set_clock_frequencyi2c_nack_nextRCC_AHB1RSTR_OTGHSRST (1 << 29)__LFRACT_FBIT__ 31DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)__ARM_ARCH_ISA_THUMB__FLT64_IS_IEC_60559__ 2__SIZEOF_WCHAR_T__ 4INTMAX_CRCC_CFGR_MCO1_MASK 0x3__USACCUM_MAX__ 0XFFFFP-8UHKPWR_CSR_WUF (1 << 0)RCC_AHB1ENR_IOPJEN RCC_AHB1ENR_GPIOJENI2C_CCR_DUTY_DIV2 0__INT8_MAX__ 0x7f_WCHAR_T_ __INT_LEAST32_MAX__ 0x7fffffffLRCC_CFGR_SWS_HSI 0x0RCC_AHB1ENR_BKPSRAMEN (1 << 18)I2C_CR1_NOSTRETCH (1 << 7)__USACCUM_EPSILON__ 0x1P-8UHKRCC_CFGR MMIO32(RCC_BASE + 0x08)RCC_AHB1LPENR_ETHMACLPEN (1 << 25)RCC_DCKCFGR_SAI1SRC_ERROR 0x3_SYS_SIZE_T_H __INTMAX_C(c) c ## LLi2c_enable_ack__UINT_FAST16_MAX__ 0xffffffffUi2c_set_own_10bit_slave_address__UINT_FAST64_TYPE__ long long unsigned intRCC_CKGATENR_RCC_CKEN (1<<6)BIT0 (1<<0)RCC_APB2LPENR_SPI6LPEN (1 << 21)RCC_BDCR_RTCEN (1 << 15)STIR_BASE (SCS_BASE + 0x0F00)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__UFRACT_EPSILON__ 0x1P-16URRCC_AHB1LPENR_SRAM2LPEN (1 << 17)UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)RCC_CSR_SFTRSTF (1 << 28)RCC_APB2LPENR_ADC2LPEN (1 << 9)RCC_CFGR_MCOPRE_DIV_2 0x4I2C_SR1_PECERR (1 << 12)LIBOPENCM3_MEMORYMAP_COMMON_H RCC_AHB1LPENR_GPIOKLPEN (1 << 10)I2C_CR1_SMBTYPE (1 << 3)RCC_AHB1ENR_GPIODEN (1 << 3)TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)__UINT_FAST8_MAX__ 0xffffffffUI2C_CR2_ITBUFEN (1 << 10)__SQ_IBIT__ 0INT_FAST16_MIN (-INT_FAST16_MAX - 1)__ARM_FEATURE_SIMD32 1__need_NULLoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UHQ_IBIT__ 0RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6RCC_APB2RSTR_TIM11RST (1 << 18)__SFRACT_MIN__ (-0.5HR-0.5HR)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__LACCUM_FBIT__ 31RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3RCC_APB2RSTR_SAI1RST (1 << 22)__ULACCUM_MIN__ 0.0ULKRCC_AHB1LPENR_GPIODLPEN (1 << 3)RCC_CFGR_SW_HSE 0x1RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)RCC_APB1ENR_TIM14EN (1 << 8)__LONG_MAX__ 0x7fffffffL__INT32_C(c) c ## L__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INTPTR_MAXRCC_CFGR_MCO2_SYSCLK 0x0RCC_CIR_LSIRDYF (1 << 0)I2C2 I2C2_BASE__FLT32X_IS_IEC_60559__ 2UINT_FAST32_MAX __UINT_FAST32_MAX__UINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)short unsigned int__LDBL_DECIMAL_DIG__ 17signed charRCC_CIR_PLLRDYC (1 << 20)RCC_DCKCFGR_SAI1BSRC_SHIFT 22I2C_CR1_ENGC (1 << 6)UINT16_C__size_t__ LIBOPENCM3_RCC_H RCC_APB1RSTR_TIM5RST (1 << 3)i2c_peripheral_disableBIT6 (1<<6)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX__i2c_clear_stopI2C_SR1_BTF (1 << 2)__ULLACCUM_EPSILON__ 0x1P-32ULLK__CHAR_BIT__ 8INTMAX_MINRCC_CFGR_HPRE_DIV_16 (0x8 + 3)__INTMAX_TYPE__ long long intI2C2_TRISE I2C_TRISE(I2C2)RST_CRYPRCC_APB1RSTR_I2C3RST (1 << 23)__ARM_FEATURE_DOTPRODI2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08)UART7_BASE (PERIPH_BASE_APB1 + 0x7800)_BSD_SIZE_T_ UINT16_C(c) __UINT16_C(c)__CHAR16_TYPE__ short unsigned intRCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGEN__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffffI2C2_SR1 I2C_SR1(I2C2)RCC_APB2RSTR_ADCRST (1 << 8)INT8_MINFMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)__GCC_ATOMIC_POINTER_LOCK_FREE 2I2C_OAR1_ADDMODE (1 << 15)RCC_AHB2LPENR_OTGFSLPEN (1 << 7)RCC_CFGR_MCO2PRE_MASK 0x7__DBL_MAX__ ((double)1.7976931348623157e+308L)GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)__FLT32_MAX_10_EXP__ 38SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)PWR_CSR_SBF (1 << 1)RCC_AHB1ENR_GPIOAEN (1 << 0)RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RST_GPIOFRST_GPIOGRST_GPIOHRST_GPIOIRST_GPIOJRST_GPIOKITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAX__WINT_WIDTH__ 32RCC_SSCGR MMIO32(RCC_BASE + 0x80)__WCHAR_T__ PERIPH_BASE (0x40000000U)__INT_FAST32_WIDTH__ 32__LDBL_HAS_DENORM__ 1I2C_CR1_SMBUS (1 << 1)_ANSI_STDDEF_H RCC_BDCR_LSEON (1 << 0)i2c_speed_fm_400k__ARM_FP16_FORMAT_IEEERST_TIM8__UINT_LEAST8_TYPE__ unsigned charRST_TIM9RCC_APB2RSTR_SPI5RST (1 << 20)PWR_CR_LPDS (1 << 0)RCC_CFGR_HPRE_DIV_128 (0x8 + 5)__USES_INITFINI__ 1BIT30 (1<<30)RCC_DCKCFGR_DSISEL (1 << 29)RCC_APB1ENR_USART3EN (1 << 18)RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1I2C_SR1_OVR (1 << 11)__USFRACT_MAX__ 0XFFP-8UHRRCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0RCC_AHB2LPENR_DCMILPEN (1 << 0)I2C_CCR_FS (1 << 15)__SIZE_MAX__ 0xffffffffURCC_APB1RSTR_TIM7RST (1 << 5)INT_FAST8_MAX __INT_FAST8_MAX__RCC_APB1LPENR_TIM14LPEN (1 << 8)__DBL_MIN_10_EXP__ (-307)I2C1_CR2 I2C_CR2(I2C1)__USQ_FBIT__ 32RCC_CKGATENR_FLITF_CKEN (1<<5)__INT_FAST8_TYPE__ int__REGISTER_PREFIX__ i2c_set_fast_modeUINT8_C(c) __UINT8_C(c)UINT32_MAX__ARM_FEATURE_BF16_SCALAR_ARITHMETICRCC_CIR_LSERDYC (1 << 17)RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULL__need_ptrdiff_tRCC_APB1ENR_CAN1EN (1 << 25)RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR_LPWRRSTF (1 << 31)I2C2_SR2 I2C_SR2(I2C2)I2C_OAR1_ADDMODE_7BIT 0long int__WINT_MIN__ 0U__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)RCC_AHB1LPENR_FLITFLPEN (1 << 15)__FLT64_MAX_10_EXP__ 308_WCHAR_T_DEFINED RCC_APB2LPENR_SDIOLPEN (1 << 11)i2c_set_standard_modeRCC_APB1RSTR_USART2RST (1 << 17)__PTRDIFF_TYPE__ int__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1i2c_nack_currentINT64_C(c) __INT64_C(c)__ARM_FPRCC_CKGATENR_EVTCL_CKEN (1<<7)RCC_CKGATENR_AHB2APB1_CKEN (1<<0)RCC_APB2LPENR_ADC1LPEN (1 << 8)_PTRDIFF_T_ UINT_FAST8_MAXI2C_SR1_RxNE (1 << 6)RCC_AHB2ENR_OTGFSEN (1 << 7)RCC_AHB1ENR_OTGHSULPIEN (1 << 30)RCC_APB2LPENR_SAI1LPEN (1 << 22)__UTQ_FBIT__ 128LIBOPENCM3_CM3_COMMON_H __PTRDIFF_T FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)__ARM_FEATURE_DSP 1RCC_CIR_HSERDYF (1 << 3)ST_VREFINT_CAL MMIO16(0x1FFF7A2A)I2C_CR1_PE (1 << 0)RCC_CFGR_RTCPRE_SHIFT 16LIBOPENCM3_PWR_H __FLT32_HAS_DENORM__ 1I2C_FLTR(i2c_base) MMIO32((i2c_base) + 0x24)RCC_AHB3ENR_QSPIEN (1 << 1)uint8_tINT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CSR_BORRSTF (1 << 25)__HQ_FBIT__ 15UINT8_C__LLACCUM_IBIT__ 32uint32_t__SIZE_T RST_UART4__FLT_MIN_EXP__ (-125)__LLFRACT_FBIT__ 63i2c_set_ccr__CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RCC_CFGR_SW_PLL 0x2__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPEN__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRI2C_CR2_ITERREN (1 << 8)RCC_AHB1LPENR_SRAM1LPEN (1 << 16)__SIZEOF_POINTER__ 4__GCC_ASM_FLAG_OUTPUTS__ 1QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)RST_SDIORCC_AHB1ENR_GPIOFEN (1 << 5)RCC_APB2ENR_USART1EN (1 << 4)RCC_APB1RSTR_SPI3RST (1 << 15)UINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned int_T_SIZE RCC_AHB1RSTR_GPIOKRST (1 << 10)RCC_CFGR_HPRE_DIV4 (0x8 + 1)__INTPTR_WIDTH__ 32INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXLIBOPENCM3_RCC_COMMON_ALL_H USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINi2c_set_dutycycle__ATOMIC_RELAXED 0__GNUC_EXECUTION_CHARSET_NAME "UTF-8"__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64RCC_CIR_PLLRDYIE (1 << 12)__FINITE_MATH_ONLY__ 0__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CR_PLLRDY (1 << 25)RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)_T_WCHAR_ __GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"UINT_FAST64_MAXRCC_APB1LPENR_SPI3LPEN (1 << 15)__STDC_VERSION__ 199901LRCC_AHB1ENR_OTGHSEN (1 << 29)__LFRACT_MIN__ (-0.5LR-0.5LR)PTRDIFF_MAXRST_DACRST_OTGFSI2C1 I2C1_BASE__LLFRACT_MIN__ (-0.5LLR-0.5LLR)I2C2_CR2 I2C_CR2(I2C2)RST_UART5RST_UART7RST_UART8RCC_APB2RSTR_SPI4RST (1 << 13)__GCC_ATOMIC_LLONG_LOCK_FREE 1I2C_CCR_DUTY_16_DIV_9 1I2C_DR(i2c_base) MMIO32((i2c_base) + 0x10)RCC_APB2ENR_ADC2EN (1 << 9)__ULFRACT_EPSILON__ 0x1P-32ULRRST_TIM1RST_TIM2RST_TIM3RST_TIM4RST_TIM5RST_TIM6RST_TIM7__LONG_LONG_WIDTH__ 64INT_LEAST64_MINRST_DMA2Dtrise__VERSION__ "12.2.1 20221205"RCC_CFGR_MCO1_LSE 0x1__FLT64_EPSILON__ 2.2204460492503131e-16F64__DBL_MANT_DIG__ 53RCC_PLLCFGR_PLLM_MASK 0x3f__ARM_ARCH_EXT_IDIV__ 1RCC_APB2LPENR_DSILPEN (1 << 27)__DEFINED_wchar_t RCC_APB2LPENR_LTDCLPEN (1 << 26)RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARSTI2C3_SR2 I2C_SR2(I2C3)UINT64_C(c) __UINT64_C(c)__ULLACCUM_FBIT__ 32i2c_send_7bit_addressRCC_AHB1LPENR_DMA2LPEN (1 << 22)__LDBL_HAS_QUIET_NAN__ 1___int_wchar_t_h RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)_SIZE_T FMC_BANK1 (PERIPH_BASE_AHB3)RCC_AHB1ENR_ETHMACEN (1 << 25)__ULLACCUM_IBIT__ 32RCC_APB1RSTR_TIM2RST (1 << 0)RCC_APB1LPENR_I2C1LPEN (1 << 21)__LDBL_MANT_DIG__ 53__ULLFRACT_FBIT__ 64WCHAR_MAXI2C_SR1(i2c_base) MMIO32((i2c_base) + 0x14)__DQ_IBIT__ 0DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)__FLT64_MAX__ 1.7976931348623157e+308F64_SIZE_T_DEFINED RST_OTGHSINT_LEAST8_MINCORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))RCC_AHB2ENR_CRYPEN (1 << 4)RCC_CR_HSITRIM_SHIFT 3RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)RCC_APB1LPENR_USART2LPEN (1 << 17)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_APB1ENR_I2C2EN (1 << 22)SYS_TICK_BASE (SCS_BASE + 0x0010)__ARM_FEATURE_LDREXTIM14_BASE (PERIPH_BASE_APB1 + 0x2000)I2C_SR2(i2c_base) MMIO32((i2c_base) + 0x18)__UINT_LEAST32_MAX__ 0xffffffffUL__LDBL_MAX_EXP__ 1024NULL ((void *)0)__USFRACT_EPSILON__ 0x1P-8UHRDESIG_UNIQUE_ID_BASE (0x1FFF7A10U)__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSERST_CAN1RST_CAN2__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1I2C_CCR_DUTY (1 << 14)I2C_CR1_STOP (1 << 9)__UINT_FAST32_TYPE__ unsigned int__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)true 1I2C_SR1_ADD10 (1 << 3)__need_wchar_t__FLT_DECIMAL_DIG__ 9BIT31 (1<<31)I2C_CR2_LAST (1 << 12)_T_PTRDIFF RCC_CFGR_HPRE_DIV_NONE 0x0__USACCUM_IBIT__ 8RCC_APB1ENR_TIM13EN (1 << 7)__ULFRACT_MIN__ 0.0ULRRCC_APB2RSTR MMIO32(RCC_BASE + 0x24)RST_LTDCSPI5_BASE (PERIPH_BASE_APB2 + 0x5000)__ARM_FEATURE_CDE__UINTPTR_TYPE__ unsigned intPWR_CSR_EWUP (1 << 8)RCC_APB1RSTR_TIM4RST (1 << 2)RCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRSTRCC_APB1RSTR_UART8RST (1 << 31)UINT8_MAX __UINT8_MAX____UDQ_FBIT__ 64RCC_CR_HSITRIM_MASK 0x1f__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT_EVAL_METHOD__ 0slaveRCC_BDCR_LSEBYP (1 << 2)UINT8_MAXST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C)RCC_AHB1LPENR_GPIOILPEN (1 << 8)RCC_APB1ENR_TIM5EN (1 << 3)RCC_APB2ENR_SPI6EN (1 << 21)RCC_CFGR_MCO1PRE_SHIFT 24POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)__ARM_SIZEOF_MINIMAL_ENUM 1__INT64_C(c) c ## LLI2C_SR1_ARLO (1 << 9)RCC_CFGR_HPRE_DIV2 (0x8 + 0)RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)RCC_AHB2RSTR_RNGRST (1 << 6)__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32SIZE_MAX __SIZE_MAX__RCC_CIR_HSIRDYIE (1 << 10)__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MIN__INT_FAST32_MAX__ 0x7fffffff__FLT_MAX_10_EXP__ 38RCC_APB2RSTR_SPI1RST (1 << 12)RCC_AHB1ENR_DMA2DEN (1 << 23)WINT_MIN __WINT_MIN__PWR_CR_PDDS (1 << 1)__TQ_FBIT__ 127__VFP_FP__ 1INT_LEAST16_MAX__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_PLLSAICFGR_PLLSAIR_SHIFT 28i2c_send_stopi2c_write7_v1RCC_PLLCFGR_PLLQ_SHIFT 24INT32_MAX__ARM_FP 4RCC_CIR_HSERDYC (1 << 19)RCC_CSR_WWDGRSTF (1 << 30)RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)__ULFRACT_IBIT__ 0RCC_APB1LPENR_UART5LPEN (1 << 20)i2c_send_dataETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)i2c_set_triseRCC_CFGR_SW_HSI 0x0GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)__GCC_CONSTRUCTIVE_SIZE 64__ARM_SIZEOF_WCHAR_T 4TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)RCC_SSCGR_MODPER_MASK 0x1fff__UINT_FAST32_MAX__ 0xffffffffUI2C1_TRISE I2C_TRISE(I2C1)RCC_APB1ENR_USART2EN (1 << 17)RCC_BDCR_RTCSEL_MASK 0x3RST_I2C1RCC_APB2RSTR_DSIRST (1 << 27)_BSD_WCHAR_T_ RCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICI2C_SR1_ADDR (1 << 1)RCC_APB1RSTR_UART4RST (1 << 19)_STDDEF_H speedTIM11_BASE (PERIPH_BASE_APB2 + 0x4800)UINT_LEAST16_MAX__INTMAX_MAX__ 0x7fffffffffffffffLLINT64_MAXRCC_APB1RSTR_DACRST (1 << 29)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_PLLSAICFGR_PLLSAIN_SHIFT 6__LONG_WIDTH__ 32__OPTIMIZE__ 1RCC_AHB1LPENR_IOPKLPEN RCC_AHB1LPENR_GPIOKLPEN__arm__ 1PTRDIFF_MINRCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRSTRCC_APB2ENR_TIM1EN (1 << 0)RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1RCC_CIR_LSIRDYC (1 << 16)I2C_CR2_ITEVTEN (1 << 9)RST_SPI5RST_SPI4RST_SPI1RST_SPI2RST_SPI3_T_WCHAR INT_FAST32_MIN (-INT_FAST32_MAX - 1)RST_SPI6_SIZET_ __INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324Li2c_reseti2c_set_own_7bit_slave_addressI2C_SR2_MSL (1 << 0)RCC_CIR_PLLSAIRDYC (1 << 22)i2c_enable_interruptUINT_LEAST32_MAX__ACCUM_MAX__ 0X7FFFFFFFP-15K__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intRCC_APB1ENR_I2C1EN (1 << 21)RCC_CR_HSIRDY (1 << 1)RCC_AHB1ENR_GPIOJEN (1 << 9)RCC_CFGR_MCOPRE_DIV_3 0x5RCC_CSR_PORRSTF (1 << 27)__ARM_NEON__USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_APB1RSTR_PWRRST (1 << 28)RCC_SSCGR_MODPER_SHIFT 0INT8_MAXI2C_CR1_PEC (1 << 12)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)RCC_CFGR_MCO1_HSE 0x2_BSD_PTRDIFF_T_ __WCHAR_T I2C_SR1_BERR (1 << 8)__ARM_ARCH_PROFILERCC_CFGR_MCO2_HSE 0x2__LACCUM_IBIT__ 32I2C_CR1_ENPEC (1 << 5)__ULLFRACT_EPSILON__ 0x1P-64ULLRMMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)RCC_AHB1LPENR_GPIOELPEN (1 << 4)RST_TIM14___int_ptrdiff_t_h RCC_APB1LPENR_I2C3LPEN (1 << 23)WCHAR_MIN __WCHAR_MIN__RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2long long unsigned int__SIZEOF_SHORT__ 2I2C_CR1_ALERT (1 << 13)UINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX__I2C_TRISE(i2c_base) MMIO32((i2c_base) + 0x20)I2C1_DR I2C_DR(I2C1)RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPENRCC_CSR_LSION (1 << 0)__UINT8_MAX__ 0xffRCC_APB1RSTR_CAN2RST (1 << 26)RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPENINT64_CRCC_APB2RSTR_SDIORST (1 << 11)RCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRSTRCC_APB1ENR_CAN2EN (1 << 26)RST_CRCRCC_APB2ENR_LTDCEN (1 << 26)RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPENRCC_CIR_CSSC (1 << 23)I2C1_CR1 I2C_CR1(I2C1)BIT19 (1<<19)RCC_AHB1RSTR_IOPJRST RCC_AHB1RSTR_GPIOJRSTUINT_FAST16_MAX__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEXRCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEENrcc_periph_reset_pulseRCC_DCKCFGR_48MSEL (1 << 27)RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)RCC_AHB1LPENR_GPIOFLPEN (1 << 5)__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1RCC_CFGR_MCO2_SHIFT 30__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short int__UINT_LEAST64_TYPE__ long long unsigned intRCC_APB1ENR_I2C3EN (1 << 23)END_DECLS INT32_MAX __INT32_MAX____USFRACT_FBIT__ 8RCC_APB1ENR_UART8EN (1 << 31)PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E)i2c_speedsPWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CKGATENR_AHB2APB2_CKEN (1<<1)__SIZEOF_PTRDIFF_T__ 4__DA_IBIT__ 32__DBL_DECIMAL_DIG__ 17RCC_AHB3LPENR_FMCLPEN (1 << 0)RCC_PLLCFGR_PLLP_MASK 0x3RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)UINT64_MAX__FLT32X_HAS_QUIET_NAN__ 1RCC_PLLSAICFGR_PLLSAIQ_MASK 0xFRCC_CFGR_HPRE_DIV8 (0x8 + 2)TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_APB1ENR_UART5EN (1 << 20)__SIG_ATOMIC_WIDTH__ 32__DBL_MIN_EXP__ (-1021)i2c_set_speedMPU_BASE (SCS_BASE + 0x0D90)QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)RCC_AHB1RSTR_GPIOHRST (1 << 7)UINT16_MAXRCC_APB2ENR_ADC1EN (1 << 8)__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)PWR_CR_CSBF (1 << 3)RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)RST_SYSCFG__INT64_TYPE__ long long intINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308L../common/i2c_common_v1.cbool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_AHB1LPENR_GPIOBLPEN (1 << 1)i2c_disable_dual_addressing_modePWR_CSR_VOSRDY (1 << 14)__UINT_LEAST32_TYPE__ long unsigned intRCC_APB1ENR_TIM7EN (1 << 5)RCC_APB2RSTR_SPI6RST (1 << 21)RST_FSMCPWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)RCC_APB1RSTR_UART5RST (1 << 20)INT32_MIN__HA_IBIT__ 8INT16_C(c) __INT16_C(c)__TA_IBIT__ 64RCC_CFGR_PPRE_DIV_NONE 0x0I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)INT8_MIN (-INT8_MAX - 1)I2C_CR1_ENARP (1 << 4)INT16_C__FLT32_HAS_QUIET_NAN__ 1__ATOMIC_RELEASE 3__HQ_IBIT__ 0long long intRCC_CIR_PLLRDYF (1 << 4)__SA_IBIT__ 16RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERSTRCC_CR_HSEON (1 << 16)BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)__UHA_FBIT__ 8RCC_BDCR MMIO32(RCC_BASE + 0x70)I2C_SR1_TIMEOUT (1 << 14)i2c_send_startRCC_CSR_PINRSTF (1 << 26)__ARM_FEATURE_CLZ 1INT_LEAST32_MAX__FLT64_MIN_10_EXP__ (-307)RCC_APB2LPENR_TIM1LPEN (1 << 0)RCC_AHB2LPENR_CRYPLPEN (1 << 4)__ARM_FEATURE_FMA 1__DEFINED_size_t RCC_APB1RSTR_TIM14RST (1 << 8)LIBOPENCM3_I2C_COMMON_V1_H __ARM_NEON_FP__FDPIC__RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffRCC_AHB1ENR_GPIOCEN (1 << 2)RCC_CIR_PLLSAIRDYIE (1 << 14)USART1_BASE (PERIPH_BASE_APB2 + 0x1000)__UFRACT_IBIT__ 0I2C2_FLTR I2C_FLTR(I2C2)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)RCC_AHB3LPENR_FSMCLPEN (1 << 0)RCC_AHB1ENR_GPIOBEN (1 << 1)__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)i2c_clear_dma_last_transferSIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_CKGATENR_SPARE_CKEN (1<<3)RCC_AHB1RSTR_GPIOJRST (1 << 9)__FLT32X_MIN_10_EXP__ (-307)INT16_MINRCC_CFGR_HPRE_MASK 0xfWCHAR_MAX __WCHAR_MAX____DEC_EVAL_METHOD__ 2INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1RCC_APB1RSTR_USART3RST (1 << 18)long unsigned intRCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)_GCC_SIZE_T RCC_CFGR_PPRE_DIV2 0x4I2C_CR1_POS (1 << 11)__SFRACT_MAX__ 0X7FP-7HRRCC_CIR_PLLI2SRDYIE (1 << 13)DBGMCU_BASE (PPBI_BASE + 0x00042000)TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)I2C_SR1_TxE (1 << 7)__SIZEOF_LONG_DOUBLE__ 8RCC_APB1ENR_TIM12EN (1 << 6)RCC_AHB1LPENR_IOPJLPEN RCC_AHB1LPENR_GPIOJLPEN__FLT64_HAS_DENORM__ 1RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1__FLT_HAS_DENORM__ 1RCC_APB2ENR_SPI5EN (1 << 20)i2c_enable_dmaUINT_LEAST8_MAX__THUMBEL__ 1RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPENRCC_PLLCFGR_PLLR_SHIFT 28I2C1_OAR2 I2C_OAR2(I2C1)RCC_AHB2RSTR_CRYPRST (1 << 4)RCC_AHB1LPENR_SRAM3LPEN (1 << 19)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0RCC_CFGR_MCO1_PLL 0x3__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_CIR_PLLI2SRDYC (1 << 21)__SIZEOF_FLOAT__ 4RCC_CFGR_MCO2_PLL 0x3FPB_BASE (PPBI_BASE + 0x2000)__SIZE_T__ __SIZE_TYPE__ unsigned intRCC_SSCGR_INCSTEP_MASK 0x7fffRCC_APB1ENR_TIM4EN (1 << 2)I2C_FLTR_DNF_SHIFT 0RCC_BDCR_LSEMOD (1 << 3)I2C3 I2C3_BASERCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRSTI2C_CR2_DMAEN (1 << 11)INT16_MIN (-INT16_MAX - 1)__LDBL_IS_IEC_60559__ 2RST_DSI__UFRACT_FBIT__ 16RCC_APB1LPENR_TIM12LPEN (1 << 6)RCC_APB1RSTR_CAN1RST (1 << 25)i2c_set_dma_last_transferID_BASE (SCS_BASE + 0x0FD0)RCC_AHB1ENR_IOPKEN RCC_AHB1ENR_GPIOKENRCC_CIR_HSIRDYC (1 << 18)RCC_AHB1LPENR_GPIOJLPEN (1 << 9)RCC_APB2LPENR_TIM11LPEN (1 << 18)__ARM_FEATURE_MVE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32I2C1_SR2 I2C_SR2(I2C1)RCC_BDCR_RTCSEL_LSI 2INT_FAST16_MAX __INT_FAST16_MAX__RCC_DCKCFGR_SAI1BSRC_MASK 0x3__ARM_FEATURE_CDE_COPROCLIBOPENCM3_I2C_H short int__GNUC_MINOR__ 2BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RST_I2C2RST_I2C3RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0INTMAX_MAX __INTMAX_MAX__TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)__UINT_LEAST16_TYPE__ short unsigned intRCC_APB1LPENR_I2C2LPEN (1 << 22)__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIENRCC_APB1ENR_UART7EN (1 << 30)RCC_APB1LPENR_UART4LPEN (1 << 19)RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__FLT_DENORM_MIN__ 1.4012984643248171e-45FRST_GPIOEINT_FAST32_MAX __INT_FAST32_MAX__UINTMAX_MAX __UINTMAX_MAX____DEFINED_ptrdiff_t RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT__UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 2__UINT32_MAX__ 0xffffffffULPWR_CR_VOS_MASK 0x3RCC_CIR_PLLSAIRDYF (1 << 6)PERIPH_BASE_AHB2 0x50000000U__UHA_IBIT__ 8I2C1_SR1 I2C_SR1(I2C1)__GNUC_PATCHLEVEL__ 1BIT2 (1<<2)GCC: (15:12.2.rel1-1) 12.2.1 20221205 | 0         (BV:AA3aeabi)7E-M M  ",  !!""##$$%%&&''(())**++,,--..//00224679;=Y[?ACEGIKMOQSUW]>o7k   : h \_     0      /Or      ! " #1$>%S &i 'x ( ) *+ , - . /0:2i2c_common_v1.c$t$dwm4.0.abb921a0aaad2653e18524772a7677abwm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.28.d4265628b39d8c27901d9acd2ab09e64wm4.stddef.h.39.14c6052d10f67a5d7cb73ea4beacde53wm4.i2c_common_v1.h.48.ad5b6f0c05f63ce10be04d3f69b9595dwm4.i2c.h.42.d60c91af2a3ac9e79c322e51073f6e61wm4.pwr_common_v1.h.34.5ba50cacb26c1962a4ec30bab2f0c81cwm4.pwr.h.49.809022926b9bde88f41e2ab32c7d2effwm4.rcc.h.55.7c6d4c25def1b1ac1cdf558eafc4ba01i2c_resetrcc_periph_reset_pulsei2c_peripheral_enablei2c_peripheral_disablei2c_send_starti2c_send_stopi2c_clear_stopi2c_set_own_7bit_slave_addressi2c_set_own_10bit_slave_addressi2c_set_own_7bit_slave_address_twoi2c_enable_dual_addressing_modei2c_disable_dual_addressing_modei2c_set_clock_frequencyi2c_send_datai2c_set_fast_modei2c_set_standard_modei2c_set_ccri2c_set_trisei2c_send_7bit_addressi2c_get_datai2c_enable_interrupti2c_disable_interrupti2c_enable_acki2c_disable_acki2c_nack_nexti2c_nack_currenti2c_set_dutycyclei2c_enable_dmai2c_disable_dmai2c_set_dma_last_transferi2c_clear_dma_last_transferi2c_transfer7i2c_set_speedy |\ |` }  & 2 G MMMJ"L&K-M4M;MBMGMZM_MmMrMMMMMMMMMMMMMMMMM MMM M'M.M5M<MCMJMQMXM_MfMmMtM{MMMMMMMMMMMMMMMMMMMMMMMM#M*M1M8M?MFMMMTM[MbMiMpMwM~MMMMMMMMMMMDMHHMHHD=DBD[H_HeDDDDMBMHHHHHHH HHH#BJBOBcHgHpHtH}HHBHHBBHHBBJHHHHHHH!H*B/BCHGHPHTH]HaHkB|HHBBBBBBMM0MGMSMuM{@M>M<M:M 8(M7M=6[Ma4M2M0M.MM,M+MJMaMmMzMMM$MMHHM" M  - MF MS MX t M~ H H M H H M  M  M  M H H H! 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