ELF(X4(CB !"#$%&'()*+,-./0123456780hAT,C,CCCCh CDCC`` 0h#c`pGhCc`pGE{ \  !}Mi$ 4`@jintWDz spiz!TP{o spio TPUSn( spiST brS,TQ?5S9TR SHT'#dffTT}hTT lV TJ:$ > :!; 9 I.?:!; 9!'@z:!; 9 I% Uy: ; 9 I$ > .?: ; 9 'I@z : ; 9 IB : ; 9 IB 4: ; 9 IB&P&(PS(STt @0 t @04! t @0q!4!t @0q!r!4!t @0q!r!s!4!tq!r!s!4!$T,( (  7?@  /  " $ $ 8  /\1 #Q%#![X JQ"~%>G;FHZHWoel p$v)-{Qca8j]\SA[|*^k$* pvm.  q3QR4vA `{%HamvFWlV TCCG$+z3z(1aY2k:3cbLyfB ASKNeqctPPb7]@DwI.&<1<z=d?1͓j: /D{?P8  }?2ikFYo%v@~/OpOuZYBMGX[Wj$ eKj;,#3x1{@]79tzieOGHUbX?"0 xg ^ ]4/UK  L`|-+Ies6NFkERfP `H 3 zSF؅ 6 ,XvP#M HPOXrWiR;nZ>7!1t _ P$N9w5S@;-\. |;"i%C%U|d,vRKpQd?Z9^ۗ%qmzpHyǒ I04gkyg5XZx>f|\h?@Ky3iHXW#mDNkLp\vC1W"'ȃ='2uɏAkq '$Z>LV@l;'v8UHns$bO"t@166al"]*|(~d z<!(t *gj]qGg"4wLO5*=g}@*QZu=Ihфb@G>d)ANY-=,w+^> Q!#;_Mk 't3c~8YO_A`eZkx:.T<t,77,[p~[T|284Eqtj3Z'!r"w$)ddH!eFf\gejkn$No9ptqL;tPu6xhyKz{ ~9Ray $J\3)l2ulZ#) CZ]kd2BDN%tYW~kq#eid<V<?G^.\j')ChtB( xR P-S>T.N-`!TH# x\PaQ!D7Cp"*cdw K6rF@*$]{a]Z_ryn!mD+z^)zkKCkt >2]!|7&( 'U2؏C6DJE#Fx`I8LQR*S~TMUVWNX@YZO[2\]d]<^n_o@`fa]bLcCdwieAfggh@iCj*jk6l% mGnloDp~4E=X"%R*50{8=x?J@pB.CsJD5PEgI\JpLp M4.O;PTQRfTV:WXYZҍ[d\\s],_fs`_,aEbWDc>g<h&itwj4kl+m0nwo%Gp˕qs)u2v(wx|y(zy|<}0? c..:V!7o5xf  @xn[UG$0a6+)6hUj!/.m/i`012ܓ32:;?f@KATBDy'G3JgM kP|SEZT_ bue#41 27n>0CUH7E_9;A;=eS?AD`CEFH1LH2NLP%:SU` Y[]e`JbfNh%l/nUp0Drtvx}~:9CmpY^^.H3):<`R2^CMb QzA t\EuƁa=ro0aVh=}6OyX%Ysk|uO7 >/up\-J3RɐnAKc#j#/b&KOSg!MLs>0g;HTWŊ4(<u 47fL(Xwdud'7#D8;j/ Ob` nv)e3 mBNLv I: ىMA{h+4K:[N]{ ]IwH!i &D5i j^g%MHsߘMne618~JeVa݁wWbi8XI:4QRȆZ1zA<c18RGH96iT>])sK'˔qI-}WN*vuC&`NY"h3p*RyER0!L1]uRE}Ls;%W0oQ~m].n;/ h[B)\uh }cq'?yNEY{{tl6&@vdo(BU"d_3Kr-\,Jo4$fAdGS9N,yZx4.>*Sq=gh~GɈwIvbFy?RaVieSS&kz2m_= |UV;CA=O"i=ZCa<lw n_-#F Ob&2,HbaJ/-9'^=v^A IAmR?Yno6h7oBMq5f7j5W}x>BrvJZcaF ,[Xl$d &*Yfr{1"W_PQV^i_֑r?Y&rBVh W_t.KFDro-;}}3E/8{g3MYl6Rf ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/f4../../../include/libopencm3/stm32/commonspi_common_v1.cstdint.hspi.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hspi.hspi_common_v1_frf.hspi_common_v1.hspi_common_all.hrcc.hrcc.hpwr.hpwr.hpwr_common_v1.hrcc_common_all.h! #y .  J 0="  = =RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1SCB_BASE (SCS_BASE + 0x0D00)RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPEN__UHA_FBIT__ 8SPI_I2SCFGR_DATLEN_LSB 1RCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGENRCC_CIR_LSERDYIE (1 << 9)RCC_APB2LPENR_SAI1LPEN (1 << 22)RCC_APB2LPENR_USART1LPEN (1 << 4)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRSTCORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CIR_LSIRDYF (1 << 0)__CHAR_UNSIGNED__ 1RCC_AHB1ENR_CCMDATARAMEN (1 << 20)RCC_CSR_LSION (1 << 0)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)RCC_CR_HSIRDY (1 << 1)RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)RCC_CSR_LPWRRSTF (1 << 31)__FLT64_HAS_INFINITY__ 1ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)RCC_APB2RSTR_TIM11RST (1 << 18)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKINT64_MAX __INT64_MAX____PTRDIFF_MAX__ 0x7fffffffRCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)__ARM_FEATURE_FMA 1RCC_APB1RSTR_CAN1RST (1 << 25)SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)RCC_APB1RSTR_I2C3RST (1 << 23)__INTMAX_MAX__ 0x7fffffffffffffffLLRCC_APB1ENR_TIM14EN (1 << 8)RCC_AHB2ENR_DCMIEN (1 << 0)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17RCC_APB2ENR_TIM11EN (1 << 18)WINT_MIN __WINT_MIN__INT_FAST64_MAXSPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUSPI2_DR SPI_DR(SPI2_BASE)LIBOPENCM3_RCC_COMMON_ALL_H RCC_APB1LPENR_TIM3LPEN (1 << 1)RCC_BDCR_LSERDY (1 << 1)RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)RCC_APB2LPENR_SYSCFGLPEN (1 << 14)GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)INTMAX_MIN__SIZEOF_LONG_LONG__ 8SPI_CR1_MSTR (1 << 2)__DBL_MAX_10_EXP__ 308RCC_CR_PLLSAIRDY (1 << 29)RCC_CFGR_MCOPRE_DIV_2 0x4__FRACT_MIN__ (-0.5R-0.5R)RCC_CIR_PLLRDYF (1 << 4)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKPWR_CR_LPDS (1 << 0)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64RCC_AHB1LPENR_DMA2DLPEN (1 << 23)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))__SIZE_TYPE__ unsigned intSPI_CR1_BR_FPCLK_DIV_8 0x2RCC_CIR_PLLRDYIE (1 << 12)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0__USACCUM_MIN__ 0.0UHKRCC_AHB1RSTR_IOPJRST RCC_AHB1RSTR_GPIOJRST__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)RCC_APB1LPENR_I2C3LPEN (1 << 23)__LDBL_MANT_DIG__ 53SPI_SR_CRCERR (1 << 4)INT64_MIN (-INT64_MAX - 1)RCC_APB1LPENR_SPI3LPEN (1 << 15)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1RCC_APB1ENR_UART8EN (1 << 31)__FLT64_MAX__ 1.7976931348623157e+308F64SPI_CR1_RXONLY (1 << 10)RCC_DCKCFGR_SAI1SRC_SAIQ 0x0UINT_FAST32_MAXSPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPENSPI_I2SPR_ODD (1 << 8)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1PWR_CSR_PVDO (1 << 2)RCC_PLLCFGR_PLLN_MASK 0x1ff__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RCC_AHB1RSTR_DMA2DRST (1 << 23)__SIG_ATOMIC_TYPE__ intI2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)USART1_BASE (PERIPH_BASE_APB2 + 0x1000)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intRCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRSTINT32_MIN (-INT32_MAX - 1)USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)__FLT32_MAX_10_EXP__ 38RCC_APB2ENR MMIO32(RCC_BASE + 0x44)QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)__USFRACT_MAX__ 0XFFP-8UHRRCC_AHB1RSTR_OTGHSRST (1 << 29)__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffU../common/spi_common_v1.cRCC_CFGR_MCO1PRE_MASK 0x7__FLT32_MIN_EXP__ (-125)RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERSTRCC_CIR_HSIRDYC (1 << 18)SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)SPI_I2SCFGR_I2SCFG_LSB 8SPI_CR1_BR_FPCLK_DIV_128 0x6UINT32_MAX __UINT32_MAX__RCC_APB2ENR_SPI6EN (1 << 21)RCC_APB1ENR_UART4EN (1 << 19)RCC_APB2RSTR_SPI4RST (1 << 13)PWR_CR_PDDS (1 << 1)__ULFRACT_FBIT__ 32RCC_AHB3RSTR_QSPIRST (1 << 1)__FLT64_MIN_10_EXP__ (-307)RCC_AHB1RSTR_DMA1RST (1 << 21)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"__HA_FBIT__ 7BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_CFGR_HPRE_SHIFT 4RCC_SSCGR_INCSTEP_SHIFT 13cpha__SFRACT_EPSILON__ 0x1P-7HRRCC_AHB1LPENR_GPIOELPEN (1 << 4)RCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEEN__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)SPI_I2SPR_MCKOE (1 << 9)FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)SPI3_CR1 SPI_CR1(SPI3_BASE)__UHQ_FBIT__ 16RCC_APB2ENR_ADC2EN (1 << 9)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)__PTRDIFF_WIDTH__ 32RCC_AHB1LPENR_SRAM2LPEN (1 << 17)RCC_CFGR_MCO1_PLL 0x3__UINT_FAST8_MAX__ 0xffffffffURCC_APB1LPENR_TIM14LPEN (1 << 8)RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)UINT16_C(c) __UINT16_C(c)RCC_APB1LPENR_USART2LPEN (1 << 17)__LACCUM_IBIT__ 32SPI_CR1_BR_FPCLK_DIV_256 0x7__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"RCC_AHB1LPENR_GPIOJLPEN (1 << 9)__VFP_FP__ 1SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXRCC_CIR_HSERDYC (1 << 19)RCC_APB1ENR_I2C3EN (1 << 23)__UINT_FAST16_MAX__ 0xffffffffURCC_APB1LPENR_UART7EN (1 << 30)QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)INT64_C(c) __INT64_C(c)SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2__INTPTR_MAX__ 0x7fffffffRCC_AHB2LPENR_OTGFSLPEN (1 << 7)SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)SPI4 SPI4_BASERCC_CFGR_MCO1_HSI 0x0WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)__UINT_LEAST8_TYPE__ unsigned charRCC_AHB1RSTR_GPIODRST (1 << 3)SPI_DR(spi_base) MMIO32((spi_base) + 0x0c)RCC_APB2LPENR_DSILPEN (1 << 27)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_APB2RSTR_TIM8RST (1 << 1)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODEN__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_BDCR_RTCEN (1 << 15)RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32RCC_AHB2ENR_OTGFSEN (1 << 7)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)__GCC_ATOMIC_BOOL_LOCK_FREE 2RCC_CFGR_SW_HSE 0x1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRTIM1_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_AHB1RSTR_IOPKRST RCC_AHB1RSTR_GPIOKRSTshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)RCC_AHB1LPENR_FLITFLPEN (1 << 15)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_PLLI2SCFGR_PLLI2SQ_MASK 0xfLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CIR_HSERDYF (1 << 3)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)RCC_APB1ENR_TIM4EN (1 << 2)RCC_APB1LPENR_DACLPEN (1 << 29)SPI_CR1_MSBFIRST (0 << 7)RCC_APB1ENR_SPI3EN (1 << 15)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RCC_AHB1LPENR_GPIOFLPEN (1 << 5)__FLT32X_MIN_EXP__ (-1021)SPI_I2SCFGR_DATLEN_32BIT 0x2RCC_DCKCFGR_SDMMCSEL (1 << 28)PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)RCC_BDCR_RTCSEL_NONE 0RCC_CKGATENR_AHB2APB2_CKEN (1<<1)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)RCC_CIR_CSSF (1 << 7)SPI_CR1_DFF_8BIT (0 << 11)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_CIR_LSERDYC (1 << 17)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charRCC_CFGR_HPRE_DIV512 (0x8 + 7)SPI_SR_BSY (1 << 7)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRSTFMC_BANK1 (PERIPH_BASE_AHB3)__GNUC_STDC_INLINE__ 1SPI_CR1_BIDIMODE (1 << 15)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKRCC_PLLSAICFGR_PLLSAIQ_SHIFT 24__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINRCC_AHB1ENR_CRCEN (1 << 12)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)RCC_AHB3LPENR_QSPIEN (1 << 1)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77RCC_CFGR_HPRE_DIV_512 (0x8 + 7)__LACCUM_FBIT__ 31RCC_CFGR_PPRE_DIV16 0x7RCC_CFGR_PPRE_DIV8 0x6__FLT64_MAX_10_EXP__ 308RCC_APB1LPENR_UART5LPEN (1 << 20)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)SPI_CR1_LSBFIRST (1 << 7)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)SPI1_DR SPI_DR(SPI1_BASE)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RCC_CSR MMIO32(RCC_BASE + 0x74)RCC_CFGR_HPRE_DIV2 (0x8 + 0)SPI_SR_TXE (1 << 1)RCC_APB1ENR_TIM12EN (1 << 6)RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPENSPI_I2SCFGR_DATLEN_24BIT 0x1RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRSTGPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_APB1ENR_UART5EN (1 << 20)__USQ_FBIT__ 32RCC_APB2RSTR_SDIORST (1 << 11)INT_FAST16_MINPWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)SPI_SR_UDR (1 << 3)RCC_CFGR_HPRE_DIV_256 (0x8 + 6)__thumb2__ 1__ULLACCUM_FBIT__ 32RCC_APB2LPENR_SPI5LPEN (1 << 20)RCC_APB1ENR_TIM2EN (1 << 0)RCC_CFGR_PPRE_DIV_2 0x4RCC_CFGR_HPRE_DIV_2 (0x8 + 0)PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)UINT_LEAST8_MAXINT_LEAST8_MAXRCC_APB1ENR_PWREN (1 << 28)UINT8_C(c) __UINT8_C(c)RCC_CIR_HSIRDYIE (1 << 10)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)RCC_CR_HSITRIM_SHIFT 3ST_VREFINT_CAL MMIO16(0x1FFF7A2A)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1RCC_AHB1ENR_GPIOIEN (1 << 8)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6UART5_BASE (PERIPH_BASE_APB1 + 0x5000)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)RCC_AHB1RSTR_GPIOHRST (1 << 7)__UINT_FAST64_TYPE__ long long unsigned intSPI_CR1_BIDIOE (1 << 14)GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)RCC_SSCGR_SSCGEN (1 << 31)__FLT_MIN__ 1.1754943508222875e-38FSPI6_BASE (PERIPH_BASE_APB2 + 0x5400)__FDPIC____UFRACT_MIN__ 0.0URRCC_APB1LPENR_TIM12LPEN (1 << 6)TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)__FLT32_IS_IEC_60559__ 2SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c)SPI_I2SCFGR_I2SE (1 << 10)INT_FAST64_MINRCC_APB1LPENR_I2C1LPEN (1 << 21)__USFRACT_IBIT__ 0RCC_CFGR_RTCPRE_SHIFT 16RCC_AHB1ENR_OTGHSULPIEN (1 << 30)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_APB2LPENR_LTDCLPEN (1 << 26)RCC_AHB3ENR_QSPIEN (1 << 1)USART6_BASE (PERIPH_BASE_APB2 + 0x1400)__USFRACT_MIN__ 0.0UHRSPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)__ARM_NEONDCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)__UINT8_MAX__ 0xffSPI_I2SCFGR_DATLEN_16BIT 0x0RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16RCC_CKGATENR_RCC_CKEN (1<<6)__LDBL_MAX_EXP__ 1024RCC_APB1LPENR_TIM2LPEN (1 << 0)RCC_CIR_PLLRDYC (1 << 20)LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfLIBOPENCM3_SPI_COMMON_ALL_H RCC_SSCGR MMIO32(RCC_BASE + 0x80)SPI_CR2_FRF_TI_MODE (1 << 4)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_AHB1ENR_GPIOEEN (1 << 4)RCC_CFGR_MCO2_PLL 0x3SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)PWR_CSR_VOSRDY (1 << 14)RCC_CFGR_SWS_HSE 0x1GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)SPI_CR2_SSOE (1 << 2)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRCC_APB1RSTR_TIM5RST (1 << 3)__FLT_DENORM_MIN__ 1.4012984643248171e-45FRCC_AHB1ENR_GPIOCEN (1 << 2)PERIPH_BASE_AHB3 0x60000000URCC_APB2RSTR MMIO32(RCC_BASE + 0x24)RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)__ULLACCUM_EPSILON__ 0x1P-32ULLKRCC_AHB1ENR MMIO32(RCC_BASE + 0x30)INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_APB1LPENR_TIM13LPEN (1 << 7)RCC_PLLCFGR_PLLR_SHIFT 28__UINT32_C(c) c ## ULRCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FRCC_CFGR_RTCPRE_MASK 0x1fLPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CKGATENR_SPARE_CKEN (1<<3)PWR_CR_PVDE (1 << 4)RCC_APB2ENR_TIM10EN (1 << 17)__ARM_ARCH_ISA_THUMBRCC_CR_HSEON (1 << 16)RCC_CFGR_PPRE_DIV_16 0x7PWR_CSR_WUF (1 << 0)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charRCC_APB2ENR_SDIOEN (1 << 11)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB1LPENR_OTGHSLPEN (1 << 29)RCC_APB1RSTR_TIM13RST (1 << 7)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1cpolRCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRSTFMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)SCS_BASE (PPBI_BASE + 0xE000)RCC_BDCR_RTCSEL_LSI 2RCC_BDCR_LSEBYP (1 << 2)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__LDBL_HAS_INFINITY__ 1RCC_APB2LPENR_TIM1LPEN (1 << 0)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))RCC_APB1RSTR_CAN2RST (1 << 26)__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1RCC_CFGR_MCO1_MASK 0x3RCC_BDCR_RTCSEL_HSE 3bool _BoolSPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)UINTMAX_MAX __UINTMAX_MAX__RCC_BDCR_RTCSEL_SHIFT 8__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)RCC_CKGATENR_FLITF_CKEN (1<<5)RCC_APB2RSTR_SAI1RST (1 << 22)__UINT_LEAST8_MAX__ 0xffRCC_APB1RSTR_SPI2RST (1 << 14)RCC_CIR_PLLSAIRDYC (1 << 22)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1RCC_APB2RSTR_SPI5RST (1 << 20)PWR_CR_DBP (1 << 8)SPI2_CR2 SPI_CR2(SPI2_BASE)__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RCC_APB2LPENR_SPI6LPEN (1 << 21)UINT32_MAXRCC_AHB1RSTR_GPIOFRST (1 << 5)RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)RCC_AHB1RSTR_ETHMACRST (1 << 25)__INT_LEAST16_WIDTH__ 16RCC_CR_HSITRIM_MASK 0x1fRCC_APB1RSTR_TIM14RST (1 << 8)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLRCC_CR_PLLSAION (1 << 28)RCC_AHB3ENR_FMCEN (1 << 0)RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8INT16_MIN (-INT16_MAX - 1)RCC_CFGR_SWS_PLL 0x2__USFRACT_EPSILON__ 0x1P-8UHRRCC_CIR_PLLI2SRDYC (1 << 21)__USFRACT_FBIT__ 8RCC_AHB2LPENR_RNGLPEN (1 << 6)CORESIGHT_LSR_SLI (1<<0)RCC_CFGR_PPRE_DIV_4 0x5__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____ARM_ARCH_7EM__ 1__UINT32_MAX__ 0xffffffffULRCC_APB2RSTR_DSIRST (1 << 27)RCC_APB1LPENR_CAN2LPEN (1 << 26)GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB2LPENR_TIM10LPEN (1 << 17)RCC_AHB2LPENR_CRYPLPEN (1 << 4)RCC_CFGR_MCO2_SYSCLK 0x0__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)RCC_APB2RSTR_TIM9RST (1 << 16)RCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)RCC_CFGR_MCO1_LSE 0x1RCC_CSR_IWDGRSTF (1 << 29)__UINT_LEAST32_MAX__ 0xffffffffULDMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_DCKCFGR_48MSEL (1 << 27)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16SPI_I2SCFGR_PCMSYNC (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_PLLCFGR MMIO32(RCC_BASE + 0x04)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_APB1RSTR_TIM2RST (1 << 0)RCC_APB2LPENR_SPI1LPEN (1 << 12)RCC_PLLCFGR_PLLN_SHIFT 6TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)RCC_CSR_SFTRSTF (1 << 28)UINT_LEAST16_MAX __UINT_LEAST16_MAX__SPI_CR2_FRF (1 << 4)RCC_CIR_PLLSAIRDYF (1 << 6)INT_FAST32_MINSPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_DCKCFGR_SAI1BSRC_MASK 0x3__SCHAR_WIDTH__ 8INT_LEAST16_MAXBIT18 (1<<18)UINT_FAST16_MAXRCC_CR_PLLI2SRDY (1 << 27)__UINT_FAST8_TYPE__ unsigned intRCC_AHB1ENR_ETHMACEN (1 << 25)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RSPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1BIT24 (1<<24)RCC_AHB2LPENR_HASHLPEN (1 << 5)__INT32_MAX__ 0x7fffffffLRCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)LTDC_BASE (PERIPH_BASE_APB2 + 0x6800)SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1UINTMAX_MAXspi_set_dff_16bitBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CIR_CSSC (1 << 23)__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_CKGATENR_EVTCL_CKEN (1<<7)RCC_AHB1ENR_IOPKEN RCC_AHB1ENR_GPIOKENSPI_CR1_BR_FPCLK_DIV_4 0x1PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_AHB1ENR_GPIOFEN (1 << 5)SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32SPI_SR_TIFRFE (1 << 8)RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_APB1LPENR_UART4LPEN (1 << 19)INT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)RCC_APB2RSTR_SPI6RST (1 << 21)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2DESIG_UNIQUE_ID_BASE (0x1FFF7A10U)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long intRCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_APB1LPENR_TIM7LPEN (1 << 5)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXSPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2RCC_APB2LPENR_ADC3LPEN (1 << 10)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_APB1RSTR_WWDGRST (1 << 11)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1RCC_AHB1LPENR_CRCLPEN (1 << 12)__ULLFRACT_IBIT__ 0RCC_APB2RSTR_TIM1RST (1 << 0)MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APB2ENR_SPI1EN (1 << 12)PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12RCC_CSR_BORRSTF (1 << 25)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)WCHAR_MAXRCC_CFGR_HPRE_DIV4 (0x8 + 1)RCC_AHB1RSTR_GPIOGRST (1 << 6)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)RCC_CFGR_PPRE_NODIV 0x0__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0URCC_AHB1ENR_GPIODEN (1 << 3)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4RCC_AHB1ENR_IOPJEN RCC_AHB1ENR_GPIOJEN__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKRCC_CIR_HSIRDYF (1 << 2)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7RCC_AHB2RSTR_HASHRST (1 << 5)RCC_PLLCFGR_PLLQ_SHIFT 24SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55RCC_AHB1RSTR_GPIOJRST (1 << 9)RCC_CKGATENR_CM4DBG_CKEN (1<<2)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXRCC_APB2ENR_USART1EN (1 << 4)RCC_AHB1ENR_ETHMACPTPEN (1 << 28)RCC_APB1ENR_USART3EN (1 << 18)__LDBL_HAS_QUIET_NAN__ 1RCC_BDCR MMIO32(RCC_BASE + 0x70)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_AHB1ENR_DMA1EN (1 << 21)RCC_CFGR_HPRE_DIV8 (0x8 + 2)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CIR_LSIRDYC (1 << 16)RCC_APB1LPENR_SPI2LPEN (1 << 14)BIT9 (1<<9)RCC_AHB2LPENR_DCMILPEN (1 << 0)__FLT32X_MIN__ 2.2250738585072014e-308F32xUART7_BASE (PERIPH_BASE_APB1 + 0x7800)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXSPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRCC_AHB2ENR_RNGEN (1 << 6)__ARM_ARCH_PROFILE__INT64_TYPE__ long long intRCC_PLLSAICFGR_PLLSAIP_MASK 0x3__LFRACT_FBIT__ 31__CHAR_BIT__ 8RCC_APB1RSTR_TIM12RST (1 << 6)__SIZEOF_WCHAR_T__ 4SPI_CR1_SPE (1 << 6)SPI_CR1_SSM (1 << 9)LIBOPENCM3_PWR_H RCC_AHB1ENR_GPIOHEN (1 << 7)__FLT32X_MANT_DIG__ 53_REG_BITRCC_AHB1LPENR_GPIOGLPEN (1 << 6)RCC_CR_HSION (1 << 0)__UFRACT_MAX__ 0XFFFFP-16URRCC_APB1RSTR_TIM7RST (1 << 5)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2LPENR_ADC1LPEN (1 << 8)RCC_CFGR_PPRE2_SHIFT 13INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_APB2ENR_USART6EN (1 << 5)RCC_CIR MMIO32(RCC_BASE + 0x0c)RCC_CFGR_HPRE_DIV64 (0x8 + 4)STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)RCC_CFGR_SW_HSI 0x0ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)DESIG_FLASH_SIZE_BASE (0x1FFF7A22U)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPENRCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)__LDBL_MAX_10_EXP__ 308PWR_CSR_BRE (1 << 9)RCC_APB2ENR_LTDCEN (1 << 26)RCC_DCKCFGR_SAI1ASRC_SHIFT 20HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)RCC_CFGR_MCO2PRE_SHIFT 27SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)__INT_FAST32_TYPE__ intRCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPENSPI_CR1_DFF (1 << 11)unsigned intSPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_PLLSAICFGR_PLLSAIQ_MASK 0xFRCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBENRCC_DCKCFGR_SAI1SRC_I2SQ 0x1RCC_CFGR_SW_PLL 0x2__USACCUM_IBIT__ 8SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)ITM_BASE (PPBI_BASE + 0x0000)RCC_SSCGR_SPREADSEL (1 << 30)RCC_CFGR_MCOPRE_DIV_3 0x5__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKRCC_CFGR_HPRE_DIV_4 (0x8 + 1)SPI2_CR1 SPI_CR1(SPI2_BASE)__FLT_EVAL_METHOD__ 0RCC_CFGR_MCOPRE_DIV_5 0x7RCC_APB2LPENR_USART6LPEN (1 << 5)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RCC_AHB1ENR_BKPSRAMEN (1 << 18)RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ffRCC_CR_PLLON (1 << 24)__ARM_FEATURE_LDREXRCC_APB2ENR_TIM1EN (1 << 0)__UQQ_FBIT__ 8STM32F4 1RCC_APB1LPENR_UART8EN (1 << 31)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4RCC_APB1ENR_DACEN (1 << 29)__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0SPI_CR1_CRCEN (1 << 13)RCC_AHB1RSTR_GPIOERST (1 << 4)__ARM_FEATURE_COPROC 15RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASKRCC_APB2ENR_SPI4EN (1 << 13)UINT64_MAX __UINT64_MAX__TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_PLLCFGR_PLLM_MASK 0x3fINT8_MIN__ORDER_PDP_ENDIAN__ 3412/build/libopencm3/lib/stm32/f4LIBOPENCM3_RCC_H PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_AHB1RSTR_GPIOCRST (1 << 2)RCC_AHB2ENR_CRYPEN (1 << 4)INT8_C__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_CR_CSSON (1 << 19)RCC_PLLCFGR_PLLR_MASK 0x7__LFRACT_EPSILON__ 0x1P-31LRRCC_PLLSAICFGR_PLLSAIP_DIV2 0x0RCC_APB2LPENR_TIM9LPEN (1 << 16)RCC_APB2LPENR_TIM11LPEN (1 << 18)SPI_SR_OVR (1 << 6)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_APB2ENR_SPI5EN (1 << 20)RCC_DCKCFGR_SAI1SRC_ALT 0x2RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPENRCC_PLLSAICFGR_PLLSAIP_SHIFT 16RCC_PLLSAICFGR_PLLSAIN_SHIFT 6__FLT32_MIN_10_EXP__ (-37)RCC_AHB1ENR_DMA2DEN (1 << 23)RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)SPI2 SPI2_BASEMMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINSPI_I2SCFGR_I2SSTD_LSB 4DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)RCC_APB1LPENR_PWRLPEN (1 << 28)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RCC_APB1RSTR_UART4RST (1 << 19)RCC_APB1LPENR_TIM4LPEN (1 << 2)__TA_IBIT__ 64RCC_AHB1LPENR_GPIOCLPEN (1 << 2)RCC_APB1LPENR_WWDGLPEN (1 << 11)SPI_CR2_TXDMAEN (1 << 1)SPI_CR1_DFF_16BIT (1 << 11)RCC_APB1RSTR_SPI3RST (1 << 15)RCC_AHB1LPENR_GPIOKLPEN (1 << 10)RCC_CIR_PLLI2SRDYIE (1 << 13)RCC_PLLCFGR_PLLQ_MASK 0xf__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_APB1LPENR_TIM5LPEN (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CSR_RMVF (1 << 24)__WINT_WIDTH__ 32RCC_CFGR_PPRE_DIV4 0x5SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)RCC_APB2RSTR_LTDCRST (1 << 26)RCC_APB1ENR_TIM5EN (1 << 3)RCC_SSCGR_MODPER_MASK 0x1fffRCC_APB2ENR_ADC1EN (1 << 8)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_CFGR_HPRE_DIV_16 (0x8 + 3)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)RCC_APB1RSTR_I2C1RST (1 << 21)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1RCC_AHB1LPENR_IOPKLPEN RCC_AHB1LPENR_GPIOKLPENRCC_CIR_LSIRDYIE (1 << 8)INT8_MIN (-INT8_MAX - 1)RCC_APB1RSTR_DACRST (1 << 29)SPI2_CRCPR SPI_CRCPR(SPI2_BASE)RCC_CFGR_HPRE_DIV_NONE 0x0__FLT32_DIG__ 6SPI_CR1_CPHA (1 << 0)FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)SPI1_SR SPI_SR(SPI1_BASE)PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)BIT15 (1<<15)ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)RCC_CFGR_HPRE_DIV256 (0x8 + 6)RCC_AHB1LPENR_DMA2LPEN (1 << 22)RCC_AHB2RSTR_RNGRST (1 << 6)RCC_CKGATENR_SRAM_CKEN (1<<4)PWR_CR_CSBF (1 << 3)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXRCC_BDCR_BDRST (1 << 16)ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C)__ACCUM_MIN__ (-0X1P15K-0X1P15K)lsbfirstRCC_CFGR_MCO2PRE_MASK 0x7RCC_DCKCFGR_SAI1ASRC_MASK 0x3__ARM_FEATURE_CRYPTORCC_APB1ENR_UART7EN (1 << 30)RCC_AHB1ENR_GPIOKEN (1 << 10)UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)RCC_APB2RSTR_TIM10RST (1 << 17)RCC_AHB1LPENR_GPIOBLPEN (1 << 1)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2RCC_AHB2RSTR_OTGFSRST (1 << 7)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E)SPI_CR1_BR_FPCLK_DIV_2 0x0__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_BDCR_LSEMOD (1 << 3)long long unsigned int__FLT_MIN_10_EXP__ (-37)PWR_CR_CWUF (1 << 2)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intRCC_CFGR_PLLSRC_HSI_CLK 0x0__APCS_32__ 1__DQ_FBIT__ 63SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)INT_LEAST64_MAX__SACCUM_IBIT__ 8SPI_CR2_RXNEIE (1 << 6)reg32_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINRCC_APB1LPENR_CAN1LPEN (1 << 25)BIT29 (1<<29)RCC_APB1ENR_TIM13EN (1 << 7)__INT_FAST16_TYPE__ intSPI3_I2SPR SPI_I2SPR(SPI3_BASE)SPI1 SPI1_BASEINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_APB2LPENR_ADC2LPEN (1 << 9)__UINT_LEAST16_TYPE__ short unsigned intRCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_AHB3ENR_FSMCEN (1 << 0)RCC_CIR_HSERDYIE (1 << 11)__FLT32X_DIG__ 15RCC_APB1RSTR_UART8RST (1 << 31)SPI_I2SCFGR_CHLEN (1 << 0)RCC_APB1LPENR_I2C2LPEN (1 << 22)SPI3_CRCPR SPI_CRCPR(SPI3_BASE)__UTQ_FBIT__ 128PWR_CR_FPDS (1 << 9)RCC_CFGR_PPRE1_SHIFT 10SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN__FINITE_MATH_ONLY__ 0RCC_APB2LPENR_TIM8LPEN (1 << 1)__INT_FAST16_MAX__ 0x7fffffffRCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3RCC_APB1ENR_TIM3EN (1 << 1)RCC_BDCR_RTCSEL_MASK 0x3PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_AHB1ENR_GPIOJEN (1 << 9)PERIPH_BASE_AHB2 0x50000000URCC_CR_PLLRDY (1 << 25)RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKTIM8_BASE (PERIPH_BASE_APB2 + 0x0400)BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)__ULFRACT_MIN__ 0.0ULRPWR_CR_PLS_LSB 5RCC_BDCR_RTCSEL_LSE 1RCC_APB1ENR_I2C1EN (1 << 21)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB1LPENR_ETHMACLPEN (1 << 25)SPI_SR_MODF (1 << 5)RCC_APB2RSTR_USART1RST (1 << 4)WCHAR_MINRCC_DCKCFGR_SAI1BSRC_SHIFT 22RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0RCC_PLLSAICFGR_PLLSAIR_SHIFT 28RCC_CSR_PORRSTF (1 << 27)BEGIN_DECLS RCC_APB2ENR_SYSCFGEN (1 << 14)RCC_CFGR_MCO2_PLLI2S 0x1RCC_DCKCFGR_DSISEL (1 << 29)RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHENRCC_APB2RSTR_SPI1RST (1 << 12)RCC_AHB2RSTR_CRYPRST (1 << 4)SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)SPI1_CR2 SPI_CR2(SPI1_BASE)SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xSPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)RCC_PLLCFGR_PLLM_SHIFT 0__ARM_EABI__ 1RCC_DCKCFGR_SAI1SRC_ERROR 0x3INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1RCC_CFGR_MCO1_SHIFT 21__ARM_FEATURE_DSP 1RCC_CFGR_MCO1_HSE 0x2RCC_CFGR_MCO2_SHIFT 30RCC_APB1ENR_CAN2EN (1 << 26)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_CFGR_HPRE_DIV_64 (0x8 + 4)RCC_AHB1ENR_GPIOAEN (1 << 0)PWR_CSR_SBF (1 << 1)RCC_CFGR_PPRE_DIV_8 0x6SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)RCC_APB1ENR_TIM7EN (1 << 5)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0RCC_CSR_PINRSTF (1 << 26)__UINT_LEAST32_TYPE__ long unsigned intRCC_CIR_LSERDYF (1 << 1)I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)__ARM_FEATURE_NUMERIC_MAXMINRCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRSTGPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB1RSTR_USART2RST (1 << 17)INTMAX_MAXFMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000)FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)__ARM_FEATURE_FP16_SCALAR_ARITHMETICUINT_FAST32_MAX __UINT_FAST32_MAX____USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94)RCC_AHB1ENR_GPIOGEN (1 << 6)RCC_APB2ENR_TIM8EN (1 << 1)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSPI2_SR SPI_SR(SPI2_BASE)RCC_AHB1LPENR_GPIOHLPEN (1 << 7)DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)INT64_MINSPI_CR2_ERRIE (1 << 5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRCC_PLLCFGR_PLLP_MASK 0x3RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPENUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_AHB1RSTR_GPIOBRST (1 << 1)__SIZEOF_SIZE_T__ 4RCC_AHB1RSTR_GPIOIRST (1 << 8)__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLRCC_APB1ENR_WWDGEN (1 << 11)spi_set_dff_8bitTPIU_BASE (PPBI_BASE + 0x40000)RCC_APB1ENR_SPI2EN (1 << 14)__LDBL_MIN__ 2.2250738585072014e-308LPWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_CFGR_PLLSRC_HSE_CLK 0x1__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"SPI3_DR SPI_DR(SPI3_BASE)CORESIGHT_LAR_OFFSET 0xfb0RCC_APB1ENR_I2C2EN (1 << 22)RCC_CFGR_MCO1PRE_SHIFT 24RCC_BDCR_LSEON (1 << 0)SPI_CR1_BR_FPCLK_DIV_16 0x3RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1fshort intRCC_AHB1ENR_OTGHSEN (1 << 29)RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f__UINT16_C(c) cSPI_SR_RXNE (1 << 0)BIT31 (1<<31)__UDA_IBIT__ 32RCC_APB1RSTR_I2C2RST (1 << 22)UINT_LEAST32_MAXRCC_AHB1LPENR_DMA1LPEN (1 << 21)BIT2 (1<<2)RCC_AHB2ENR_HASHEN (1 << 5)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCTIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)RCC_APB1RSTR_UART7RST (1 << 30)__DBL_HAS_INFINITY__ 1FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)__SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53PWR_CSR_BRR (1 << 3)GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)BIT5 (1<<5)RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7BIT1 (1<<1)BIT26 (1<<26)INT_LEAST32_MAXPWR_CSR_EWUP (1 << 8)__USES_INITFINI__ 1SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14)SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)SPI_SR_CHSIDE (1 << 2)__DBL_DECIMAL_DIG__ 17LIBOPENCM3_SPI_H BIT8 (1<<8)PWR_CR_VOS_SHIFT 14SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)INT16_C(c) __INT16_C(c)RCC_CFGR_HPRE_DIV_8 (0x8 + 2)RCC_CIR_PLLI2SRDYF (1 << 5)__INT16_MAX__ 0x7fffRCC_CFGR_MCO2_MASK 0x3RCC_APB1RSTR_USART3RST (1 << 18)SPI_CR1_BR_FPCLK_DIV_64 0x5__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1RCC_APB2ENR_DSIEN (1 << 27)RCC_CR_HSEBYP (1 << 18)SPI_CR1_CRCNEXT (1 << 12)__QQ_FBIT__ 7RCC_APB1RSTR_TIM4RST (1 << 2)RCC_PLLCFGR_PLLP_SHIFT 16RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CFGR_PPRE_DIV2 0x4__SIG_ATOMIC_WIDTH__ 32RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_PLLSAICFGR_PLLSAIR_MASK 0x7RCC_APB2ENR_SAI1EN (1 << 22)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32SPI_SR_FRE (1 << 8)RCC_APB1LPENR_TIM6LPEN (1 << 4)RCC_APB1LPENR_USART3LPEN (1 << 18)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0SPI_CR2(spi_base) MMIO32((spi_base) + 0x04)__SIZEOF_WINT_T__ 4RCC_AHB1RSTR_GPIOARST (1 << 0)SPI_CR1_SSI (1 << 8)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_APB2ENR_ADC3EN (1 << 10)RCC_CFGR_PPRE1_MASK 0x7RCC_DCKCFGR_TIMPRE (1 << 24)RCC_AHB1ENR_ETHMACTXEN (1 << 26)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SPI_CR2_RXDMAEN (1 << 0)__FLT32X_HAS_DENORM__ 1RCC_PLLCFGR_PLLSRC (1 << 22)__ULLACCUM_MIN__ 0.0ULLKRCC_APB1RSTR_UART5RST (1 << 20)__INT_FAST32_WIDTH__ 32SPI1_CR1 SPI_CR1(SPI1_BASE)RCC_CFGR_HPRE_DIV16 (0x8 + 3)RCC_APB1RSTR_TIM6RST (1 << 4)RCC_CKGATENR_AHB2APB1_CKEN (1<<0)RCC_AHB1ENR_DMA2EN (1 << 22)RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCENRCC_AHB2ENR MMIO32(RCC_BASE + 0x34)__ARM_ASM_SYNTAX_UNIFIED__ 1SPI_I2SCFGR_I2SSTD_PCM 0x3RCC_APB2LPENR_SDIOLPEN (1 << 11)SPI_I2SCFGR_I2SMOD (1 << 11)RCC_CKGATENR MMIO32(RCC_BASE + 0x90)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_AHB1ENR_GPIOBEN (1 << 1)RCC_APB1RSTR_TIM3RST (1 << 1)RCC_APB2RSTR_SYSCFGRST (1 << 14)__ARM_PCS_VFP 1RCC_AHB1LPENR_SRAM1LPEN (1 << 16)SPI_CR1_CPOL (1 << 1)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24RCC_AHB1LPENR_GPIOILPEN (1 << 8)UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64RCC_AHB1RSTR_GPIOKRST (1 << 10)RCC_AHB1RSTR_DMA2RST (1 << 22)__LLFRACT_IBIT__ 0uint32_tSYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)BIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIEN__GCC_ASM_FLAG_OUTPUTS__ 1RCC_CFGR_PPRE_DIV_NONE 0x0__ARM_FP 4LIBOPENCM3_PWR_COMMON_V1_H RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2SPI3_SR SPI_SR(SPI3_BASE)__UINT_FAST16_TYPE__ unsigned intRCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)__UHA_IBIT__ 8RCC_CSR_WWDGRSTF (1 << 30)SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)BIT16 (1<<16)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXRCC_CFGR_SWS_HSI 0x0GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)SPI1_I2SPR SPI_I2SPR(SPI1_BASE)__WINT_MIN__ 0UINT_LEAST16_MINUINT_LEAST64_MAX __UINT_LEAST64_MAX__SPI_I2SCFGR_CKPOL (1 << 3)__FLT64_DIG__ 15RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short intSPI1_CRCPR SPI_CRCPR(SPI1_BASE)RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST__DBL_MAX__ ((double)1.7976931348623157e+308L)SPI_CR1(spi_base) MMIO32((spi_base) + 0x00)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)UINTMAX_CRCC_CFGR_SW_SHIFT 0INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RCC_AHB1LPENR_GPIOALPEN (1 << 0)RCC_AHB2RSTR_DCMIRST (1 << 0)__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_CIR_PLLSAIRDYIE (1 << 14)I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_APB1ENR MMIO32(RCC_BASE + 0x40)RCC_CFGR_PPRE2_MASK 0x7__ARM_ARCHRCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFENPWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)__LONG_MAX__ 0x7fffffffLRCC_AHB1LPENR_IOPJLPEN RCC_AHB1LPENR_GPIOJLPENRCC_AHB3LPENR_FSMCLPEN (1 << 0)RCC_CFGR_I2SSRC (1 << 23)RCC_CFGR_MCOPRE_DIV_4 0x6RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FFRCC_APB1ENR_TIM6EN (1 << 4)RCC_SSCGR_MODPER_SHIFT 0__ARM_FEATURE_LDREX 7PTRDIFF_MAXRCC_CFGR_MCOPRE_DIV_NONE 0x0RCC_SSCGR_INCSTEP_MASK 0x7fffRCC_CFGR_HPRE_DIV128 (0x8 + 5)__INTMAX_TYPE__ long long int__LLFRACT_EPSILON__ 0x1P-63LLRSPI3 SPI3_BASERCC_APB2RSTR_USART6RST (1 << 5)__SFRACT_MAX__ 0X7FP-7HRCRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)spi_init_master__WCHAR_WIDTH__ 32RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)WINT_MAXRCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)__INT16_C(c) cSPI5 SPI5_BASERCC_APB2LPENR MMIO32(RCC_BASE + 0x64)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_APB1ENR_USART2EN (1 << 17)RCC_CFGR_HPRE_DIV_128 (0x8 + 5)RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)RCC_AHB1LPENR_GPIODLPEN (1 << 3)RCC_APB2RSTR_ADCRST (1 << 8)SPI2_I2SPR SPI_I2SPR(SPI2_BASE)__ATOMIC_ACQ_REL 4SPI_CR2_TXEIE (1 << 7)SPI6 SPI6_BASE__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)RCC_AHB3LPENR_FMCLPEN (1 << 0)SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)SPI3_CR2 SPI_CR2(SPI3_BASE)GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)RCC_CFGR_MCO2_HSE 0x2__FLT32_NORM_MAX__ 3.4028234663852886e+38F32ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)RCC_CR_PLLI2SON (1 << 26)UINT64_C(c) __UINT64_C(c)RCC_AHB1ENR_ETHMACRXEN (1 << 27)RCC_APB2ENR_TIM9EN (1 << 16)RCC_APB1ENR_CAN1EN (1 << 25)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53SPI_CR1_BR_FPCLK_DIV_32 0x4__ULFRACT_IBIT__ 0RCC_AHB1LPENR_SRAM3LPEN (1 << 19)RCC_APB1RSTR_PWRRST (1 << 28)INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)SPI_SR(spi_base) MMIO32((spi_base) + 0x08)RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intRCC_AHB3RSTR_FSMCRST (1 << 0)PWR_CR_VOS_MASK 0x3RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCUINT32_CADC2_BASE (PERIPH_BASE_APB2 + 0x2100)GCC: (15:12.2.rel1-1) 12.2.1 20221205 | (A  A3aeabi)7E-M M  "9;!#%')+-/1357=;l4h   M { <?     (  spi_common_v1.c$twm4.0.abb921a0aaad2653e18524772a7677abwm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.28.d4265628b39d8c27901d9acd2ab09e64wm4.spi_common_all.h.33.9ea0c3889826c83e4c563d215a234fb7wm4.spi_common_v1.h.45.4c39bc544842ead07085ffcc9b28593dwm4.spi_common_v1_frf.h.42.ecde164fb2c98d54f3d2c000a63f7cf4wm4.pwr_common_v1.h.34.5ba50cacb26c1962a4ec30bab2f0c81cwm4.pwr.h.49.809022926b9bde88f41e2ab32c7d2effwm4.rcc.h.55.7c6d4c25def1b1ac1cdf558eafc4ba01spi_init_masterspi_set_dff_8bitspi_set_dff_16bit "&-4;BIPUcjx}     &4? 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