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../common../../../include/libopencm3/stm32/common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/f4timer_common_f0234.ctimer_common_all.htimer_common_f24.hstdint.htimer.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.htimer.h(-$ & ./!@#0& & TIM_CCMR2_OC3CE (1 << 7)TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)TIM_DIER_TDE (1 << 14)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8TIM_SMCR_TS_ITR2 (0x2 << 4)TIM_CCMR1_CC2S_MASK (0x3 << 8)TIM_BDTR_OSSR (1 << 11)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1TIM7_PSC TIM_PSC(TIM7)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)TIM10_CCR1 TIM_CCR1(TIM10)TIM_CR1_UDIS (1 << 1)TIM15_SMCR TIM_SMCR(TIM15)TIM16_SR TIM_SR(TIM16)__FLT64_HAS_INFINITY__ 1TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)TIM_CR1_ARPE (1 << 7)TIM8_BDTR TIM_BDTR(TIM8)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKINT64_MAX __INT64_MAX____PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLTIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUTIM5_DCR TIM_DCR(TIM5)TIM_SMCR_SMS_EM3 (0x3 << 0)GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308TIM1_SMCR TIM_SMCR(TIM1)__FRACT_MIN__ (-0.5R-0.5R)TIM2_OR_ITR1_RMP_PTP (0x1 << 10)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKTIM15_CCMR1 TIM_CCMR1(TIM15)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))__SIZE_TYPE__ unsigned intTIM15_DIER TIM_DIER(TIM15)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32TIM3_CCR4 TIM_CCR4(TIM3)TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)TIM7_CNT TIM_CNT(TIM7)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)TIM_CR1_DIR_DOWN (1 << 4)TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1TIM_CCMR2_IC3PSC_8 (0x3 << 2)__FLT64_MAX__ 1.7976931348623157e+308F64UINT_FAST32_MAXTIM5_EGR TIM_EGR(TIM5)TIM4_CCR2 TIM_CCR2(TIM4)TIM6_CNT TIM_CNT(TIM6)FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)TIM_DIER_CC2DE (1 << 10)TIM_SMCR_TS_MASK (0x7 << 4)TIM5_OR_TI4_RMP_LSI (0x1 << 6)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1TIM2_CCR1 TIM_CCR1(TIM2)TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intI2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)TIM_DIER_CC3IE (1 << 3)USART1_BASE (PERIPH_BASE_APB2 + 0x1000)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intTIM3_ARR TIM_ARR(TIM3)TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)INT32_MIN (-INT32_MAX - 1)USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)TIM_SMCR_TS_TI1F_ED (0x4 << 4)QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)TIM_BDTR_DBA_MASK (0x1F << 0)TIM12 TIM12_BASE__USFRACT_MAX__ 0XFFP-8UHRTIM17_DMAR TIM_DMAR(TIM17)__FP_FAST_FMAF32 1TIM17_RCR TIM_RCR(TIM17)__UINTPTR_MAX__ 0xffffffffUTIM13_CCER TIM_CCER(TIM13)TIM4_CNT TIM_CNT(TIM4)TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)__FLT32_MIN_EXP__ (-125)TIM_EGR_CC2G (1 << 2)TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)UINT32_MAX __UINT32_MAX__TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)TIM_SR_BIF (1 << 7)TIM3_DIER TIM_DIER(TIM3)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"__HA_FBIT__ 7BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__TIM_CCMR2_OC3FE (1 << 2)TIM_CR2_OIS4 (1 << 14)TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)__SFRACT_EPSILON__ 0x1P-7HRTIM_EGR_BG (1 << 7)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31TIM2_CCR3 TIM_CCR3(TIM2)TIM2_CNT TIM_CNT(TIM2)DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)TIM1_CR2 TIM_CR2(TIM1)__UHQ_FBIT__ 16TIM5_CCR2 TIM_CCR2(TIM5)__FLT64_MIN_EXP__ (-1021)TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)__FLT32_MAX_10_EXP__ 38__UINT_FAST8_MAX__ 0xffffffffUTIM11_CCR1 TIM_CCR1(TIM11)TIM1_CNT TIM_CNT(TIM1)TIM_CCMR2_CC4S_MASK (0x3 << 8)TIM_DIER_CC1DE (1 << 9)UINT16_C(c) __UINT16_C(c)TIM_EGR_CC1G (1 << 1)__LACCUM_IBIT__ 32TIM15_ARR TIM_ARR(TIM15)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXTIM_BDTR_BKE (1 << 12)TIM13 TIM13_BASE__UINT_FAST16_MAX__ 0xffffffffUTIM_CCER_CC3NE (1 << 10)TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)INT64_C(c) __INT64_C(c)TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)__INTPTR_MAX__ 0x7fffffffTIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)TIM_SR_TIF (1 << 6)TIM2_DMAR TIM_DMAR(TIM2)WCHAR_MAX __WCHAR_MAX__TIM2_SR TIM_SR(TIM2)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX____UINT_LEAST8_TYPE__ unsigned charTIM5_CCR4 TIM_CCR4(TIM5)TIM15_CCR2 TIM_CCR2(TIM15)TIM1_SR TIM_SR(TIM1)TIM_CCMR2_IC3PSC_4 (0x2 << 2)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)TIM5_DMAR TIM_DMAR(TIM5)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xTIM_CCMR2_OC4FE (1 << 10)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)TIM_CCER_CC1NP (1 << 3)TIM16_CR2 TIM_CR2(TIM16)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charTIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)__GCC_ATOMIC_BOOL_LOCK_FREE 2TIM_SMCR_ETP (1 << 15)BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__TIM12_CR1 TIM_CR1(TIM12)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRTIM1_BASE (PERIPH_BASE_APB2 + 0x0000)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)__ELF__ 1UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICTIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40)TIM11_CR1 TIM_CR1(TIM11)TIM_BDTR_OSSI (1 << 10)TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)TIM_CCMR1_OC1M_PWM1 (0x6 << 4)TIM15_CNT TIM_CNT(TIM15)TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)TIM17_CCER TIM_CCER(TIM17)TIM14_CCER TIM_CCER(TIM14)TIM_SMCR_ETF_OFF (0x0 << 8)TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsTIM8_CCR1 TIM_CCR1(TIM8)BIT27 (1<<27)TIM_CCMR2_CC4S_OUT (0x0 << 8)TIM_CCMR1_CC1S_OUT (0x0 << 0)TIM_IC_BOTHTIM_SR_CC2OF (1 << 10)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)../common/timer_common_f0234.c__FLT_DECIMAL_DIG__ 9__thumb__ 1TIM12_CNT TIM_CNT(TIM12)__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charTIM_CR2_MMS_UPDATE (0x2 << 4)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)TIM10_SR TIM_SR(TIM10)INT32_C(c) __INT32_C(c)TIM7_DIER TIM_DIER(TIM7)FMC_BANK1 (PERIPH_BASE_AHB3)__GNUC_STDC_INLINE__ 1TIM_CR1_CMS_MASK (0x3 << 5)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2TIM9_EGR TIM_EGR(TIM9)PTRDIFF_MINTIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)TIM1_CCMR1 TIM_CCMR1(TIM1)TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77TIM3_DCR TIM_DCR(TIM3)__LACCUM_FBIT__ 31TIM1_CCER TIM_CCER(TIM1)TIM5_PSC TIM_PSC(TIM5)__FLT64_MAX_10_EXP__ 308TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINTIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)TIM8_EGR TIM_EGR(TIM8)TIM12_CCR1 TIM_CCR1(TIM12)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM2_DCR TIM_DCR(TIM2)TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM_DIER_CC3DE (1 << 11)TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__TIM_CCER_CC3P (1 << 9)TIM_SMCR_TS_ITR0 (0x0 << 4)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5TIM7_EGR TIM_EGR(TIM7)TIM15_DCR TIM_DCR(TIM15)TIM13_DIER TIM_DIER(TIM13)TIM3_CCR2 TIM_CCR2(TIM3)TIM8_CCER TIM_CCER(TIM8)TIM17_CCMR1 TIM_CCMR1(TIM17)TIM_CR2_OIS2N (1 << 11)TIM11_ARR TIM_ARR(TIM11)TIM1_DCR TIM_DCR(TIM1)TIM_CCMR1_OC1M_TOGGLE (0x3 << 4)GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)__UINT16_MAX__ 0xffffTIM_CR2_MMS_ENABLE (0x1 << 4)__TQ_FBIT__ 127TIM_SMCR_MSM (1 << 7)TIM_CCER_CC4NP (1 << 15)TIM6_EGR TIM_EGR(TIM6)__USQ_FBIT__ 32INT_FAST16_MINTIM_CCMR2_CC3S_IN_TRC (0x3 << 0)TIM13_CNT TIM_CNT(TIM13)TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)__thumb2__ 1__ULLACCUM_FBIT__ 32TIM11_SR TIM_SR(TIM11)TIM8_CCR4 TIM_CCR4(TIM8)TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)TIM_CCMR1_IC1PSC_MASK (0x3 << 2)TIM_CCMR2_OC4M_PWM2 (0x7 << 12)TIM_CCMR1_CC2S_OUT (0x0 << 8)__STRICT_ANSI__ 1FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)UINT_LEAST8_MAXINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)ST_VREFINT_CAL MMIO16(0x1FFF7A2A)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__TIM17_PSC TIM_PSC(TIM17)TIM_CR2_OIS1 (1 << 8)__USA_IBIT__ 16TIM_CCMR2_IC3F_OFF (0x0 << 4)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1TIM5_CR1 TIM_CR1(TIM5)PTRDIFF_MIN (-PTRDIFF_MAX - 1)TIM4_EGR TIM_EGR(TIM4)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)TIM_CCMR2_OC3PE (1 << 3)__UINT_FAST64_TYPE__ long long unsigned intTIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)__FLT_MIN__ 1.1754943508222875e-38FSPI6_BASE (PERIPH_BASE_APB2 + 0x5400)TIM_BDTR_LOCK_MASK (0x3 << 8)__FDPIC__TIM16_DIER TIM_DIER(TIM16)__UFRACT_MIN__ 0.0URTIM2_SMCR TIM_SMCR(TIM2)TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)__FLT32_IS_IEC_60559__ 2TIM3_EGR TIM_EGR(TIM3)TIM6_PSC TIM_PSC(TIM6)INT_FAST64_MIN__USFRACT_IBIT__ 0TIM4_DMAR TIM_DMAR(TIM4)__LDBL_EPSILON__ 2.2204460492503131e-16LUSART6_BASE (PERIPH_BASE_APB2 + 0x1400)__USFRACT_MIN__ 0.0UHRTIM4_CCR4 TIM_CCR4(TIM4)__ARM_NEONTIM9_CCER TIM_CCER(TIM9)DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)__UINT8_MAX__ 0xffTIM8_RCR TIM_RCR(TIM8)__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H TIM_SMCR_SMS_EM1 (0x1 << 0)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)TIM8_DIER TIM_DIER(TIM8)TIM_CR1_CKD_CK_INT (0x0 << 8)TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)TIM5 TIM5_BASEGPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)__DA_FBIT__ 31TIM_CCMR1_IC1PSC_2 (0x1 << 2)TIM_CCMR2_CC4S_IN_TI3 (0x2 << 8)__GXX_ABI_VERSION 1017TIM_CR2_CCPC (1 << 0)__INT_LEAST16_MAX__ 0x7fffTIM_DCR(tim_base) MMIO32((tim_base) + 0x48)__FLT_DENORM_MIN__ 1.4012984643248171e-45FPERIPH_BASE_AHB3 0x60000000UTIM_CCMR2_CC3S_IN_TI4 (0x2 << 0)RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)__ULLACCUM_EPSILON__ 0x1P-32ULLKTIM4_CR1 TIM_CR1(TIM4)TIM11_CNT TIM_CNT(TIM11)TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)INT_LEAST8_MAX __INT_LEAST8_MAX__TIM16_BDTR TIM_BDTR(TIM16)TIM_CCMR2_OC3M_FROZEN (0x0 << 4)TIM_CR2(tim_base) MMIO32((tim_base) + 0x04)__UINT32_C(c) c ## ULTIM8_DMAR TIM_DMAR(TIM8)TIM8_CR2 TIM_CR2(TIM8)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FTIM9_PSC TIM_PSC(TIM9)TIM17_CR1 TIM_CR1(TIM17)TIM11_CCMR1 TIM_CCMR1(TIM11)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38)TIM2_ARR TIM_ARR(TIM2)__ARM_ARCH_ISA_THUMBTIM15_PSC TIM_PSC(TIM15)TIM_SR_CC4IF (1 << 4)TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2TIM2_CCMR2 TIM_CCMR2(TIM2)TIM9 TIM9_BASETIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)TIM4_DIER TIM_DIER(TIM4)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1TIM_BDTR_DBL_MASK (0x1F << 8)FMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)SCS_BASE (PPBI_BASE + 0xE000)TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)TIM13_CCMR1 TIM_CCMR1(TIM13)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1TIM_CCMR1_OC2PE (1 << 11)TIM_CCMR1_IC2PSC_4 (0x2 << 10)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))TIM_CCER(tim_base) MMIO32((tim_base) + 0x20)__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1TIM3_SR TIM_SR(TIM3)TIM_CCMR1_IC1F_OFF (0x0 << 4)bool _BoolTIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)TIM_RCR(tim_base) MMIO32((tim_base) + 0x30)TIM9_DIER TIM_DIER(TIM9)__UINT_LEAST8_MAX__ 0xffTIM9_CR1 TIM_CR1(TIM9)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)TIM15_EGR TIM_EGR(TIM15)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1TIM_CCMR2_OC3M_MASK (0x7 << 4)TIM8_PSC TIM_PSC(TIM8)__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)TIM_CR1_CMS_CENTER_2 (0x2 << 5)TIM1_ARR TIM_ARR(TIM1)TIM13_CCR1 TIM_CCR1(TIM13)UINT32_MAXTIM8_CR1 TIM_CR1(TIM8)TIM_SMCR_TS_ITR3 (0x3 << 4)__INT_LEAST16_WIDTH__ 16TIM_CCMR1_OC1M_FROZEN (0x0 << 4)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)TIM1_RCR TIM_RCR(TIM1)__ARM_FEATURE_FP16_FMLTIM15_SR TIM_SR(TIM15)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRTIM_CCMR2_CC3S_MASK (0x3 << 0)TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C)TIM5_OR_TI4_RMP_RTC (0x3 << 6)__USFRACT_FBIT__ 8TIM7_CR1 TIM_CR1(TIM7)CORESIGHT_LSR_SLI (1<<0)TIM17_CR2 TIM_CR2(TIM17)TIM6_SR TIM_SR(TIM6)TIM_SMCR_SMS_OFF (0x0 << 0)TIM15_CR1 TIM_CR1(TIM15)TIM_CCMR1_OC2FE (1 << 10)TIM4 TIM4_BASE__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____ARM_ARCH_7EM__ 1TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)__UINT32_MAX__ 0xffffffffULTIM2 TIM2_BASETIM_CCMR1_IC1PSC_OFF (0x0 << 2)GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)TIM16_CCR1 TIM_CCR1(TIM16)UINTPTR_MAX__INT_LEAST8_MAX__ 0x7fTIM8_SR TIM_SR(TIM8)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXTIM1_BDTR TIM_BDTR(TIM1)TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)TIM7_SR TIM_SR(TIM7)TIM5_OR_TI4_RMP_LSE (0x2 << 6)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)TIM_SMCR_TS_ETRF (0x7 << 4)__UINT_LEAST32_MAX__ 0xffffffffULDMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)TIM8_SMCR TIM_SMCR(TIM8)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)TIM_SMCR_ETF_MASK (0xF << 8)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVETIM_CCMR1_OC1M_MASK (0x7 << 4)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intTIM9_ARR TIM_ARR(TIM9)TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)TIM13_EGR TIM_EGR(TIM13)TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)UINT_LEAST16_MAX __UINT_LEAST16_MAX__TIM_SR_CC4OF (1 << 12)INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0TIM3_CR1 TIM_CR1(TIM3)TIM_SMCR_SMS_TM (0x6 << 0)__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXTIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)TIM_CCER_CC2E (1 << 4)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32TIM8_ARR TIM_ARR(TIM8)__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)TIM_CCER_CC1NE (1 << 2)__INT32_MAX__ 0x7fffffffLLTDC_BASE (PERIPH_BASE_APB2 + 0x6800)TIM9_CCR1 TIM_CCR1(TIM9)UINTMAX_MAXTIM2_CR1 TIM_CR1(TIM2)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICTIM14_CCR1 TIM_CCR1(TIM14)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24TIM15_CR2 TIM_CR2(TIM15)SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32TIM13_CR1 TIM_CR1(TIM13)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__TIM1_CR1 TIM_CR1(TIM1)BIT28 (1<<28)GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2DESIG_UNIQUE_ID_BASE (0x1FFF7A10U)TIM_BDTR_AOE (1 << 14)TIM_SR_CC2IF (1 << 2)__DBL_MAX_EXP__ 1024TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44)__ATOMIC_RELEASE 3TIM15_RCR TIM_RCR(TIM15)TIM_CCMR2_IC3PSC_2 (0x1 << 2)UINT_FAST8_MAX__FLT_MANT_DIG__ 24TIM_SR_CC3OF (1 << 11)TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)__UDQ_IBIT__ 0TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1TIM2_CCER TIM_CCER(TIM2)__UACCUM_MAX__ 0XFFFFFFFFP-16UKTIM_CR1_OPM (1 << 3)TIM_SMCR_SMS_MASK (0x7 << 0)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64TIM5_ARR TIM_ARR(TIM5)__FINITE_MATH_ONLY__ 0__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIM_CCER_CC1E (1 << 0)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1TIM13_ARR TIM_ARR(TIM13)__ULLFRACT_IBIT__ 0TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)MMIO16(addr) (*(volatile uint16_t *)(addr))TIM9_CCMR1 TIM_CCMR1(TIM9)TIM4_ARR TIM_ARR(TIM4)TIM_CCMR2_IC3F_MASK (0xF << 4)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXTIM_CCMR2_OC4M_PWM1 (0x6 << 12)__LONG_WIDTH__ 32TIM3_SMCR TIM_SMCR(TIM3)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16TIM_CR1_CMS_EDGE (0x0 << 5)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0TIM17_ARR TIM_ARR(TIM17)CORESIGHT_LSR_OFFSET 0xfb4TIM4_CR2 TIM_CR2(TIM4)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7TIM13_SR TIM_SR(TIM13)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55TIM_CCER_CC4P (1 << 13)TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXTIM_CR1_CKD_CK_INT_MASK (0x3 << 8)TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08)__LDBL_HAS_QUIET_NAN__ 1TIM_DIER_CC4DE (1 << 12)TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)TIM17_DCR TIM_DCR(TIM17)TIM3_PSC TIM_PSC(TIM3)TIM8_CNT TIM_CNT(TIM8)TIM_CCMR1_IC2PSC_OFF (0x0 << 10)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8TIM_SR_CC1OF (1 << 9)__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1tim_ic_polBIT9 (1<<9)TIM_EGR_CC4G (1 << 4)__FLT32X_MIN__ 2.2250738585072014e-308F32xUART7_BASE (PERIPH_BASE_APB1 + 0x7800)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64TIM8_CCR2 TIM_CCR2(TIM8)__INTMAX_C(c) c ## LLTIM_SR_UIF (1 << 0)TIM_CCER_CC3E (1 << 8)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8TIM15_BDTR TIM_BDTR(TIM15)__SIZEOF_WCHAR_T__ 4TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34)TIM_BDTR_MOE (1 << 15)__FLT32X_MANT_DIG__ 53TIM_CCMR1_IC2PSC_2 (0x1 << 10)TIM_CR2_OIS3 (1 << 12)TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)__UFRACT_MAX__ 0XFFFFP-16URTIM1_DMAR TIM_DMAR(TIM1)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)TIM_SR(tim_base) MMIO32((tim_base) + 0x10)TIM_DIER_UIE (1 << 0)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0TIM8_CCR3 TIM_CCR3(TIM8)STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)TIM_CCMR1_OC2CE (1 << 15)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)TIM_CCMR2_IC4F_OFF (0x0 << 12)DESIG_FLASH_SIZE_BASE (0x1FFF7A22U)TIM14_PSC TIM_PSC(TIM14)TIM12_PSC TIM_PSC(TIM12)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)TIM_CCMR2_IC4F_MASK (0xF << 12)TIM_CCMR1_IC1PSC_4 (0x2 << 2)__LDBL_MAX_10_EXP__ 308TIM3_DMAR TIM_DMAR(TIM3)TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C)__INT_FAST32_TYPE__ intTIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)TIM11_EGR TIM_EGR(TIM11)TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)unsigned intTIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1TIM4_CCMR1 TIM_CCMR1(TIM4)__USACCUM_IBIT__ 8SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)ITM_BASE (PPBI_BASE + 0x0000)TIM_CR1_URS (1 << 2)TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKTIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)__FLT_EVAL_METHOD__ 0TIM_DIER_UDE (1 << 8)TIM5_DIER TIM_DIER(TIM5)TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32TIM_CCER_CC3NP (1 << 11)TIM3_CCER TIM_CCER(TIM3)__ARM_FEATURE_LDREXTIM2_DIER TIM_DIER(TIM2)__UQQ_FBIT__ 8STM32F4 1INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0TIM_CCMR1_IC2F_OFF (0x0 << 12)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__TIM_SMCR_SMS_GM (0x5 << 0)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4TIM_DIER_CC1IE (1 << 1)__STDC__ 1TIM_BDTR_LOCK_OFF (0x0 << 8)__ARM_FEATURE_IDIV 1TIM_EGR_UG (1 << 0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)TIM_CCMR1_CC1S_MASK (0x3 << 0)TIM_CCMR2_OC4M_MASK (0x7 << 12)__ARM_FEATURE_COPROC 15TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)UINT64_MAX __UINT64_MAX__TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)INT8_MIN__ORDER_PDP_ENDIAN__ 3412TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)/build/libopencm3/lib/stm32/f4TIM_CR1(tim_base) MMIO32((tim_base) + 0x00)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)TIM_CCER_CC1P (1 << 1)INT8_C__LDBL_MIN_10_EXP__ (-307)TIM_IC_RISINGINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)TIM_CCMR2_OC3M_PWM1 (0x6 << 4)__LFRACT_EPSILON__ 0x1P-31LRTIM_CCMR1_OC1PE (1 << 3)TIM2_EGR TIM_EGR(TIM2)TIM16_RCR TIM_RCR(TIM16)TIM_EGR_CC3G (1 << 3)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xTIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)__arm__ 1TIM11_DIER TIM_DIER(TIM11)TIM8_DCR TIM_DCR(TIM8)TIM1_CCR2 TIM_CCR2(TIM1)TIM7_CR2 TIM_CR2(TIM7)TIM_CCMR2_IC4PSC_OFF (0x0 << 10)__FLT32_MIN_10_EXP__ (-37)TIM4_CCER TIM_CCER(TIM4)TIM_CCMR1_IC2F_MASK (0xF << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)TIM1_EGR TIM_EGR(TIM1)__ARM_FP16_FORMAT_ALTERNATIVETIM17_CNT TIM_CNT(TIM17)__LDBL_NORM_MAX__ 1.7976931348623157e+308LTIM_SMCR_SMS_ECM1 (0x7 << 0)TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)TIM6_CR2 TIM_CR2(TIM6)TIM8_CCMR1 TIM_CCMR1(TIM8)__TA_IBIT__ 64TIM5_CNT TIM_CNT(TIM5)TIM_CCMR2_OC4PE (1 << 11)TIM2_CCR2 TIM_CCR2(TIM2)TIM_IC_FALLINGTIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)TIM4_PSC TIM_PSC(TIM4)__ARM_FEATURE_QRDMXTIM16_CCMR1 TIM_CCMR1(TIM16)TIM_DIER_COMIE (1 << 5)__ARM_ARCH_ISA_THUMB 2TIM5_CR2 TIM_CR2(TIM5)__LONG_LONG_MAX__ 0x7fffffffffffffffLLTIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)TIM_EGR_TG (1 << 6)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)TIM9_SMCR TIM_SMCR(TIM9)TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__TIM_CCER_CC4E (1 << 12)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)TIM_CCER_CC2P (1 << 5)INT_FAST32_MIN (-INT_FAST32_MAX - 1)TIM_CCMR1_OC2M_PWM1 (0x6 << 12)TIM2_PSC TIM_PSC(TIM2)__FLT32_DIG__ 6TIM1_PSC TIM_PSC(TIM1)INT_LEAST16_MAXTIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)TIM10 TIM10_BASEBIT15 (1<<15)ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)TIM_EGR_COMG (1 << 5)TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)TIM1_CCR3 TIM_CCR3(TIM1)TIM_EGR(tim_base) MMIO32((tim_base) + 0x14)TIM3_CCMR2 TIM_CCMR2(TIM3)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXTIM_CR2_CCUS (1 << 2)ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C)__ACCUM_MIN__ (-0X1P15K-0X1P15K)TIM_CCER_CC2NE (1 << 6)__ARM_FEATURE_CRYPTOTIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)TIM5_CCMR2 TIM_CCMR2(TIM5)TIM_SR_COMIF (1 << 5)TIM_BDTR_BKP (1 << 13)TIM_CCMR2_OC3M_TOGGLE (0x3 << 4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLTIM5_SMCR TIM_SMCR(TIM5)__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2TIM_CR2_OIS2 (1 << 10)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E)TIM9_CCR2 TIM_CCR2(TIM9)__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned intTIM16_CCER TIM_CCER(TIM16)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)TIM10_EGR TIM_EGR(TIM10)__ULACCUM_IBIT__ 32TIM_DIER_COMDE (1 << 13)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18)INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINTIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)TIM_CCMR2_IC4PSC_8 (0x3 << 10)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRTIM16_DCR TIM_DCR(TIM16)__UINT_LEAST16_TYPE__ short unsigned intTIM12_SMCR TIM_SMCR(TIM12)TIM9_SR TIM_SR(TIM9)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intTIM_CCMR2_OC3M_PWM2 (0x7 << 4)TIM15_CCR1 TIM_CCR1(TIM15)__FLT32X_DIG__ 15TIM11 TIM11_BASE__UTQ_FBIT__ 128TIM17_CCR1 TIM_CCR1(TIM17)TIM_CCMR1_OC1CE (1 << 7)TIM10_CR1 TIM_CR1(TIM10)timer_peripheral__INT_FAST16_MAX__ 0x7fffffffTIM_CR2_TI1S (1 << 7)TIM3_CNT TIM_CNT(TIM3)TIM14_CNT TIM_CNT(TIM14)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2TIM_CCER_CC2NP (1 << 7)PERIPH_BASE_AHB2 0x50000000UTIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)TIM_CR2_MMS_RESET (0x0 << 4)TIM12_DIER TIM_DIER(TIM12)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKTIM_SMCR_TS_ITR1 (0x1 << 4)TIM_CCMR1_IC1PSC_8 (0x3 << 2)TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)__ULFRACT_MIN__ 0.0ULRTIM_CR2_CCDS (1 << 3)TIM12_CCR2 TIM_CCR2(TIM12)__DQ_IBIT__ 0TIM4_SMCR TIM_SMCR(TIM4)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intTIM_CR1_DIR_UP (0 << 4)TIM8 TIM8_BASETIM_SMCR_SMS_EM2 (0x2 << 0)TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)WCHAR_MINTIM16_ARR TIM_ARR(TIM16)TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)TIM_CR2_OIS3N (1 << 13)BEGIN_DECLS TIM3_CCR1 TIM_CCR1(TIM3)TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)timer_ic_set_polarityTIM5_CCMR1 TIM_CCMR1(TIM5)SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)TIM_CCMR2_IC4PSC_4 (0x2 << 10)TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xTIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)__ARM_EABI__ 1INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)__ARM_FEATURE_DSP 1TIM_SR_CC1IF (1 << 1)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0TIM11_PSC TIM_PSC(TIM11)TIM10_CCER TIM_CCER(TIM10)TIM5_SR TIM_SR(TIM5)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intTIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)__USQ_IBIT__ 0TIM17_BDTR TIM_BDTR(TIM17)__UINT_LEAST32_TYPE__ long unsigned intTIM4_SR TIM_SR(TIM4)I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)__ARM_FEATURE_NUMERIC_MAXMINTIM3_CCR3 TIM_CCR3(TIM3)GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)__GCC_ATOMIC_INT_LOCK_FREE 2INTMAX_MAXTIM7_ARR TIM_ARR(TIM7)FMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000)FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)TIM3_CCMR1 TIM_CCMR1(TIM3)__ARM_FEATURE_FP16_SCALAR_ARITHMETICUINT_FAST32_MAX __UINT_FAST32_MAX____USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CTIM3 TIM3_BASEDMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)INT64_MINTIM5_CCR1 TIM_CCR1(TIM5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intTIM4_CCR1 TIM_CCR1(TIM4)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRTIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)__SIZEOF_SIZE_T__ 4TIM14_ARR TIM_ARR(TIM14)TIM_SMCR_ECE (1 << 14)__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLTIM_CCMR1_IC1F_MASK (0xF << 4)TIM_CCMR1_OC2M_PWM2 (0x7 << 12)TIM_SR_CC3IF (1 << 3)TPIU_BASE (PPBI_BASE + 0x40000)TIM_CR2_OIS_MASK (0x7f << 8)__LDBL_MIN__ 2.2250738585072014e-308LTIM12_SR TIM_SR(TIM12)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)CORESIGHT_LAR_OFFSET 0xfb0TIM_CCMR1_OC1FE (1 << 2)TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)TIM_DIER_CC4IE (1 << 4)TIM5_OR TIM_OR(TIM5)short intTIM6_DIER TIM_DIER(TIM6)TIM7 TIM7_BASE__UINT16_C(c) c__UDA_IBIT__ 32TIM16_DMAR TIM_DMAR(TIM16)TIM_CR2_MMS_MASK (0x7 << 4)UINT_LEAST32_MAXTIM4_CCR3 TIM_CCR3(TIM4)BIT2 (1<<2)TIM1_CCR1 TIM_CCR1(TIM1)__ATOMIC_RELAXED 0TIM14_CCMR1 TIM_CCMR1(TIM14)__ARM_FEATURE_COPROCTIM_SMCR_TS_TI1FP1 (0x5 << 4)TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)TIM16_EGR TIM_EGR(TIM16)__DBL_HAS_INFINITY__ 1FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)__SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)TIM10_DIER TIM_DIER(TIM10)BIT5 (1<<5)TIM2_OR_ITR1_RMP_MASK (0x3 << 10)BIT1 (1<<1)BIT26 (1<<26)INT_LEAST32_MAXTIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)__USES_INITFINI__ 1TIM2_CCR4 TIM_CCR4(TIM2)TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)__DBL_DECIMAL_DIG__ 17TIM_CCMR2_IC4PSC_MASK (0x3 << 10)BIT8 (1<<8)TIM10_CNT TIM_CNT(TIM10)INT16_C(c) __INT16_C(c)TIM5_OR_TI4_RMP_GPIO (0x0 << 6)TIM_OR(tim_base) MMIO32((tim_base) + 0x50)TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)TIM_CR1_CMS_CENTER_3 (0x3 << 5)__INT16_MAX__ 0x7fffTIM_DIER_BIE (1 << 7)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1TIM16_CR1 TIM_CR1(TIM16)TIM6_ARR TIM_ARR(TIM6)TIM_SMCR_ETPS_OFF (0x0 << 12)__QQ_FBIT__ 7TIM_SMCR_ETPS_MASK (0X3 << 12)TIM16_PSC TIM_PSC(TIM16)TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)TIM2_CCMR1 TIM_CCMR1(TIM2)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)TIM_CCMR2_IC4PSC_2 (0x1 << 10)TIM12_ARR TIM_ARR(TIM12)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32TIM5_CCER TIM_CCER(TIM5)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0TIM14_SR TIM_SR(TIM14)TIM2_OR TIM_OR(TIM2)TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)__SIZEOF_WINT_T__ 4TIM15_DMAR TIM_DMAR(TIM15)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17TIM11_CCER TIM_CCER(TIM11)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)TIM_CCMR1_OC1M_PWM2 (0x7 << 4)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1TIM13_PSC TIM_PSC(TIM13)TIM5_CCR3 TIM_CCR3(TIM5)__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32TIM10_CCMR1 TIM_CCMR1(TIM10)TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)__ARM_ASM_SYNTAX_UNIFIED__ 1TIM_CR1_CMS_CENTER_1 (0x1 << 5)TIM_DIER_CC2IE (1 << 2)TIM4_DCR TIM_DCR(TIM4)TIM1_CCR4 TIM_CCR4(TIM1)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODTIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)TIM14_EGR TIM_EGR(TIM14)TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)TIM_CR1_CEN (1 << 0)__ARM_PCS_VFP 1TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)TIM_CCMR2_OC4M_TOGGLE (0x3 << 12)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H TIM6_CR1 TIM_CR1(TIM6)TIM4_CCMR2 TIM_CCMR2(TIM4)TIM9_CNT TIM_CNT(TIM9)UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)INT_LEAST64_MINTIM_SMCR_SMS_RM (0x4 << 0)__GCC_CONSTRUCTIVE_SIZE 64TIM6 TIM6_BASE__LLFRACT_IBIT__ 0TIM_SMCR_TS_TI2FP2 (0x6 << 4)uint32_tSYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)BIT12 (1<<12)TIM_CCMR1_OC2M_FROZEN (0x0 << 12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKTIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)__GCC_ASM_FLAG_OUTPUTS__ 1TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)__ARM_FP 4TIM_CCMR2_IC3PSC_MASK (0x3 << 2)TIM1_CCMR2 TIM_CCMR2(TIM1)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8TIM14_CR1 TIM_CR1(TIM14)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKTIM_BDTR_DTG_MASK 0x00FF__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)BIT16 (1<<16)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXTIM_CCMR1_IC2PSC_MASK (0x3 << 10)GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)__WINT_MIN__ 0UINT_LEAST16_MINUINT_LEAST64_MAX __UINT_LEAST64_MAX__TIM12_CCMR1 TIM_CCMR1(TIM12)__FLT64_DIG__ 15TIM10_ARR TIM_ARR(TIM10)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)TIM_DIER_TIE (1 << 6)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1TIM1_DIER TIM_DIER(TIM1)UINTMAX_CINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1TIM17_DIER TIM_DIER(TIM17)TIM14_DIER TIM_DIER(TIM14)TIM16_CNT TIM_CNT(TIM16)I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)TIM_CCMR2_OC4M_FROZEN (0x0 << 12)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)__ARM_ARCH__LONG_MAX__ 0x7fffffffLTIM_CNT(tim_base) MMIO32((tim_base) + 0x24)TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)TIM_CCMR2_OC4CE (1 << 15)TIM1 TIM1_BASETIM12_EGR TIM_EGR(TIM12)TIM_IC1TIM_IC2TIM_IC3TIM_IC4TIM_PSC(tim_base) MMIO32((tim_base) + 0x28)__ARM_FEATURE_LDREX 7PTRDIFF_MAXTIM_CCMR2_OC3M_INACTIVE (0x2 << 4)TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C)__INTMAX_TYPE__ long long intTIM_CCMR2_CC4S_IN_TI4 (0x1 << 8)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HRCRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)TIM14 TIM14_BASE__WCHAR_WIDTH__ 32TIM5_OR_TI4_RMP_MASK (0x3 << 6)WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__PTRDIFF_WIDTH__ 32RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)__ATOMIC_ACQ_REL 4TIM_CCMR1_OC2M_MASK (0x7 << 12)__HQ_IBIT__ 0TIM17_SR TIM_SR(TIM17)__DBL_MIN_10_EXP__ (-307)TIM_CCMR1_IC2PSC_8 (0x3 << 10)TIM15_CCER TIM_CCER(TIM15)TIM12_CCER TIM_CCER(TIM12)TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)TIM_CCMR2_CC3S_OUT (0x0 << 0)GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)TIM10_PSC TIM_PSC(TIM10)TIM8_CCMR2 TIM_CCMR2(TIM8)TIM17_EGR TIM_EGR(TIM17)TIM_CCMR2_IC3PSC_OFF (0x0 << 2)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)UINT64_C(c) __UINT64_C(c)TIM_CR2_OIS1N (1 << 9)TIM3_CR2 TIM_CR2(TIM3)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0TIM_CCMR1_OC2M_ACTIVE (0x1 << 12)tim_ic_idINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intTIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)__ARM_FEATURE_CDE_COPROCTIM2_CR2 TIM_CR2(TIM2)UINT32_CADC2_BASE (PERIPH_BASE_APB2 + 0x2100)GCC: (15:12.2.rel1-1) 12.2.1 20221205 | (AA3aeabi)7E-M M  "     +-!#%')/@q9m .1 ( timer_common_f0234.c$twm4.0.abb921a0aaad2653e18524772a7677abwm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.28.d4265628b39d8c27901d9acd2ab09e64wm4.timer_common_all.h.38.1e06b1c38b4fa3b42e65fafbbc60bcfdwm4.timer_common_f24.h.39.dbb660608fe9ac16c8091996090fb0edtimer_ic_set_polarity  " & -4;BIPUcjx}    ,  '-7@HN^d #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y          #)/5;AGMSY_ekqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BI  #)/5;AGMSY_ekqw} #)/5;AGMSY_ekq #)/5;AGMSY_ekqw} %+17=CIOU[agmsy  '.5<CJQX_fmt #)/5;AGMSY_ekqw} %+29@GNU\cjqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BIPW^elsz ")07>ELSZahov} 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F M T [ b i p w ~                        & - 4 ; B I P W ^ e l s z                        " ) 0 7 > E L S Z a h o v }                        % , 3 : A H O V ] d k r y                     !(/6=DKRY`gnu|$+29@GNU\cjqx #)/5;AGM.symtab.strtab.shstrtab.text.data.bss.text.timer_ic_set_polarity.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.group4 2@ 2L 2X 2d 2p 2| 2 2  2!!',(LH @2XjKf @$2~ z @42 @D2m @L`2t  @02 @ 28N @2" @(2 @02!v @,2#y @(2%} @2'$R @h2)N% @<2+0!'0'( @D2/p 4@3-  T