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../../cm3../../cm3/../dispatch/../stm32/f4/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/cm3../../../include/libopencm3/dispatch../../../include/libopencm3/stm32/f4../../cm3/../dispatchvector.cvector_chipset.cstdint.hvector.hscb.hmemorymap.hcommon.hstdbool.hnvic.hnvic.hnvic.hvector_chipset.cvector_nvic.cvector_nvic.c> $# ! 3 !4 4z '4 z M E .J'; 1$  31 $  2b   .-% . .A$.; .;SCB_DCCSW MMIO32(SCB_BASE + 0x26C)SCB_SHPR_PRI_4_MEMMANAGE 0SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1pre_mainbus_fault__FLT64_HAS_INFINITY__ 1SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17SCB_CFSR_INVSTATE (1 << 17)WINT_MIN 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1.7976931348623157e+308F64SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))UINT_FAST32_MAXNVIC_ADC_IRQ 18LIBOPENCM3_NVIC_H INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intSCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)SCB_CFSR_STKERR (1 << 12)SCB_DCISW MMIO32(SCB_BASE + 0x260)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intSCB_CPUID_REVISION_LSB 0INT32_MIN (-INT32_MAX - 1)SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)__FLT32_MAX_10_EXP__ 38vector_table_tNVIC_EXTI4_IRQ 10NVIC_PENDSV_IRQ -2SCB_AIRCR_ENDIANESS (1 << 15)__USFRACT_MAX__ 0XFFP-8UHR__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)NVIC_EXTI0_IRQ 6UINT32_MAX __UINT32_MAX__SCB_SHCSR_BUSFAULTACT (1 << 1)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__openblt_signature__SFRACT_EPSILON__ 0x1P-7HRSCB_CCR_NONBASETHRDENA (1 << 0)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)NVIC_CAN1_RX1_IRQ 21__UHQ_FBIT__ 16NVIC_USART3_IRQ 39__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)NVIC_SPI6_IRQ 86UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32NVIC_DMA2_STREAM7_IRQ 70SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCB_SHPR_PRI_9_RESERVED 5NVIC_DMA1_STREAM4_IRQ 15__UINT_FAST16_MAX__ 0xffffffffUNVIC_SPI2_IRQ 36__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCB_CTR_DMINLINE_SHIFT 16_edata__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URSCB_DCCMVAU MMIO32(SCB_BASE + 0x264)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__NVIC_FPU_IRQ 81__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15SCB_SCR_SLEEPONEXIT (1 << 1)__UACCUM_IBIT__ 16long intUINT8_MAXSCB_MMFAR MMIO32(SCB_BASE + 0x34)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1NVIC_CAN1_RX0_IRQ 20__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UINT_FAST64_MAX__ 0xffffffffffffffffULLNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32NVIC_UART7_IRQ 82__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charNVIC_MEM_MANAGE_IRQ -12__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128SCB_BFAR MMIO32(SCB_BASE + 0x38)main__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SCB_SCR_SLEEPDEEP (1 << 2)LIBOPENCM3_VECTOR_H INTMAX_MAX __INTMAX_MAX____INT_LEAST32_WIDTH__ 32SCB_SHCSR_MEMFAULTENA (1 << 16)SCB_HFSR_VECTTBL (1 << 1)NVIC_EXTI2_IRQ 8GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsNVIC_USART2_IRQ 38BIT27 (1<<27)NVIC_TIM7_IRQ 55SCB_CPUID_CONSTANT_LSB 16SCB_SHPR_PRI_13_RESERVED 9__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__preinit_array_startPTRDIFF_MINSCB_CPUID_VARIANT_LSB 20__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SCB_CPACR_CP10 (1 << 20)PPBI_BASE (0xE0000000U)__ARM_ARCH_PROFILE 77NVIC_I2C2_EV_IRQ 33null_handlerLIBOPENCM3_STM32_F4_NVIC_H __FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSCB_CFSR_MUNSTKERR (1 << 3)SCB_CCSIDR MMIO32(SCB_BASE + 0x80)NVIC_CAN2_SCE_IRQ 66__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCB_ICIALLU MMIO32(SCB_BASE + 0x250)__FRACT_MAX__ 0X7FFFP-15RNVIC_TIM3_IRQ 29SCB_ICSR_PENDSVSET (1 << 28)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5NVIC_I2C1_EV_IRQ 31SCB_CPACR MMIO32(SCB_BASE + 0x88)NVIC_USAGE_FAULT_IRQ -10NVIC_EXTI3_IRQ 9NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + (ipr_id))__UINT16_MAX__ 0xffff__TQ_FBIT__ 127usage_fault__USQ_FBIT__ 32INT_FAST16_MINNVIC_SPI5_IRQ 85__thumb2__ 1__ULLACCUM_FBIT__ 32SCB_AIRCR_VECTKEY (0x05FA << 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0x7C)SCB_SHCSR_USGFAULTENA (1 << 18)SCB_ICSR_RETOBASE (1 << 11)__DBL_HAS_DENORM__ 1NVIC_OTG_FS_IRQ 67__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffNVIC_DMA1_STREAM5_IRQ 16__FLT_DENORM_MIN__ 1.4012984643248171e-45Fvector_tableINT_LEAST32_MAX __INT_LEAST32_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKSCB_SHCSR_MEMFAULTACT (1 << 0)hard_faultINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## ULUINTMAX_MAX__UACCUM_MIN__ 0.0UKSCS_BASE (PPBI_BASE + 0xE000)__init_array_startSCB_CCSELR MMIO32(SCB_BASE + 0x84)__SIZEOF_DOUBLE__ 8__ARM_ARCH_ISA_THUMBSCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)NVIC_I2C3_EV_IRQ 72LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SCB_FPCAR MMIO32(SCB_BASE + 0x238)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)__FLT32_HAS_QUIET_NAN__ 1__ARM_FEATURE_MATMUL_INT8__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 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0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12NVIC_UART4_IRQ 52SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_BUS_FAULT_IRQ -11__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVENVIC_DMA1_STREAM0_IRQ 11__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0NVIC_TIM1_CC_IRQ 27__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__UINT_LEAST16_TYPE__ short unsigned int__INT32_MAX__ 0x7fffffffLSCB_CFSR_NOCP (1 << 19)SCB_ICSR_NMIPENDSET (1 << 31)SCB_MVFR1 MMIO32(SCB_BASE + 0x244)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32NVIC_SDIO_IRQ 49__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__BIT28 (1<<28)_ebss__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24NVIC_DMA2_STREAM6_IRQ 69__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INT64_MIN (-INT64_MAX - 1)SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)UINTPTR_MAXNVIC_UART5_IRQ 53__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))NVIC_ETH_IRQ 61SCB_CTR_FORMAT_MASK 0x7__GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKSCB_VTOR_TBLOFF_LSB 9__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7memory_manage_fault_stackNVIC_TIM8_BRK_TIM12_IRQ 43__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__FLT_EPSILON__ 1.1920928955078125e-7F__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)NVIC_TIM6_DAC_IRQ 54SCB_CPUID_IMPLEMENTER_LSB 24SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xSCB_CCR_DIV_0_TRP (1 << 4)__FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLNVIC_IRQ_COUNT 91__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4NVIC_TIM8_TRG_COM_TIM14_IRQ 45__UFRACT_MAX__ 0XFFFFP-16URblocking_handlerFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)NVIC_SPI1_IRQ 35__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCB_ICSR_PENDSTSET (1 << 26)NVIC_RTC_ALARM_IRQ 41ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)NVIC_DMA2_STREAM2_IRQ 58__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCB_CCR_DC (1 << 16)reset__INT_FAST32_TYPE__ intNVIC_USART1_IRQ 37unsigned intSCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__init_array_end__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0NVIC_OTG_HS_EP1_OUT_IRQ 74__SCHAR_MAX__ 0x7fINT_LEAST32_MINSCB_DCCISW MMIO32(SCB_BASE + 0x274)SCB_SHPR_PRI_6_USAGEFAULT 2__ARM_FEATURE_LDREX__UQQ_FBIT__ 8STM32F4 1INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0NVIC_SAI1_IRQ 87INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)__UINT8_TYPE__ unsigned charNVIC_DCMI_IRQ 78NVIC_CAN2_TX_IRQ 63SCB_SHCSR_SYSTICKACT (1 << 11)__ARM_FEATURE_COPROC 15NVIC_USB_FS_WKUP_IRQ 42UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"NVIC_TIM5_IRQ 50INT8_MIN__ORDER_PDP_ENDIAN__ 3412/build/libopencm3/lib/stm32/f4true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)pend_sv__FLT32X_MIN_EXP__ (-1021)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2IRQ_HANDLERS [NVIC_NVIC_WWDG_IRQ] = nvic_wwdg_isr, [NVIC_PVD_IRQ] = pvd_isr, [NVIC_TAMP_STAMP_IRQ] = tamp_stamp_isr, [NVIC_RTC_WKUP_IRQ] = rtc_wkup_isr, [NVIC_FLASH_IRQ] = flash_isr, [NVIC_RCC_IRQ] = rcc_isr, [NVIC_EXTI0_IRQ] = exti0_isr, [NVIC_EXTI1_IRQ] = exti1_isr, [NVIC_EXTI2_IRQ] = exti2_isr, [NVIC_EXTI3_IRQ] = exti3_isr, [NVIC_EXTI4_IRQ] = exti4_isr, [NVIC_DMA1_STREAM0_IRQ] = dma1_stream0_isr, [NVIC_DMA1_STREAM1_IRQ] = dma1_stream1_isr, [NVIC_DMA1_STREAM2_IRQ] = dma1_stream2_isr, [NVIC_DMA1_STREAM3_IRQ] = dma1_stream3_isr, [NVIC_DMA1_STREAM4_IRQ] = dma1_stream4_isr, [NVIC_DMA1_STREAM5_IRQ] = dma1_stream5_isr, [NVIC_DMA1_STREAM6_IRQ] = dma1_stream6_isr, [NVIC_ADC_IRQ] = adc_isr, [NVIC_CAN1_TX_IRQ] = can1_tx_isr, [NVIC_CAN1_RX0_IRQ] = can1_rx0_isr, [NVIC_CAN1_RX1_IRQ] = can1_rx1_isr, [NVIC_CAN1_SCE_IRQ] = can1_sce_isr, [NVIC_EXTI9_5_IRQ] = exti9_5_isr, [NVIC_TIM1_BRK_TIM9_IRQ] = tim1_brk_tim9_isr, [NVIC_TIM1_UP_TIM10_IRQ] = tim1_up_tim10_isr, [NVIC_TIM1_TRG_COM_TIM11_IRQ] = tim1_trg_com_tim11_isr, [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, [NVIC_TIM2_IRQ] = tim2_isr, [NVIC_TIM3_IRQ] = tim3_isr, [NVIC_TIM4_IRQ] = tim4_isr, [NVIC_I2C1_EV_IRQ] = i2c1_ev_isr, [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, [NVIC_I2C2_EV_IRQ] = i2c2_ev_isr, [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, [NVIC_SPI1_IRQ] = spi1_isr, [NVIC_SPI2_IRQ] = spi2_isr, [NVIC_USART1_IRQ] = usart1_isr, [NVIC_USART2_IRQ] = usart2_isr, [NVIC_USART3_IRQ] = usart3_isr, [NVIC_EXTI15_10_IRQ] = exti15_10_isr, [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, [NVIC_USB_FS_WKUP_IRQ] = usb_fs_wkup_isr, [NVIC_TIM8_BRK_TIM12_IRQ] = tim8_brk_tim12_isr, [NVIC_TIM8_UP_TIM13_IRQ] = tim8_up_tim13_isr, [NVIC_TIM8_TRG_COM_TIM14_IRQ] = tim8_trg_com_tim14_isr, [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, [NVIC_DMA1_STREAM7_IRQ] = dma1_stream7_isr, [NVIC_FSMC_IRQ] = fsmc_isr, [NVIC_SDIO_IRQ] = sdio_isr, [NVIC_TIM5_IRQ] = tim5_isr, [NVIC_SPI3_IRQ] = spi3_isr, [NVIC_UART4_IRQ] = uart4_isr, [NVIC_UART5_IRQ] = uart5_isr, [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, [NVIC_TIM7_IRQ] = tim7_isr, [NVIC_DMA2_STREAM0_IRQ] = dma2_stream0_isr, [NVIC_DMA2_STREAM1_IRQ] = dma2_stream1_isr, [NVIC_DMA2_STREAM2_IRQ] = dma2_stream2_isr, [NVIC_DMA2_STREAM3_IRQ] = dma2_stream3_isr, [NVIC_DMA2_STREAM4_IRQ] = dma2_stream4_isr, [NVIC_ETH_IRQ] = eth_isr, [NVIC_ETH_WKUP_IRQ] = eth_wkup_isr, [NVIC_CAN2_TX_IRQ] = can2_tx_isr, [NVIC_CAN2_RX0_IRQ] = can2_rx0_isr, [NVIC_CAN2_RX1_IRQ] = can2_rx1_isr, [NVIC_CAN2_SCE_IRQ] = can2_sce_isr, [NVIC_OTG_FS_IRQ] = otg_fs_isr, [NVIC_DMA2_STREAM5_IRQ] = dma2_stream5_isr, [NVIC_DMA2_STREAM6_IRQ] = dma2_stream6_isr, [NVIC_DMA2_STREAM7_IRQ] = dma2_stream7_isr, [NVIC_USART6_IRQ] = usart6_isr, [NVIC_I2C3_EV_IRQ] = i2c3_ev_isr, [NVIC_I2C3_ER_IRQ] = i2c3_er_isr, [NVIC_OTG_HS_EP1_OUT_IRQ] = otg_hs_ep1_out_isr, [NVIC_OTG_HS_EP1_IN_IRQ] = otg_hs_ep1_in_isr, [NVIC_OTG_HS_WKUP_IRQ] = otg_hs_wkup_isr, [NVIC_OTG_HS_IRQ] = otg_hs_isr, [NVIC_DCMI_IRQ] = dcmi_isr, [NVIC_CRYP_IRQ] = cryp_isr, [NVIC_HASH_RNG_IRQ] = hash_rng_isr, [NVIC_FPU_IRQ] = fpu_isr, [NVIC_UART7_IRQ] = uart7_isr, [NVIC_UART8_IRQ] = uart8_isr, [NVIC_SPI4_IRQ] = spi4_isr, [NVIC_SPI5_IRQ] = spi5_isr, [NVIC_SPI6_IRQ] = spi6_isr, [NVIC_SAI1_IRQ] = sai1_isr, [NVIC_LCD_TFT_IRQ] = lcd_tft_isr, [NVIC_LCD_TFT_ERR_IRQ] = lcd_tft_err_isr, [NVIC_DMA2D_IRQ] = dma2d_isr__LFRACT_EPSILON__ 0x1P-31LRNVIC_SPI4_IRQ 84__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SCB_CFSR_BFARVALID (1 << 15)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))NVIC_STIR MMIO32(STIR_BASE)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)SCB_AIRCR_SYSRESETREQ (1 << 2)SCB_ICSR_ISRPENDING (1 << 22)NVIC_DMA1_STREAM3_IRQ 14SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_SHCSR_USGFAULTACT (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__UINT_LEAST8_MAX __UINT_LEAST8_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)INT_FAST32_MIN (-INT_FAST32_MAX - 1)SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2SCB_CTR_CWG_SHIFT 24__FLT32_DIG__ 6INT_LEAST16_MAXSCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)BIT15 (1<<15)NVIC_SYSTICK_IRQ -1NVIC_OTG_HS_WKUP_IRQ 76BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXNVIC_HASH_RNG_IRQ 80__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0SCB_CPACR_PRIV 1UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234NVIC_HARD_FAULT_IRQ -13SCB_CTR_DMINLINE_MASK 0x1f__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_ICSR_VECTACTIVE_LSB 0long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CFSR_INVPC (1 << 18)__UHQ_IBIT__ 0INT_LEAST8_MINSCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)_data_loadaddr__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128LIBOPENCM3_SCB_H SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffNVIC_CAN2_RX0_IRQ 64NVIC_TIM2_IRQ 28PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2__FLT32_DECIMAL_DIG__ 9NVIC_DMA2_STREAM3_IRQ 59__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKNVIC_LCD_TFT_IRQ 88UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_PVD_IRQ 1NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))SCB_BPIALL MMIO32(SCB_BASE + 0x278)WCHAR_MINBEGIN_DECLS __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1destSCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0SCB_SHPR_PRI_14_PENDSV 10SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31_datainitial_sp_value__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2NVIC_OTG_HS_IRQ 77NVIC_TIM1_BRK_TIM9_IRQ 24SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXNVIC_EXTI15_10_IRQ 40NVIC_TIM8_UP_TIM13_IRQ 44__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICNVIC_SV_CALL_IRQ -5__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1NVIC_I2C3_ER_IRQ 73NVIC_TIM8_CC_IRQ 46__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_Creserved_x001c__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intNVIC_NMI_IRQ -14UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRNVIC_TAMP_STAMP_IRQ 2__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLSCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)__LDBL_MIN_10_EXP__ (-307)systickSCB_CTR_CWG_MASK 0xfTPIU_BASE (PPBI_BASE + 0x40000)SCB_CTR_IMINLINE_SHIFT 0__LDBL_MIN__ 2.2250738585072014e-308LSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16funcp_tCORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)SCB_SHPR_PRI_15_SYSTICK 11short intSCB_CFSR_UNSTKERR (1 << 11)__UINT16_C(c) cNVIC_DMA2_STREAM5_IRQ 68__UDA_IBIT__ 32UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCsv_call__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53reserved_x0034BIT5 (1<<5)BIT1 (1<<1)INT8_CINT_LEAST32_MAXSCB_CFSR_MSTKERR (1 << 4)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)NVIC_FSMC_IRQ 48__INT16_MAX__ 0x7fffSCB_SHCSR_MEMFAULTPENDED (1 << 13)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCB_CCR_BP (1 << 18)NVIC_DMA1_STREAM7_IRQ 47__QQ_FBIT__ 7SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__ULLACCUM_IBIT__ 32NVIC_CAN1_SCE_IRQ 22SCB_VTOR MMIO32(SCB_BASE + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)NVIC_DMA1_STREAM6_IRQ 17__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17SCB_HFSR MMIO32(SCB_BASE + 0x2C)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SCB_CFSR_DIVBYZERO (1 << 25)__FLT32X_HAS_DENORM__ 1NVIC_SPI3_IRQ 51__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32NVIC_FLASH_IRQ 4SCB_HFSR_DEBUG_VT (1 << 31)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODDEBUG_MONITOR_IRQ -4SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + ((iabr_id) * 4))__ARM_PCS_VFP 1SCB_CCR_STKALIGN (1 << 9)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H NVIC_TIM4_IRQ 30INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64NVIC_USART6_IRQ 71__LLFRACT_IBIT__ 0SCB_SHPR_PRI_10_RESERVED 6uint32_tBIT12 (1<<12)SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)NVIC_RTC_WKUP_IRQ 3MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1__ARM_FP 4SCB_CTR_IMINLINE_MASK 0xf__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKSCB_CPUID_PARTNO_LSB 4__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXNVIC_DMA2_STREAM1_IRQ 57BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1SCB_CFSR_UNALIGNED (1 << 24)UINTMAX_CSCB_SHPR_PRI_7_RESERVED 3INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1NVIC_ETH_WKUP_IRQ 62__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUreset_handler__ARM_ARCH__LONG_MAX__ 0x7fffffffLSCB_CPACR_FULL 3NVIC_UART8_IRQ 83SCB_CFSR_MMARVALID (1 << 7)SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)SCB_AIRCR_VECTKEYSTAT_LSB 16__ARM_FEATURE_LDREX 7PTRDIFF_MAXNVIC_TIM1_UP_TIM10_IRQ 25SCB_CCR_BFHFNMIGN (1 << 8)NVIC_DMA2_STREAM4_IRQ 60__LLFRACT_EPSILON__ 0x1P-63LLRNVIC_DMA2D_IRQ 90__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32NVIC_EXTI9_5_IRQ 23WINT_MAX__INT16_C(c) cSCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)__fini_array_startSCB_CTR_ERG_SHIFT 20SCB_SHCSR_SVCALLACT (1 << 7)SCB_SHPR_PRI_11_SVCALL 7__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)NVIC_EXTI1_IRQ 7__UINTMAX_MAX__ 0xffffffffffffffffULLSCB_ICSR_PENDSVCLR (1 << 27)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0vector_table_entry_tINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int__INT_FAST8_WIDTH__ 32__ARM_FEATURE_CDE_COPROCUINT32_CNVIC_DMA1_STREAM2_IRQ 13GCC: (15:12.2.rel1-1) 12.2.1 20221205 |  AA3aeabi)7E-M M  "       x 02 "$&(*,.47k0^ 36  " " " " " #" 3" ?" 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