Timing Advance mismatch: expected 2, but received 0 PCU_Tests.ttcn:7640 PCU_Tests control part PCU_Tests.ttcn:572 TC_ta_ul_ack_nack_first_block testcase Timing Advance value doesn't match PCU_Tests.ttcn:7641 PCU_Tests control part PCU_Tests.ttcn:607 TC_ta_idle_dl_tbf_ass testcase Failed to match Timing Advance Index for #0 PCU_Tests.ttcn:7642 PCU_Tests control part PCU_Tests.ttcn:807 TC_ta_ptcch_ul_multi_tbf testcase Expected 8 PDCH slots allocated but got 4 PCU_Tests.ttcn:7717 PCU_Tests control part PCU_Tests.ttcn:3442 TC_dl_multislot_tbf_ms_class_from_sgsn testcase Expected 1 PDCH slots allocated but got 4 PCU_Tests.ttcn:7718 PCU_Tests control part PCU_Tests.ttcn:3512 TC_dl_multislot_tbf_ms_class_unknown testcase Metric failed expectation { name := "TTCN3.bts.0.pdch.all_allocated", val := 2, mtype := "c", srate := omit } vs { name := "TTCN3.bts.0.pdch.all_allocated", mtype := "c", min := 1, max := 1 } PCU_Tests.ttcn:7762 PCU_Tests control part PCU_Tests.ttcn:7632 TC_ratectr_all_available_allocated testcase