Timing Advance mismatch: expected 2, but received 0 PCU_Tests.ttcn:MASKED PCU_Tests control part PCU_Tests.ttcn:MASKED TC_ta_ul_ack_nack_first_block testcase Timing Advance value doesn't match PCU_Tests.ttcn:MASKED PCU_Tests control part PCU_Tests.ttcn:MASKED TC_ta_idle_dl_tbf_ass testcase Failed to match Timing Advance Index for #0 PCU_Tests.ttcn:MASKED PCU_Tests control part PCU_Tests.ttcn:MASKED TC_ta_ptcch_ul_multi_tbf testcase Expected 8 PDCH slots allocated but got 4 PCU_Tests.ttcn:MASKED PCU_Tests control part PCU_Tests.ttcn:MASKED TC_dl_multislot_tbf_ms_class_from_sgsn testcase Expected 1 PDCH slots allocated but got 4 PCU_Tests.ttcn:MASKED PCU_Tests control part PCU_Tests.ttcn:MASKED TC_dl_multislot_tbf_ms_class_unknown testcase